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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s3 4; CHECK: ********** MI Scheduling **********5; We need second, post-ra scheduling to have VSTM instruction combined from single-stores6; CHECK: ********** MI Scheduling **********7; CHECK: schedule starting8; CHECK: VSTMDIA9; CHECK: rdefs left10; CHECK-NEXT: Latency : 211 12%bigVec = type [2 x double]13 14@var = global %bigVec zeroinitializer15 16define void @bar(ptr %ptr) {17 18 %tmp = load %bigVec, ptr %ptr19 store %bigVec %tmp, ptr @var20 21 ret void22}23 24