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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED3; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52plus -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=R52_SCHED4; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC5;6; Check the latency for instructions for both generic and cortex-r52.7; Cortex-r52 machine model will cause the div to be sceduled before eor8; as div takes more cycles to compute than eor.9;10; CHECK: ********** MI Scheduling **********11; CHECK: foo:%bb.0 entry12; CHECK: EORrr13; GENERIC: Latency : 114; R52_SCHED: Latency : 315; CHECK: MLA16; GENERIC: Latency : 217; R52_SCHED: Latency : 418; CHECK: SDIV19; GENERIC: Latency : 020; R52_SCHED: Latency : 821; CHECK: ** Final schedule for %bb.0 ***22; GENERIC: EORrr23; GENERIC: SDIV24; R52_SCHED: SDIV25; R52_SCHED: EORrr26; CHECK: ********** INTERVALS **********27 28target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"29target triple = "armv8r-arm-none-eabi"30 31; Function Attrs: norecurse nounwind readnone32define hidden i32 @foo(i32 %a, i32 %b, i32 %c) local_unnamed_addr #0 {33entry:34 %xor = xor i32 %c, %b35 %mul = mul nsw i32 %xor, %c36 %add = add nsw i32 %mul, %a37 %div = sdiv i32 %a, %b38 %sub = sub i32 %add, %div39 ret i32 %sub40}41