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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple armv7-linux-gnueabihf -mattr=+neon | FileCheck %s3 4; This test checks the @llvm.cttz.* intrinsics for vectors.5 6declare <1 x i8> @llvm.cttz.v1i8(<1 x i8>, i1)7declare <2 x i8> @llvm.cttz.v2i8(<2 x i8>, i1)8declare <4 x i8> @llvm.cttz.v4i8(<4 x i8>, i1)9declare <8 x i8> @llvm.cttz.v8i8(<8 x i8>, i1)10declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)11 12declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)13declare <2 x i16> @llvm.cttz.v2i16(<2 x i16>, i1)14declare <4 x i16> @llvm.cttz.v4i16(<4 x i16>, i1)15declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)16 17declare <1 x i32> @llvm.cttz.v1i32(<1 x i32>, i1)18declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)19declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)20 21declare <1 x i64> @llvm.cttz.v1i64(<1 x i64>, i1)22declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)23 24;------------------------------------------------------------------------------25 26define void @test_v1i8(ptr %p) {27; CHECK-LABEL: test_v1i8:28; CHECK: @ %bb.0:29; CHECK-NEXT: ldrb r1, [r0]30; CHECK-NEXT: orr r1, r1, #25631; CHECK-NEXT: rbit r1, r132; CHECK-NEXT: clz r1, r133; CHECK-NEXT: strb r1, [r0]34; CHECK-NEXT: bx lr35 %a = load <1 x i8>, ptr %p36 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 false)37 store <1 x i8> %tmp, ptr %p38 ret void39}40 41define void @test_v2i8(ptr %p) {42; CHECK-LABEL: test_v2i8:43; CHECK: @ %bb.0:44; CHECK-NEXT: vld1.16 {d16[0]}, [r0:16]45; CHECK-NEXT: vmovl.u8 q8, d1646; CHECK-NEXT: vmovl.u16 q8, d1647; CHECK-NEXT: vorr.i32 d16, #0x10048; CHECK-NEXT: vneg.s32 d18, d1649; CHECK-NEXT: vand d16, d16, d1850; CHECK-NEXT: vmov.i32 d17, #0x1f51; CHECK-NEXT: vclz.i32 d16, d1652; CHECK-NEXT: vsub.i32 d16, d17, d1653; CHECK-NEXT: vmov.32 r1, d16[1]54; CHECK-NEXT: vmov.32 r2, d16[0]55; CHECK-NEXT: strb r1, [r0, #1]56; CHECK-NEXT: strb r2, [r0]57; CHECK-NEXT: bx lr58 %a = load <2 x i8>, ptr %p59 %tmp = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %a, i1 false)60 store <2 x i8> %tmp, ptr %p61 ret void62}63 64define void @test_v4i8(ptr %p) {65; CHECK-LABEL: test_v4i8:66; CHECK: @ %bb.0:67; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]68; CHECK-NEXT: vmovl.u8 q8, d1669; CHECK-NEXT: vorr.i16 d16, #0x10070; CHECK-NEXT: vneg.s16 d18, d1671; CHECK-NEXT: vand d16, d16, d1872; CHECK-NEXT: vmov.i16 d17, #0xf73; CHECK-NEXT: vclz.i16 d16, d1674; CHECK-NEXT: vsub.i16 d16, d17, d1675; CHECK-NEXT: vuzp.8 d16, d1776; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]77; CHECK-NEXT: bx lr78 %a = load <4 x i8>, ptr %p79 %tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 false)80 store <4 x i8> %tmp, ptr %p81 ret void82}83 84define void @test_v8i8(ptr %p) {85; CHECK-LABEL: test_v8i8:86; CHECK: @ %bb.0:87; CHECK-NEXT: vldr d16, [r0]88; CHECK-NEXT: vmov.i8 d18, #0x189; CHECK-NEXT: vneg.s8 d17, d1690; CHECK-NEXT: vand d16, d16, d1791; CHECK-NEXT: vsub.i8 d16, d16, d1892; CHECK-NEXT: vcnt.8 d16, d1693; CHECK-NEXT: vstr d16, [r0]94; CHECK-NEXT: bx lr95 %a = load <8 x i8>, ptr %p96 %tmp = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 false)97 store <8 x i8> %tmp, ptr %p98 ret void99}100 101define void @test_v16i8(ptr %p) {102; CHECK-LABEL: test_v16i8:103; CHECK: @ %bb.0:104; CHECK-NEXT: vld1.64 {d16, d17}, [r0]105; CHECK-NEXT: vmov.i8 q10, #0x1106; CHECK-NEXT: vneg.s8 q9, q8107; CHECK-NEXT: vand q8, q8, q9108; CHECK-NEXT: vsub.i8 q8, q8, q10109; CHECK-NEXT: vcnt.8 q8, q8110; CHECK-NEXT: vst1.64 {d16, d17}, [r0]111; CHECK-NEXT: bx lr112 %a = load <16 x i8>, ptr %p113 %tmp = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false)114 store <16 x i8> %tmp, ptr %p115 ret void116}117 118define void @test_v1i16(ptr %p) {119; CHECK-LABEL: test_v1i16:120; CHECK: @ %bb.0:121; CHECK-NEXT: ldrh r1, [r0]122; CHECK-NEXT: orr r1, r1, #65536123; CHECK-NEXT: rbit r1, r1124; CHECK-NEXT: clz r1, r1125; CHECK-NEXT: strh r1, [r0]126; CHECK-NEXT: bx lr127 %a = load <1 x i16>, ptr %p128 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)129 store <1 x i16> %tmp, ptr %p130 ret void131}132 133define void @test_v2i16(ptr %p) {134; CHECK-LABEL: test_v2i16:135; CHECK: @ %bb.0:136; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]137; CHECK-NEXT: vmovl.u16 q8, d16138; CHECK-NEXT: vorr.i32 d16, #0x10000139; CHECK-NEXT: vneg.s32 d18, d16140; CHECK-NEXT: vand d16, d16, d18141; CHECK-NEXT: vmov.i32 d17, #0x1f142; CHECK-NEXT: vclz.i32 d16, d16143; CHECK-NEXT: vsub.i32 d16, d17, d16144; CHECK-NEXT: vuzp.16 d16, d17145; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]146; CHECK-NEXT: bx lr147 %a = load <2 x i16>, ptr %p148 %tmp = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %a, i1 false)149 store <2 x i16> %tmp, ptr %p150 ret void151}152 153define void @test_v4i16(ptr %p) {154; CHECK-LABEL: test_v4i16:155; CHECK: @ %bb.0:156; CHECK-NEXT: vldr d16, [r0]157; CHECK-NEXT: vmov.i16 d18, #0x1158; CHECK-NEXT: vneg.s16 d17, d16159; CHECK-NEXT: vand d16, d16, d17160; CHECK-NEXT: vsub.i16 d16, d16, d18161; CHECK-NEXT: vcnt.8 d16, d16162; CHECK-NEXT: vpaddl.u8 d16, d16163; CHECK-NEXT: vstr d16, [r0]164; CHECK-NEXT: bx lr165 %a = load <4 x i16>, ptr %p166 %tmp = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 false)167 store <4 x i16> %tmp, ptr %p168 ret void169}170 171define void @test_v8i16(ptr %p) {172; CHECK-LABEL: test_v8i16:173; CHECK: @ %bb.0:174; CHECK-NEXT: vld1.64 {d16, d17}, [r0]175; CHECK-NEXT: vmov.i16 q10, #0x1176; CHECK-NEXT: vneg.s16 q9, q8177; CHECK-NEXT: vand q8, q8, q9178; CHECK-NEXT: vsub.i16 q8, q8, q10179; CHECK-NEXT: vcnt.8 q8, q8180; CHECK-NEXT: vpaddl.u8 q8, q8181; CHECK-NEXT: vst1.64 {d16, d17}, [r0]182; CHECK-NEXT: bx lr183 %a = load <8 x i16>, ptr %p184 %tmp = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false)185 store <8 x i16> %tmp, ptr %p186 ret void187}188 189define void @test_v1i32(ptr %p) {190; CHECK-LABEL: test_v1i32:191; CHECK: @ %bb.0:192; CHECK-NEXT: ldr r1, [r0]193; CHECK-NEXT: rbit r1, r1194; CHECK-NEXT: clz r1, r1195; CHECK-NEXT: str r1, [r0]196; CHECK-NEXT: bx lr197 %a = load <1 x i32>, ptr %p198 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 false)199 store <1 x i32> %tmp, ptr %p200 ret void201}202 203define void @test_v2i32(ptr %p) {204; CHECK-LABEL: test_v2i32:205; CHECK: @ %bb.0:206; CHECK-NEXT: vldr d16, [r0]207; CHECK-NEXT: vmov.i32 d18, #0x1208; CHECK-NEXT: vneg.s32 d17, d16209; CHECK-NEXT: vand d16, d16, d17210; CHECK-NEXT: vsub.i32 d16, d16, d18211; CHECK-NEXT: vcnt.8 d16, d16212; CHECK-NEXT: vpaddl.u8 d16, d16213; CHECK-NEXT: vpaddl.u16 d16, d16214; CHECK-NEXT: vstr d16, [r0]215; CHECK-NEXT: bx lr216 %a = load <2 x i32>, ptr %p217 %tmp = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 false)218 store <2 x i32> %tmp, ptr %p219 ret void220}221 222define void @test_v4i32(ptr %p) {223; CHECK-LABEL: test_v4i32:224; CHECK: @ %bb.0:225; CHECK-NEXT: vld1.64 {d16, d17}, [r0]226; CHECK-NEXT: vmov.i32 q10, #0x1227; CHECK-NEXT: vneg.s32 q9, q8228; CHECK-NEXT: vand q8, q8, q9229; CHECK-NEXT: vsub.i32 q8, q8, q10230; CHECK-NEXT: vcnt.8 q8, q8231; CHECK-NEXT: vpaddl.u8 q8, q8232; CHECK-NEXT: vpaddl.u16 q8, q8233; CHECK-NEXT: vst1.64 {d16, d17}, [r0]234; CHECK-NEXT: bx lr235 %a = load <4 x i32>, ptr %p236 %tmp = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false)237 store <4 x i32> %tmp, ptr %p238 ret void239}240 241define void @test_v1i64(ptr %p) {242; CHECK-LABEL: test_v1i64:243; CHECK: @ %bb.0:244; CHECK-NEXT: vmov.i32 d16, #0x0245; CHECK-NEXT: vldr d17, [r0]246; CHECK-NEXT: vmov.i64 d18, #0xffffffffffffffff247; CHECK-NEXT: vsub.i64 d16, d16, d17248; CHECK-NEXT: vand d16, d17, d16249; CHECK-NEXT: vadd.i64 d16, d16, d18250; CHECK-NEXT: vcnt.8 d16, d16251; CHECK-NEXT: vpaddl.u8 d16, d16252; CHECK-NEXT: vpaddl.u16 d16, d16253; CHECK-NEXT: vpaddl.u32 d16, d16254; CHECK-NEXT: vstr d16, [r0]255; CHECK-NEXT: bx lr256 %a = load <1 x i64>, ptr %p257 %tmp = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 false)258 store <1 x i64> %tmp, ptr %p259 ret void260}261 262define void @test_v2i64(ptr %p) {263; CHECK-LABEL: test_v2i64:264; CHECK: @ %bb.0:265; CHECK-NEXT: vmov.i32 q8, #0x0266; CHECK-NEXT: vld1.64 {d18, d19}, [r0]267; CHECK-NEXT: vmov.i64 q10, #0xffffffffffffffff268; CHECK-NEXT: vsub.i64 q8, q8, q9269; CHECK-NEXT: vand q8, q9, q8270; CHECK-NEXT: vadd.i64 q8, q8, q10271; CHECK-NEXT: vcnt.8 q8, q8272; CHECK-NEXT: vpaddl.u8 q8, q8273; CHECK-NEXT: vpaddl.u16 q8, q8274; CHECK-NEXT: vpaddl.u32 q8, q8275; CHECK-NEXT: vst1.64 {d16, d17}, [r0]276; CHECK-NEXT: bx lr277 %a = load <2 x i64>, ptr %p278 %tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)279 store <2 x i64> %tmp, ptr %p280 ret void281}282 283;------------------------------------------------------------------------------284 285define void @test_v1i8_zero_undef(ptr %p) {286; CHECK-LABEL: test_v1i8_zero_undef:287; CHECK: @ %bb.0:288; CHECK-NEXT: ldrb r1, [r0]289; CHECK-NEXT: rbit r1, r1290; CHECK-NEXT: clz r1, r1291; CHECK-NEXT: strb r1, [r0]292; CHECK-NEXT: bx lr293 %a = load <1 x i8>, ptr %p294 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 true)295 store <1 x i8> %tmp, ptr %p296 ret void297}298 299define void @test_v2i8_zero_undef(ptr %p) {300; CHECK-LABEL: test_v2i8_zero_undef:301; CHECK: @ %bb.0:302; CHECK-NEXT: vld1.16 {d16[0]}, [r0:16]303; CHECK-NEXT: vmovl.u8 q8, d16304; CHECK-NEXT: vmovl.u16 q8, d16305; CHECK-NEXT: vneg.s32 d18, d16306; CHECK-NEXT: vand d16, d16, d18307; CHECK-NEXT: vmov.i32 d17, #0x1f308; CHECK-NEXT: vclz.i32 d16, d16309; CHECK-NEXT: vsub.i32 d16, d17, d16310; CHECK-NEXT: vmov.32 r1, d16[1]311; CHECK-NEXT: vmov.32 r2, d16[0]312; CHECK-NEXT: strb r1, [r0, #1]313; CHECK-NEXT: strb r2, [r0]314; CHECK-NEXT: bx lr315 %a = load <2 x i8>, ptr %p316 %tmp = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %a, i1 true)317 store <2 x i8> %tmp, ptr %p318 ret void319}320 321define void @test_v4i8_zero_undef(ptr %p) {322; CHECK-LABEL: test_v4i8_zero_undef:323; CHECK: @ %bb.0:324; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]325; CHECK-NEXT: vmovl.u8 q8, d16326; CHECK-NEXT: vneg.s16 d18, d16327; CHECK-NEXT: vand d16, d16, d18328; CHECK-NEXT: vmov.i16 d17, #0xf329; CHECK-NEXT: vclz.i16 d16, d16330; CHECK-NEXT: vsub.i16 d16, d17, d16331; CHECK-NEXT: vuzp.8 d16, d17332; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]333; CHECK-NEXT: bx lr334 %a = load <4 x i8>, ptr %p335 %tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 true)336 store <4 x i8> %tmp, ptr %p337 ret void338}339 340define void @test_v8i8_zero_undef(ptr %p) {341; CHECK-LABEL: test_v8i8_zero_undef:342; CHECK: @ %bb.0:343; CHECK-NEXT: vldr d16, [r0]344; CHECK-NEXT: vmov.i8 d18, #0x1345; CHECK-NEXT: vneg.s8 d17, d16346; CHECK-NEXT: vand d16, d16, d17347; CHECK-NEXT: vsub.i8 d16, d16, d18348; CHECK-NEXT: vcnt.8 d16, d16349; CHECK-NEXT: vstr d16, [r0]350; CHECK-NEXT: bx lr351 %a = load <8 x i8>, ptr %p352 %tmp = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 true)353 store <8 x i8> %tmp, ptr %p354 ret void355}356 357define void @test_v16i8_zero_undef(ptr %p) {358; CHECK-LABEL: test_v16i8_zero_undef:359; CHECK: @ %bb.0:360; CHECK-NEXT: vld1.64 {d16, d17}, [r0]361; CHECK-NEXT: vmov.i8 q10, #0x1362; CHECK-NEXT: vneg.s8 q9, q8363; CHECK-NEXT: vand q8, q8, q9364; CHECK-NEXT: vsub.i8 q8, q8, q10365; CHECK-NEXT: vcnt.8 q8, q8366; CHECK-NEXT: vst1.64 {d16, d17}, [r0]367; CHECK-NEXT: bx lr368 %a = load <16 x i8>, ptr %p369 %tmp = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 true)370 store <16 x i8> %tmp, ptr %p371 ret void372}373 374define void @test_v1i16_zero_undef(ptr %p) {375; CHECK-LABEL: test_v1i16_zero_undef:376; CHECK: @ %bb.0:377; CHECK-NEXT: ldrh r1, [r0]378; CHECK-NEXT: rbit r1, r1379; CHECK-NEXT: clz r1, r1380; CHECK-NEXT: strh r1, [r0]381; CHECK-NEXT: bx lr382 %a = load <1 x i16>, ptr %p383 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)384 store <1 x i16> %tmp, ptr %p385 ret void386}387 388define void @test_v2i16_zero_undef(ptr %p) {389; CHECK-LABEL: test_v2i16_zero_undef:390; CHECK: @ %bb.0:391; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]392; CHECK-NEXT: vmovl.u16 q8, d16393; CHECK-NEXT: vneg.s32 d18, d16394; CHECK-NEXT: vand d16, d16, d18395; CHECK-NEXT: vmov.i32 d17, #0x1f396; CHECK-NEXT: vclz.i32 d16, d16397; CHECK-NEXT: vsub.i32 d16, d17, d16398; CHECK-NEXT: vuzp.16 d16, d17399; CHECK-NEXT: vst1.32 {d16[0]}, [r0:32]400; CHECK-NEXT: bx lr401 %a = load <2 x i16>, ptr %p402 %tmp = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %a, i1 true)403 store <2 x i16> %tmp, ptr %p404 ret void405}406 407define void @test_v4i16_zero_undef(ptr %p) {408; CHECK-LABEL: test_v4i16_zero_undef:409; CHECK: @ %bb.0:410; CHECK-NEXT: vldr d16, [r0]411; CHECK-NEXT: vneg.s16 d17, d16412; CHECK-NEXT: vand d16, d16, d17413; CHECK-NEXT: vmov.i16 d17, #0xf414; CHECK-NEXT: vclz.i16 d16, d16415; CHECK-NEXT: vsub.i16 d16, d17, d16416; CHECK-NEXT: vstr d16, [r0]417; CHECK-NEXT: bx lr418 %a = load <4 x i16>, ptr %p419 %tmp = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 true)420 store <4 x i16> %tmp, ptr %p421 ret void422}423 424define void @test_v8i16_zero_undef(ptr %p) {425; CHECK-LABEL: test_v8i16_zero_undef:426; CHECK: @ %bb.0:427; CHECK-NEXT: vld1.64 {d16, d17}, [r0]428; CHECK-NEXT: vneg.s16 q9, q8429; CHECK-NEXT: vand q8, q8, q9430; CHECK-NEXT: vmov.i16 q9, #0xf431; CHECK-NEXT: vclz.i16 q8, q8432; CHECK-NEXT: vsub.i16 q8, q9, q8433; CHECK-NEXT: vst1.64 {d16, d17}, [r0]434; CHECK-NEXT: bx lr435 %a = load <8 x i16>, ptr %p436 %tmp = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 true)437 store <8 x i16> %tmp, ptr %p438 ret void439}440 441define void @test_v1i32_zero_undef(ptr %p) {442; CHECK-LABEL: test_v1i32_zero_undef:443; CHECK: @ %bb.0:444; CHECK-NEXT: ldr r1, [r0]445; CHECK-NEXT: rbit r1, r1446; CHECK-NEXT: clz r1, r1447; CHECK-NEXT: str r1, [r0]448; CHECK-NEXT: bx lr449 %a = load <1 x i32>, ptr %p450 %tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 true)451 store <1 x i32> %tmp, ptr %p452 ret void453}454 455define void @test_v2i32_zero_undef(ptr %p) {456; CHECK-LABEL: test_v2i32_zero_undef:457; CHECK: @ %bb.0:458; CHECK-NEXT: vldr d16, [r0]459; CHECK-NEXT: vneg.s32 d17, d16460; CHECK-NEXT: vand d16, d16, d17461; CHECK-NEXT: vmov.i32 d17, #0x1f462; CHECK-NEXT: vclz.i32 d16, d16463; CHECK-NEXT: vsub.i32 d16, d17, d16464; CHECK-NEXT: vstr d16, [r0]465; CHECK-NEXT: bx lr466 %a = load <2 x i32>, ptr %p467 %tmp = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 true)468 store <2 x i32> %tmp, ptr %p469 ret void470}471 472define void @test_v4i32_zero_undef(ptr %p) {473; CHECK-LABEL: test_v4i32_zero_undef:474; CHECK: @ %bb.0:475; CHECK-NEXT: vld1.64 {d16, d17}, [r0]476; CHECK-NEXT: vneg.s32 q9, q8477; CHECK-NEXT: vand q8, q8, q9478; CHECK-NEXT: vmov.i32 q9, #0x1f479; CHECK-NEXT: vclz.i32 q8, q8480; CHECK-NEXT: vsub.i32 q8, q9, q8481; CHECK-NEXT: vst1.64 {d16, d17}, [r0]482; CHECK-NEXT: bx lr483 %a = load <4 x i32>, ptr %p484 %tmp = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true)485 store <4 x i32> %tmp, ptr %p486 ret void487}488 489define void @test_v1i64_zero_undef(ptr %p) {490; CHECK-LABEL: test_v1i64_zero_undef:491; CHECK: @ %bb.0:492; CHECK-NEXT: vmov.i32 d16, #0x0493; CHECK-NEXT: vldr d17, [r0]494; CHECK-NEXT: vmov.i64 d18, #0xffffffffffffffff495; CHECK-NEXT: vsub.i64 d16, d16, d17496; CHECK-NEXT: vand d16, d17, d16497; CHECK-NEXT: vadd.i64 d16, d16, d18498; CHECK-NEXT: vcnt.8 d16, d16499; CHECK-NEXT: vpaddl.u8 d16, d16500; CHECK-NEXT: vpaddl.u16 d16, d16501; CHECK-NEXT: vpaddl.u32 d16, d16502; CHECK-NEXT: vstr d16, [r0]503; CHECK-NEXT: bx lr504 %a = load <1 x i64>, ptr %p505 %tmp = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 true)506 store <1 x i64> %tmp, ptr %p507 ret void508}509 510define void @test_v2i64_zero_undef(ptr %p) {511; CHECK-LABEL: test_v2i64_zero_undef:512; CHECK: @ %bb.0:513; CHECK-NEXT: vmov.i32 q8, #0x0514; CHECK-NEXT: vld1.64 {d18, d19}, [r0]515; CHECK-NEXT: vmov.i64 q10, #0xffffffffffffffff516; CHECK-NEXT: vsub.i64 q8, q8, q9517; CHECK-NEXT: vand q8, q9, q8518; CHECK-NEXT: vadd.i64 q8, q8, q10519; CHECK-NEXT: vcnt.8 q8, q8520; CHECK-NEXT: vpaddl.u8 q8, q8521; CHECK-NEXT: vpaddl.u16 q8, q8522; CHECK-NEXT: vpaddl.u32 q8, q8523; CHECK-NEXT: vst1.64 {d16, d17}, [r0]524; CHECK-NEXT: bx lr525 %a = load <2 x i64>, ptr %p526 %tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)527 store <2 x i64> %tmp, ptr %p528 ret void529}530