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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple armv7 %s -o - | FileCheck %s3 4define float @f(ptr nocapture %in) {5; CHECK-LABEL: f:6; CHECK: @ %bb.0:7; CHECK-NEXT: vld1.16 {d16}, [r0:64]8; CHECK-NEXT: vmovl.u16 q8, d169; CHECK-NEXT: vcvt.f32.u32 q0, q810; CHECK-NEXT: vadd.f32 s4, s0, s111; CHECK-NEXT: vadd.f32 s0, s4, s212; CHECK-NEXT: vmov r0, s013; CHECK-NEXT: bx lr14 %1 = load <4 x i16>, ptr %in15 %2 = uitofp <4 x i16> %1 to <4 x float>16 %3 = extractelement <4 x float> %2, i32 017 %4 = extractelement <4 x float> %2, i32 118 %5 = extractelement <4 x float> %2, i32 219 20 %6 = fadd float %3, %421 %7 = fadd float %6, %522 23 ret float %724}25 26define float @g(ptr nocapture %in) {27; CHECK-LABEL: g:28; CHECK: @ %bb.0:29; CHECK-NEXT: vldr d16, [r0]30; CHECK-NEXT: vmov.u16 r0, d16[0]31; CHECK-NEXT: vmov s0, r032; CHECK-NEXT: vcvt.f32.u32 s0, s033; CHECK-NEXT: vmov r0, s034; CHECK-NEXT: bx lr35 %1 = load <4 x i16>, ptr %in36 %2 = extractelement <4 x i16> %1, i32 037 %3 = uitofp i16 %2 to float38 ret float %339}40 41; Make sure we generate zext from <4 x i8> to <4 x 32>.42define <4 x i32> @h(ptr %in) {43; CHECK-LABEL: h:44; CHECK: @ %bb.0:45; CHECK-NEXT: vld1.32 {d16[0]}, [r0:32]46; CHECK-NEXT: vmovl.u8 q8, d1647; CHECK-NEXT: vmov.u16 r0, d16[0]48; CHECK-NEXT: vmov.u16 r1, d16[1]49; CHECK-NEXT: vmov.u16 r2, d16[2]50; CHECK-NEXT: vmov.u16 r3, d16[3]51; CHECK-NEXT: uxtb r0, r052; CHECK-NEXT: uxtb r1, r153; CHECK-NEXT: uxtb r2, r254; CHECK-NEXT: uxtb r3, r355; CHECK-NEXT: bx lr56 %1 = load <4 x i8>, ptr %in, align 457 %2 = extractelement <4 x i8> %1, i32 058 %3 = zext i8 %2 to i3259 %4 = insertelement <4 x i32> undef, i32 %3, i32 060 %5 = extractelement <4 x i8> %1, i32 161 %6 = zext i8 %5 to i3262 %7 = insertelement <4 x i32> %4, i32 %6, i32 163 %8 = extractelement <4 x i8> %1, i32 264 %9 = zext i8 %8 to i3265 %10 = insertelement <4 x i32> %7, i32 %9, i32 266 %11 = extractelement <4 x i8> %1, i32 367 %12 = zext i8 %11 to i3268 %13 = insertelement <4 x i32> %10, i32 %12, i32 369 ret <4 x i32> %1370}71 72define float @i(ptr nocapture %in) {73; CHECK-LABEL: i:74; CHECK: @ %bb.0:75; CHECK-NEXT: vldr d16, [r0]76; CHECK-NEXT: vmov.s16 r0, d16[0]77; CHECK-NEXT: vmov s0, r078; CHECK-NEXT: vcvt.f32.s32 s0, s079; CHECK-NEXT: vmov r0, s080; CHECK-NEXT: bx lr81 %1 = load <4 x i16>, ptr %in82 %2 = extractelement <4 x i16> %1, i32 083 %3 = sitofp i16 %2 to float84 ret float %385}86 87define float @j(ptr nocapture %in) {88; CHECK-LABEL: j:89; CHECK: @ %bb.0:90; CHECK-NEXT: vldr d16, [r0]91; CHECK-NEXT: vmov.u8 r0, d16[7]92; CHECK-NEXT: vmov s0, r093; CHECK-NEXT: vcvt.f32.u32 s0, s094; CHECK-NEXT: vmov r0, s095; CHECK-NEXT: bx lr96 %1 = load <8 x i8>, ptr %in97 %2 = extractelement <8 x i8> %1, i32 798 %3 = uitofp i8 %2 to float99 ret float %3100}101 102define float @k(ptr nocapture %in) {103; CHECK-LABEL: k:104; CHECK: @ %bb.0:105; CHECK-NEXT: vldr d16, [r0]106; CHECK-NEXT: vmov.s8 r0, d16[7]107; CHECK-NEXT: vmov s0, r0108; CHECK-NEXT: vcvt.f32.s32 s0, s0109; CHECK-NEXT: vmov r0, s0110; CHECK-NEXT: bx lr111 %1 = load <8 x i8>, ptr %in112 %2 = extractelement <8 x i8> %1, i32 7113 %3 = sitofp i8 %2 to float114 ret float %3115}116 117define float @KnownUpperZero(<4 x i16> %v) {118; CHECK-LABEL: KnownUpperZero:119; CHECK: @ %bb.0:120; CHECK-NEXT: vmov d16, r0, r1121; CHECK-NEXT: vmov.u16 r0, d16[0]122; CHECK-NEXT: vmov.u16 r1, d16[3]123; CHECK-NEXT: and r0, r0, #3124; CHECK-NEXT: vmov s0, r0125; CHECK-NEXT: and r0, r1, #3126; CHECK-NEXT: vmov s2, r0127; CHECK-NEXT: vcvt.f32.s32 s0, s0128; CHECK-NEXT: vcvt.f32.s32 s2, s2129; CHECK-NEXT: vadd.f32 s0, s2, s0130; CHECK-NEXT: vmov r0, s0131; CHECK-NEXT: bx lr132 %1 = and <4 x i16> %v, <i16 3,i16 3,i16 3,i16 3>133 %2 = extractelement <4 x i16> %1, i32 3134 %3 = extractelement <4 x i16> %1, i32 0135 %sinf1 = sitofp i16 %2 to float136 %sinf2 = sitofp i16 %3 to float137 %sum = fadd float %sinf1, %sinf2138 ret float %sum139}140