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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple armv7 -O1 | FileCheck %s -check-prefix=CHECK-LE-NORMAL3; RUN: llc < %s -mtriple armv7 -O1 -combiner-reduce-load-op-store-width-force-narrowing-profitable=1 | FileCheck %s -check-prefix=CHECK-LE-NARROW4; RUN: llc < %s -mtriple armv7eb -O1 | FileCheck %s -check-prefix=CHECK-BE-NORMAL5; RUN: llc < %s -mtriple armv7eb -O1 -combiner-reduce-load-op-store-width-force-narrowing-profitable=1 | FileCheck %s -check-prefix=CHECK-BE-NARROW6 7; This is a reproducer for a bug when DAGCombiner::ReduceLoadOpStoreWidth8; would end up narrowing the load-op-store sequence into this SDNode sequence9; for little-endian10;11; t18: i32,ch = load<(load (s32) from %ir.p1 + 8, align 8)> t0, t17, undef:i3212; t20: i32 = or t18, Constant:i32<65534>13; t21: ch = store<(store (s32) into %ir.p1 + 8, align 8)> t18:1, t20, t17, undef:i3214;15; This was wrong since it accesses memory above %ir.p1+9 which is outside the16; "store size" for the original store.17;18; For big-endian we used to hit an assertion due to passing a negative offset19; to getMemBasePlusOffset (at least after commit 3e1b55cafc95d4ef4, while20; before that commit we got load/store instructions that accessed memory at a21; negative offset from %p1).22;23define i16 @test(ptr %p1) {24; CHECK-LE-NORMAL-LABEL: test:25; CHECK-LE-NORMAL: @ %bb.0: @ %entry26; CHECK-LE-NORMAL-NEXT: ldrh r1, [r0, #8]27; CHECK-LE-NORMAL-NEXT: movw r2, #6553428; CHECK-LE-NORMAL-NEXT: orr r1, r1, r229; CHECK-LE-NORMAL-NEXT: strh r1, [r0, #8]30; CHECK-LE-NORMAL-NEXT: mov r0, #031; CHECK-LE-NORMAL-NEXT: bx lr32;33; CHECK-LE-NARROW-LABEL: test:34; CHECK-LE-NARROW: @ %bb.0: @ %entry35; CHECK-LE-NARROW-NEXT: ldr r1, [r0, #6]36; CHECK-LE-NARROW-NEXT: orr r1, r1, #1664614437; CHECK-LE-NARROW-NEXT: orr r1, r1, #-1677721638; CHECK-LE-NARROW-NEXT: str r1, [r0, #6]39; CHECK-LE-NARROW-NEXT: mov r0, #040; CHECK-LE-NARROW-NEXT: bx lr41;42; CHECK-BE-NORMAL-LABEL: test:43; CHECK-BE-NORMAL: @ %bb.0: @ %entry44; CHECK-BE-NORMAL-NEXT: ldrh r1, [r0]45; CHECK-BE-NORMAL-NEXT: movw r2, #6553446; CHECK-BE-NORMAL-NEXT: orr r1, r1, r247; CHECK-BE-NORMAL-NEXT: strh r1, [r0]48; CHECK-BE-NORMAL-NEXT: mov r0, #049; CHECK-BE-NORMAL-NEXT: bx lr50;51; CHECK-BE-NARROW-LABEL: test:52; CHECK-BE-NARROW: @ %bb.0: @ %entry53; CHECK-BE-NARROW-NEXT: ldr r1, [r0]54; CHECK-BE-NARROW-NEXT: orr r1, r1, #1664614455; CHECK-BE-NARROW-NEXT: orr r1, r1, #-1677721656; CHECK-BE-NARROW-NEXT: str r1, [r0]57; CHECK-BE-NARROW-NEXT: mov r0, #058; CHECK-BE-NARROW-NEXT: bx lr59entry:60 %load = load i80, ptr %p1, align 3261 %mask = shl i80 -1, 6562 %op = or i80 %load, %mask63 store i80 %op, ptr %p1, align 3264 ret i16 065}66 67