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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s3--- |4 target triple = "armv7---gnueabi"5 6 define i32 @test1(i32 %x) {7 entry:8 unreachable9 }10 define i32 @test2(i32 %x) {11 entry:12 unreachable13 }14 define i32 @test3(i32 %x) {15 entry:16 unreachable17 }18 define i32 @test4(i32 %x) {19 entry:20 unreachable21 }22 @var = global i32 023 define i32 @test5(i32 %x) {24 entry:25 unreachable26 }27 define i32 @vbsl_kill_flags(i32 %x) {28 unreachable29 }30...31---32name: test133alignment: 434tracksRegLiveness: true35liveins:36 - { reg: '$r0', virtual-reg: '' }37body: |38 bb.0.entry:39 liveins: $r040 41 ; CHECK-LABEL: name: test142 ; CHECK: liveins: $r043 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg45 ; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr46 ; CHECK-NEXT: $r1 = MOVi16 500, 0 /* CC::eq */, killed $cpsr, implicit killed $r147 ; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg48 ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r049 $r1 = MOVi 2, 14, $noreg, $noreg50 CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr51 $r1 = MOVCCi16 killed $r1, 500, 0, killed $cpsr52 $r0 = MOVr killed $r1, 14, $noreg, $noreg53 BX_RET 14, $noreg, implicit $r054 55...56---57name: test258alignment: 459tracksRegLiveness: true60liveins:61 - { reg: '$r0', virtual-reg: '' }62body: |63 bb.0.entry:64 liveins: $r065 66 ; CHECK-LABEL: name: test267 ; CHECK: liveins: $r068 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: $r1 = MOVi 2, 14 /* CC::al */, $noreg, $noreg70 ; CHECK-NEXT: CMPri killed $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr71 ; CHECK-NEXT: $r1 = MOVi16 2068, 0 /* CC::eq */, $cpsr, implicit killed $r172 ; CHECK-NEXT: $r1 = MOVTi16 $r1, 7637, 0 /* CC::eq */, $cpsr73 ; CHECK-NEXT: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg74 ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r075 $r1 = MOVi 2, 14, $noreg, $noreg76 CMPri killed $r0, 0, 14, $noreg, implicit-def $cpsr77 $r1 = MOVCCi32imm killed $r1, 500500500, 0, killed $cpsr78 $r0 = MOVr killed $r1, 14, $noreg, $noreg79 BX_RET 14, $noreg, implicit $r080 81...82---83name: test384alignment: 485tracksRegLiveness: true86liveins:87 - { reg: '$r0', virtual-reg: '' }88 - { reg: '$r1', virtual-reg: '' }89body: |90 bb.0.entry:91 liveins: $r0, $r192 93 ; CHECK-LABEL: name: test394 ; CHECK: liveins: $r0, $r195 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: CMPri $r1, 500, 14 /* CC::al */, $noreg, implicit-def $cpsr97 ; CHECK-NEXT: $r0 = MOVr killed $r1, 12 /* CC::gt */, killed $cpsr, $noreg, implicit killed $r098 ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r099 CMPri $r1, 500, 14, $noreg, implicit-def $cpsr100 $r0 = MOVCCr killed $r0, killed $r1, 12, killed $cpsr101 BX_RET 14, $noreg, implicit $r0102 103...104---105name: test4106alignment: 4107tracksRegLiveness: true108liveins:109 - { reg: '$r0', virtual-reg: '' }110 - { reg: '$r0_r1', virtual-reg: '' }111body: |112 bb.0.entry:113 liveins: $r0, $r0_r1114 115 ; CHECK-LABEL: name: test4116 ; CHECK: liveins: $r0, $r0_r1117 ; CHECK-NEXT: {{ $}}118 ; CHECK-NEXT: $r0 = MOVi16 51712, 14 /* CC::al */, $noreg, implicit-def $r0_r1119 ; CHECK-NEXT: $r0 = MOVTi16 $r0, 15258, 14 /* CC::al */, $noreg, implicit-def $r0_r1120 ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0121 $r0 = MOVi32imm 1000000000, implicit-def $r0_r1122 BX_RET 14, $noreg, implicit $r0123 124...125---126name: test5127alignment: 4128tracksRegLiveness: true129liveins:130 - { reg: '$r0', virtual-reg: '' }131 - { reg: '$r0_r1', virtual-reg: '' }132body: |133 bb.0.entry:134 liveins: $r0, $r0_r1135 136 ; CHECK-LABEL: name: test5137 ; CHECK: liveins: $r0, $r0_r1138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: $r0 = MOVi16_ga_pcrel target-flags(arm-lo16) @var, 0, implicit-def $r0_r1140 ; CHECK-NEXT: $r0 = MOVTi16_ga_pcrel $r0, target-flags(arm-hi16) @var, 0, implicit-def $r0_r1141 ; CHECK-NEXT: $r0 = PICLDR $r0, 0, 14 /* CC::al */, $noreg, implicit-def $r0_r1142 ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0143 $r0 = MOV_ga_pcrel_ldr @var, implicit-def $r0_r1144 BX_RET 14, $noreg, implicit $r0145 146...147---148name: vbsl_kill_flags149alignment: 4150tracksRegLiveness: true151body: |152 bb.0 (%ir-block.0):153 liveins: $d1154 155 ; CHECK-LABEL: name: vbsl_kill_flags156 ; CHECK: liveins: $d1157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: renamable $d0 = VORRd renamable $d1, renamable $d1, 14 /* CC::al */, $noreg159 ; CHECK-NEXT: renamable $d0 = VBSLd killed renamable $d0, renamable $d1, renamable $d1, 14 /* CC::al */, $noreg160 ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $d0161 renamable $d0 = VBSPd killed renamable $d1, renamable $d1, renamable $d1, 14 /* CC::al */, $noreg162 BX_RET 14 /* CC::al */, $noreg, implicit $d0163 164...165