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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s --check-prefix V7M3; RUN: llc -mtriple=armv7a-eabi %s -o - | FileCheck %s --check-prefix V7A4; RUN: llc -mtriple=thumbv7a-eabi %s -o - | FileCheck %s --check-prefix V7A-T5; RUN: llc -mtriple=armv6m-eabi %s -o - | FileCheck %s --check-prefix V6M6 7; Patterns:8; a) x & (1 << nbits) - 19; b) x & ~(-1 << nbits)10; c) x & (-1 >> (32 - y))11; d) x << (32 - y) >> (32 - y)12; are equivalent.13 14; ---------------------------------------------------------------------------- ;15; Pattern a. 32-bit16; ---------------------------------------------------------------------------- ;17 18define i32 @bzhi32_a0(i32 %val, i32 %numlowbits) nounwind {19; V7M-LABEL: bzhi32_a0:20; V7M: @ %bb.0:21; V7M-NEXT: movs r2, #122; V7M-NEXT: lsl.w r1, r2, r123; V7M-NEXT: subs r1, #124; V7M-NEXT: ands r0, r125; V7M-NEXT: bx lr26;27; V7A-LABEL: bzhi32_a0:28; V7A: @ %bb.0:29; V7A-NEXT: mov r2, #130; V7A-NEXT: mvn r3, #031; V7A-NEXT: add r1, r3, r2, lsl r132; V7A-NEXT: and r0, r1, r033; V7A-NEXT: bx lr34;35; V7A-T-LABEL: bzhi32_a0:36; V7A-T: @ %bb.0:37; V7A-T-NEXT: movs r2, #138; V7A-T-NEXT: lsl.w r1, r2, r139; V7A-T-NEXT: subs r1, #140; V7A-T-NEXT: ands r0, r141; V7A-T-NEXT: bx lr42;43; V6M-LABEL: bzhi32_a0:44; V6M: @ %bb.0:45; V6M-NEXT: movs r2, #146; V6M-NEXT: lsls r2, r147; V6M-NEXT: subs r1, r2, #148; V6M-NEXT: ands r0, r149; V6M-NEXT: bx lr50 %onebit = shl i32 1, %numlowbits51 %mask = add nsw i32 %onebit, -152 %masked = and i32 %mask, %val53 ret i32 %masked54}55 56define i32 @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {57; V7M-LABEL: bzhi32_a1_indexzext:58; V7M: @ %bb.0:59; V7M-NEXT: movs r2, #160; V7M-NEXT: lsl.w r1, r2, r161; V7M-NEXT: subs r1, #162; V7M-NEXT: ands r0, r163; V7M-NEXT: bx lr64;65; V7A-LABEL: bzhi32_a1_indexzext:66; V7A: @ %bb.0:67; V7A-NEXT: mov r2, #168; V7A-NEXT: mvn r3, #069; V7A-NEXT: add r1, r3, r2, lsl r170; V7A-NEXT: and r0, r1, r071; V7A-NEXT: bx lr72;73; V7A-T-LABEL: bzhi32_a1_indexzext:74; V7A-T: @ %bb.0:75; V7A-T-NEXT: movs r2, #176; V7A-T-NEXT: lsl.w r1, r2, r177; V7A-T-NEXT: subs r1, #178; V7A-T-NEXT: ands r0, r179; V7A-T-NEXT: bx lr80;81; V6M-LABEL: bzhi32_a1_indexzext:82; V6M: @ %bb.0:83; V6M-NEXT: movs r2, #184; V6M-NEXT: lsls r2, r185; V6M-NEXT: subs r1, r2, #186; V6M-NEXT: ands r0, r187; V6M-NEXT: bx lr88 %conv = zext i8 %numlowbits to i3289 %onebit = shl i32 1, %conv90 %mask = add nsw i32 %onebit, -191 %masked = and i32 %mask, %val92 ret i32 %masked93}94 95define i32 @bzhi32_a2_load(ptr %w, i32 %numlowbits) nounwind {96; V7M-LABEL: bzhi32_a2_load:97; V7M: @ %bb.0:98; V7M-NEXT: movs r2, #199; V7M-NEXT: ldr r0, [r0]100; V7M-NEXT: lsl.w r1, r2, r1101; V7M-NEXT: subs r1, #1102; V7M-NEXT: ands r0, r1103; V7M-NEXT: bx lr104;105; V7A-LABEL: bzhi32_a2_load:106; V7A: @ %bb.0:107; V7A-NEXT: mov r2, #1108; V7A-NEXT: ldr r0, [r0]109; V7A-NEXT: mvn r3, #0110; V7A-NEXT: add r1, r3, r2, lsl r1111; V7A-NEXT: and r0, r1, r0112; V7A-NEXT: bx lr113;114; V7A-T-LABEL: bzhi32_a2_load:115; V7A-T: @ %bb.0:116; V7A-T-NEXT: movs r2, #1117; V7A-T-NEXT: ldr r0, [r0]118; V7A-T-NEXT: lsl.w r1, r2, r1119; V7A-T-NEXT: subs r1, #1120; V7A-T-NEXT: ands r0, r1121; V7A-T-NEXT: bx lr122;123; V6M-LABEL: bzhi32_a2_load:124; V6M: @ %bb.0:125; V6M-NEXT: movs r2, #1126; V6M-NEXT: lsls r2, r1127; V6M-NEXT: subs r1, r2, #1128; V6M-NEXT: ldr r0, [r0]129; V6M-NEXT: ands r0, r1130; V6M-NEXT: bx lr131 %val = load i32, ptr %w132 %onebit = shl i32 1, %numlowbits133 %mask = add nsw i32 %onebit, -1134 %masked = and i32 %mask, %val135 ret i32 %masked136}137 138define i32 @bzhi32_a3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {139; V7M-LABEL: bzhi32_a3_load_indexzext:140; V7M: @ %bb.0:141; V7M-NEXT: movs r2, #1142; V7M-NEXT: ldr r0, [r0]143; V7M-NEXT: lsl.w r1, r2, r1144; V7M-NEXT: subs r1, #1145; V7M-NEXT: ands r0, r1146; V7M-NEXT: bx lr147;148; V7A-LABEL: bzhi32_a3_load_indexzext:149; V7A: @ %bb.0:150; V7A-NEXT: mov r2, #1151; V7A-NEXT: ldr r0, [r0]152; V7A-NEXT: mvn r3, #0153; V7A-NEXT: add r1, r3, r2, lsl r1154; V7A-NEXT: and r0, r1, r0155; V7A-NEXT: bx lr156;157; V7A-T-LABEL: bzhi32_a3_load_indexzext:158; V7A-T: @ %bb.0:159; V7A-T-NEXT: movs r2, #1160; V7A-T-NEXT: ldr r0, [r0]161; V7A-T-NEXT: lsl.w r1, r2, r1162; V7A-T-NEXT: subs r1, #1163; V7A-T-NEXT: ands r0, r1164; V7A-T-NEXT: bx lr165;166; V6M-LABEL: bzhi32_a3_load_indexzext:167; V6M: @ %bb.0:168; V6M-NEXT: movs r2, #1169; V6M-NEXT: lsls r2, r1170; V6M-NEXT: subs r1, r2, #1171; V6M-NEXT: ldr r0, [r0]172; V6M-NEXT: ands r0, r1173; V6M-NEXT: bx lr174 %val = load i32, ptr %w175 %conv = zext i8 %numlowbits to i32176 %onebit = shl i32 1, %conv177 %mask = add nsw i32 %onebit, -1178 %masked = and i32 %mask, %val179 ret i32 %masked180}181 182define i32 @bzhi32_a4_commutative(i32 %val, i32 %numlowbits) nounwind {183; V7M-LABEL: bzhi32_a4_commutative:184; V7M: @ %bb.0:185; V7M-NEXT: movs r2, #1186; V7M-NEXT: lsl.w r1, r2, r1187; V7M-NEXT: subs r1, #1188; V7M-NEXT: ands r0, r1189; V7M-NEXT: bx lr190;191; V7A-LABEL: bzhi32_a4_commutative:192; V7A: @ %bb.0:193; V7A-NEXT: mov r2, #1194; V7A-NEXT: mvn r3, #0195; V7A-NEXT: add r1, r3, r2, lsl r1196; V7A-NEXT: and r0, r0, r1197; V7A-NEXT: bx lr198;199; V7A-T-LABEL: bzhi32_a4_commutative:200; V7A-T: @ %bb.0:201; V7A-T-NEXT: movs r2, #1202; V7A-T-NEXT: lsl.w r1, r2, r1203; V7A-T-NEXT: subs r1, #1204; V7A-T-NEXT: ands r0, r1205; V7A-T-NEXT: bx lr206;207; V6M-LABEL: bzhi32_a4_commutative:208; V6M: @ %bb.0:209; V6M-NEXT: movs r2, #1210; V6M-NEXT: lsls r2, r1211; V6M-NEXT: subs r1, r2, #1212; V6M-NEXT: ands r0, r1213; V6M-NEXT: bx lr214 %onebit = shl i32 1, %numlowbits215 %mask = add nsw i32 %onebit, -1216 %masked = and i32 %val, %mask ; swapped order217 ret i32 %masked218}219 220; 64-bit221 222define i64 @bzhi64_a0(i64 %val, i64 %numlowbits) nounwind {223; V7M-LABEL: bzhi64_a0:224; V7M: @ %bb.0:225; V7M-NEXT: .save {r7, lr}226; V7M-NEXT: push {r7, lr}227; V7M-NEXT: rsb.w r3, r2, #32228; V7M-NEXT: mov.w r12, #1229; V7M-NEXT: subs.w lr, r2, #32230; V7M-NEXT: lsl.w r2, r12, r2231; V7M-NEXT: lsr.w r3, r12, r3232; V7M-NEXT: it pl233; V7M-NEXT: lslpl.w r3, r12, lr234; V7M-NEXT: it pl235; V7M-NEXT: movpl r2, #0236; V7M-NEXT: subs r2, #1237; V7M-NEXT: sbc r3, r3, #0238; V7M-NEXT: ands r0, r2239; V7M-NEXT: ands r1, r3240; V7M-NEXT: pop {r7, pc}241;242; V7A-LABEL: bzhi64_a0:243; V7A: @ %bb.0:244; V7A-NEXT: .save {r11, lr}245; V7A-NEXT: push {r11, lr}246; V7A-NEXT: rsb r12, r2, #32247; V7A-NEXT: mov lr, #1248; V7A-NEXT: subs r3, r2, #32249; V7A-NEXT: lsl r2, lr, r2250; V7A-NEXT: lsr r12, lr, r12251; V7A-NEXT: movwpl r2, #0252; V7A-NEXT: lslpl r12, lr, r3253; V7A-NEXT: subs r2, r2, #1254; V7A-NEXT: sbc r3, r12, #0255; V7A-NEXT: and r0, r2, r0256; V7A-NEXT: and r1, r3, r1257; V7A-NEXT: pop {r11, pc}258;259; V7A-T-LABEL: bzhi64_a0:260; V7A-T: @ %bb.0:261; V7A-T-NEXT: .save {r7, lr}262; V7A-T-NEXT: push {r7, lr}263; V7A-T-NEXT: rsb.w r3, r2, #32264; V7A-T-NEXT: mov.w r12, #1265; V7A-T-NEXT: subs.w lr, r2, #32266; V7A-T-NEXT: lsl.w r2, r12, r2267; V7A-T-NEXT: lsr.w r3, r12, r3268; V7A-T-NEXT: it pl269; V7A-T-NEXT: lslpl.w r3, r12, lr270; V7A-T-NEXT: it pl271; V7A-T-NEXT: movpl r2, #0272; V7A-T-NEXT: subs r2, #1273; V7A-T-NEXT: sbc r3, r3, #0274; V7A-T-NEXT: ands r0, r2275; V7A-T-NEXT: ands r1, r3276; V7A-T-NEXT: pop {r7, pc}277;278; V6M-LABEL: bzhi64_a0:279; V6M: @ %bb.0:280; V6M-NEXT: .save {r4, r5, r6, lr}281; V6M-NEXT: push {r4, r5, r6, lr}282; V6M-NEXT: mov r5, r1283; V6M-NEXT: mov r4, r0284; V6M-NEXT: movs r0, #1285; V6M-NEXT: movs r6, #0286; V6M-NEXT: mov r1, r6287; V6M-NEXT: bl __aeabi_llsl288; V6M-NEXT: subs r0, r0, #1289; V6M-NEXT: sbcs r1, r6290; V6M-NEXT: ands r1, r5291; V6M-NEXT: ands r0, r4292; V6M-NEXT: pop {r4, r5, r6, pc}293 %onebit = shl i64 1, %numlowbits294 %mask = add nsw i64 %onebit, -1295 %masked = and i64 %mask, %val296 ret i64 %masked297}298 299; Check that we don't throw away the vreg_width-1 mask if not using shifts300define i64 @bzhi64_a0_masked(i64 %val, i64 %numlowbits) nounwind {301; V7M-LABEL: bzhi64_a0_masked:302; V7M: @ %bb.0:303; V7M-NEXT: .save {r7, lr}304; V7M-NEXT: push {r7, lr}305; V7M-NEXT: and r2, r2, #63306; V7M-NEXT: mov.w r12, #1307; V7M-NEXT: rsb.w r3, r2, #32308; V7M-NEXT: subs.w lr, r2, #32309; V7M-NEXT: lsl.w r2, r12, r2310; V7M-NEXT: lsr.w r3, r12, r3311; V7M-NEXT: it pl312; V7M-NEXT: lslpl.w r3, r12, lr313; V7M-NEXT: it pl314; V7M-NEXT: movpl r2, #0315; V7M-NEXT: subs r2, #1316; V7M-NEXT: sbc r3, r3, #0317; V7M-NEXT: ands r0, r2318; V7M-NEXT: ands r1, r3319; V7M-NEXT: pop {r7, pc}320;321; V7A-LABEL: bzhi64_a0_masked:322; V7A: @ %bb.0:323; V7A-NEXT: .save {r11, lr}324; V7A-NEXT: push {r11, lr}325; V7A-NEXT: and r2, r2, #63326; V7A-NEXT: mov lr, #1327; V7A-NEXT: rsb r12, r2, #32328; V7A-NEXT: subs r3, r2, #32329; V7A-NEXT: lsl r2, lr, r2330; V7A-NEXT: lsr r12, lr, r12331; V7A-NEXT: movwpl r2, #0332; V7A-NEXT: lslpl r12, lr, r3333; V7A-NEXT: subs r2, r2, #1334; V7A-NEXT: sbc r3, r12, #0335; V7A-NEXT: and r0, r2, r0336; V7A-NEXT: and r1, r3, r1337; V7A-NEXT: pop {r11, pc}338;339; V7A-T-LABEL: bzhi64_a0_masked:340; V7A-T: @ %bb.0:341; V7A-T-NEXT: .save {r7, lr}342; V7A-T-NEXT: push {r7, lr}343; V7A-T-NEXT: and r2, r2, #63344; V7A-T-NEXT: mov.w r12, #1345; V7A-T-NEXT: rsb.w r3, r2, #32346; V7A-T-NEXT: subs.w lr, r2, #32347; V7A-T-NEXT: lsl.w r2, r12, r2348; V7A-T-NEXT: lsr.w r3, r12, r3349; V7A-T-NEXT: it pl350; V7A-T-NEXT: lslpl.w r3, r12, lr351; V7A-T-NEXT: it pl352; V7A-T-NEXT: movpl r2, #0353; V7A-T-NEXT: subs r2, #1354; V7A-T-NEXT: sbc r3, r3, #0355; V7A-T-NEXT: ands r0, r2356; V7A-T-NEXT: ands r1, r3357; V7A-T-NEXT: pop {r7, pc}358;359; V6M-LABEL: bzhi64_a0_masked:360; V6M: @ %bb.0:361; V6M-NEXT: .save {r4, r5, r6, lr}362; V6M-NEXT: push {r4, r5, r6, lr}363; V6M-NEXT: mov r5, r1364; V6M-NEXT: mov r4, r0365; V6M-NEXT: movs r0, #63366; V6M-NEXT: ands r2, r0367; V6M-NEXT: movs r0, #1368; V6M-NEXT: movs r6, #0369; V6M-NEXT: mov r1, r6370; V6M-NEXT: bl __aeabi_llsl371; V6M-NEXT: subs r0, r0, #1372; V6M-NEXT: sbcs r1, r6373; V6M-NEXT: ands r1, r5374; V6M-NEXT: ands r0, r4375; V6M-NEXT: pop {r4, r5, r6, pc}376 %numlowbits.masked = and i64 %numlowbits, 63377 %onebit = shl i64 1, %numlowbits.masked378 %mask = add nsw i64 %onebit, -1379 %masked = and i64 %mask, %val380 ret i64 %masked381}382 383define i64 @bzhi64_a1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {384; V7M-LABEL: bzhi64_a1_indexzext:385; V7M: @ %bb.0:386; V7M-NEXT: .save {r7, lr}387; V7M-NEXT: push {r7, lr}388; V7M-NEXT: rsb.w r3, r2, #32389; V7M-NEXT: mov.w r12, #1390; V7M-NEXT: subs.w lr, r2, #32391; V7M-NEXT: lsl.w r2, r12, r2392; V7M-NEXT: lsr.w r3, r12, r3393; V7M-NEXT: it pl394; V7M-NEXT: lslpl.w r3, r12, lr395; V7M-NEXT: it pl396; V7M-NEXT: movpl r2, #0397; V7M-NEXT: subs r2, #1398; V7M-NEXT: sbc r3, r3, #0399; V7M-NEXT: ands r0, r2400; V7M-NEXT: ands r1, r3401; V7M-NEXT: pop {r7, pc}402;403; V7A-LABEL: bzhi64_a1_indexzext:404; V7A: @ %bb.0:405; V7A-NEXT: .save {r11, lr}406; V7A-NEXT: push {r11, lr}407; V7A-NEXT: rsb r12, r2, #32408; V7A-NEXT: mov lr, #1409; V7A-NEXT: subs r3, r2, #32410; V7A-NEXT: lsl r2, lr, r2411; V7A-NEXT: lsr r12, lr, r12412; V7A-NEXT: movwpl r2, #0413; V7A-NEXT: lslpl r12, lr, r3414; V7A-NEXT: subs r2, r2, #1415; V7A-NEXT: sbc r3, r12, #0416; V7A-NEXT: and r0, r2, r0417; V7A-NEXT: and r1, r3, r1418; V7A-NEXT: pop {r11, pc}419;420; V7A-T-LABEL: bzhi64_a1_indexzext:421; V7A-T: @ %bb.0:422; V7A-T-NEXT: .save {r7, lr}423; V7A-T-NEXT: push {r7, lr}424; V7A-T-NEXT: rsb.w r3, r2, #32425; V7A-T-NEXT: mov.w r12, #1426; V7A-T-NEXT: subs.w lr, r2, #32427; V7A-T-NEXT: lsl.w r2, r12, r2428; V7A-T-NEXT: lsr.w r3, r12, r3429; V7A-T-NEXT: it pl430; V7A-T-NEXT: lslpl.w r3, r12, lr431; V7A-T-NEXT: it pl432; V7A-T-NEXT: movpl r2, #0433; V7A-T-NEXT: subs r2, #1434; V7A-T-NEXT: sbc r3, r3, #0435; V7A-T-NEXT: ands r0, r2436; V7A-T-NEXT: ands r1, r3437; V7A-T-NEXT: pop {r7, pc}438;439; V6M-LABEL: bzhi64_a1_indexzext:440; V6M: @ %bb.0:441; V6M-NEXT: .save {r4, r5, r6, lr}442; V6M-NEXT: push {r4, r5, r6, lr}443; V6M-NEXT: mov r5, r1444; V6M-NEXT: mov r4, r0445; V6M-NEXT: movs r0, #1446; V6M-NEXT: movs r6, #0447; V6M-NEXT: mov r1, r6448; V6M-NEXT: bl __aeabi_llsl449; V6M-NEXT: subs r0, r0, #1450; V6M-NEXT: sbcs r1, r6451; V6M-NEXT: ands r1, r5452; V6M-NEXT: ands r0, r4453; V6M-NEXT: pop {r4, r5, r6, pc}454 %conv = zext i8 %numlowbits to i64455 %onebit = shl i64 1, %conv456 %mask = add nsw i64 %onebit, -1457 %masked = and i64 %mask, %val458 ret i64 %masked459}460 461define i64 @bzhi64_a2_load(ptr %w, i64 %numlowbits) nounwind {462; V7M-LABEL: bzhi64_a2_load:463; V7M: @ %bb.0:464; V7M-NEXT: rsb.w r1, r2, #32465; V7M-NEXT: movs r3, #1466; V7M-NEXT: subs.w r12, r2, #32467; V7M-NEXT: lsl.w r2, r3, r2468; V7M-NEXT: lsr.w r1, r3, r1469; V7M-NEXT: it pl470; V7M-NEXT: lslpl.w r1, r3, r12471; V7M-NEXT: it pl472; V7M-NEXT: movpl r2, #0473; V7M-NEXT: subs r2, #1474; V7M-NEXT: ldrd r0, r3, [r0]475; V7M-NEXT: sbc r1, r1, #0476; V7M-NEXT: ands r1, r3477; V7M-NEXT: ands r0, r2478; V7M-NEXT: bx lr479;480; V7A-LABEL: bzhi64_a2_load:481; V7A: @ %bb.0:482; V7A-NEXT: .save {r4, r6, r11, lr}483; V7A-NEXT: push {r4, r6, r11, lr}484; V7A-NEXT: ldr r6, [r0]485; V7A-NEXT: mov r1, #1486; V7A-NEXT: ldr r3, [r0, #4]487; V7A-NEXT: rsb r0, r2, #32488; V7A-NEXT: subs r4, r2, #32489; V7A-NEXT: lsr r0, r1, r0490; V7A-NEXT: lslpl r0, r1, r4491; V7A-NEXT: lsl r1, r1, r2492; V7A-NEXT: movwpl r1, #0493; V7A-NEXT: subs r2, r1, #1494; V7A-NEXT: sbc r0, r0, #0495; V7A-NEXT: and r1, r0, r3496; V7A-NEXT: and r0, r2, r6497; V7A-NEXT: pop {r4, r6, r11, pc}498;499; V7A-T-LABEL: bzhi64_a2_load:500; V7A-T: @ %bb.0:501; V7A-T-NEXT: .save {r7, lr}502; V7A-T-NEXT: push {r7, lr}503; V7A-T-NEXT: rsb.w r3, r2, #32504; V7A-T-NEXT: movs r1, #1505; V7A-T-NEXT: ldrd r12, lr, [r0]506; V7A-T-NEXT: subs.w r0, r2, #32507; V7A-T-NEXT: lsr.w r3, r1, r3508; V7A-T-NEXT: it pl509; V7A-T-NEXT: lslpl.w r3, r1, r0510; V7A-T-NEXT: lsl.w r0, r1, r2511; V7A-T-NEXT: it pl512; V7A-T-NEXT: movpl r0, #0513; V7A-T-NEXT: subs r0, #1514; V7A-T-NEXT: sbc r1, r3, #0515; V7A-T-NEXT: and.w r0, r0, r12516; V7A-T-NEXT: and.w r1, r1, lr517; V7A-T-NEXT: pop {r7, pc}518;519; V6M-LABEL: bzhi64_a2_load:520; V6M: @ %bb.0:521; V6M-NEXT: .save {r4, r5, r7, lr}522; V6M-NEXT: push {r4, r5, r7, lr}523; V6M-NEXT: mov r4, r0524; V6M-NEXT: movs r0, #1525; V6M-NEXT: movs r5, #0526; V6M-NEXT: mov r1, r5527; V6M-NEXT: bl __aeabi_llsl528; V6M-NEXT: subs r2, r0, #1529; V6M-NEXT: sbcs r1, r5530; V6M-NEXT: ldm r4!, {r0, r3}531; V6M-NEXT: ands r1, r3532; V6M-NEXT: ands r0, r2533; V6M-NEXT: pop {r4, r5, r7, pc}534 %val = load i64, ptr %w535 %onebit = shl i64 1, %numlowbits536 %mask = add nsw i64 %onebit, -1537 %masked = and i64 %mask, %val538 ret i64 %masked539}540 541define i64 @bzhi64_a3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {542; V7M-LABEL: bzhi64_a3_load_indexzext:543; V7M: @ %bb.0:544; V7M-NEXT: rsb.w r2, r1, #32545; V7M-NEXT: movs r3, #1546; V7M-NEXT: subs.w r12, r1, #32547; V7M-NEXT: lsl.w r1, r3, r1548; V7M-NEXT: lsr.w r2, r3, r2549; V7M-NEXT: it pl550; V7M-NEXT: lslpl.w r2, r3, r12551; V7M-NEXT: it pl552; V7M-NEXT: movpl r1, #0553; V7M-NEXT: subs r3, r1, #1554; V7M-NEXT: sbc r1, r2, #0555; V7M-NEXT: ldrd r0, r2, [r0]556; V7M-NEXT: ands r1, r2557; V7M-NEXT: ands r0, r3558; V7M-NEXT: bx lr559;560; V7A-LABEL: bzhi64_a3_load_indexzext:561; V7A: @ %bb.0:562; V7A-NEXT: .save {r4, r6, r11, lr}563; V7A-NEXT: push {r4, r6, r11, lr}564; V7A-NEXT: ldr r6, [r0]565; V7A-NEXT: mov r2, #1566; V7A-NEXT: ldr r3, [r0, #4]567; V7A-NEXT: rsb r0, r1, #32568; V7A-NEXT: subs r4, r1, #32569; V7A-NEXT: lsl r1, r2, r1570; V7A-NEXT: lsr r0, r2, r0571; V7A-NEXT: movwpl r1, #0572; V7A-NEXT: lslpl r0, r2, r4573; V7A-NEXT: subs r2, r1, #1574; V7A-NEXT: sbc r0, r0, #0575; V7A-NEXT: and r1, r0, r3576; V7A-NEXT: and r0, r2, r6577; V7A-NEXT: pop {r4, r6, r11, pc}578;579; V7A-T-LABEL: bzhi64_a3_load_indexzext:580; V7A-T: @ %bb.0:581; V7A-T-NEXT: .save {r7, lr}582; V7A-T-NEXT: push {r7, lr}583; V7A-T-NEXT: rsb.w r3, r1, #32584; V7A-T-NEXT: movs r2, #1585; V7A-T-NEXT: ldrd r12, lr, [r0]586; V7A-T-NEXT: subs.w r0, r1, #32587; V7A-T-NEXT: lsr.w r3, r2, r3588; V7A-T-NEXT: it pl589; V7A-T-NEXT: lslpl.w r3, r2, r0590; V7A-T-NEXT: lsl.w r0, r2, r1591; V7A-T-NEXT: it pl592; V7A-T-NEXT: movpl r0, #0593; V7A-T-NEXT: subs r0, #1594; V7A-T-NEXT: sbc r1, r3, #0595; V7A-T-NEXT: and.w r0, r0, r12596; V7A-T-NEXT: and.w r1, r1, lr597; V7A-T-NEXT: pop {r7, pc}598;599; V6M-LABEL: bzhi64_a3_load_indexzext:600; V6M: @ %bb.0:601; V6M-NEXT: .save {r4, r5, r7, lr}602; V6M-NEXT: push {r4, r5, r7, lr}603; V6M-NEXT: mov r2, r1604; V6M-NEXT: mov r4, r0605; V6M-NEXT: movs r0, #1606; V6M-NEXT: movs r5, #0607; V6M-NEXT: mov r1, r5608; V6M-NEXT: bl __aeabi_llsl609; V6M-NEXT: subs r2, r0, #1610; V6M-NEXT: sbcs r1, r5611; V6M-NEXT: ldm r4!, {r0, r3}612; V6M-NEXT: ands r1, r3613; V6M-NEXT: ands r0, r2614; V6M-NEXT: pop {r4, r5, r7, pc}615 %val = load i64, ptr %w616 %conv = zext i8 %numlowbits to i64617 %onebit = shl i64 1, %conv618 %mask = add nsw i64 %onebit, -1619 %masked = and i64 %mask, %val620 ret i64 %masked621}622 623define i64 @bzhi64_a4_commutative(i64 %val, i64 %numlowbits) nounwind {624; V7M-LABEL: bzhi64_a4_commutative:625; V7M: @ %bb.0:626; V7M-NEXT: .save {r7, lr}627; V7M-NEXT: push {r7, lr}628; V7M-NEXT: rsb.w r3, r2, #32629; V7M-NEXT: mov.w r12, #1630; V7M-NEXT: subs.w lr, r2, #32631; V7M-NEXT: lsl.w r2, r12, r2632; V7M-NEXT: lsr.w r3, r12, r3633; V7M-NEXT: it pl634; V7M-NEXT: lslpl.w r3, r12, lr635; V7M-NEXT: it pl636; V7M-NEXT: movpl r2, #0637; V7M-NEXT: subs r2, #1638; V7M-NEXT: sbc r3, r3, #0639; V7M-NEXT: ands r0, r2640; V7M-NEXT: ands r1, r3641; V7M-NEXT: pop {r7, pc}642;643; V7A-LABEL: bzhi64_a4_commutative:644; V7A: @ %bb.0:645; V7A-NEXT: .save {r11, lr}646; V7A-NEXT: push {r11, lr}647; V7A-NEXT: rsb r12, r2, #32648; V7A-NEXT: mov lr, #1649; V7A-NEXT: subs r3, r2, #32650; V7A-NEXT: lsl r2, lr, r2651; V7A-NEXT: lsr r12, lr, r12652; V7A-NEXT: movwpl r2, #0653; V7A-NEXT: lslpl r12, lr, r3654; V7A-NEXT: subs r2, r2, #1655; V7A-NEXT: sbc r3, r12, #0656; V7A-NEXT: and r0, r0, r2657; V7A-NEXT: and r1, r1, r3658; V7A-NEXT: pop {r11, pc}659;660; V7A-T-LABEL: bzhi64_a4_commutative:661; V7A-T: @ %bb.0:662; V7A-T-NEXT: .save {r7, lr}663; V7A-T-NEXT: push {r7, lr}664; V7A-T-NEXT: rsb.w r3, r2, #32665; V7A-T-NEXT: mov.w r12, #1666; V7A-T-NEXT: subs.w lr, r2, #32667; V7A-T-NEXT: lsl.w r2, r12, r2668; V7A-T-NEXT: lsr.w r3, r12, r3669; V7A-T-NEXT: it pl670; V7A-T-NEXT: lslpl.w r3, r12, lr671; V7A-T-NEXT: it pl672; V7A-T-NEXT: movpl r2, #0673; V7A-T-NEXT: subs r2, #1674; V7A-T-NEXT: sbc r3, r3, #0675; V7A-T-NEXT: ands r0, r2676; V7A-T-NEXT: ands r1, r3677; V7A-T-NEXT: pop {r7, pc}678;679; V6M-LABEL: bzhi64_a4_commutative:680; V6M: @ %bb.0:681; V6M-NEXT: .save {r4, r5, r6, lr}682; V6M-NEXT: push {r4, r5, r6, lr}683; V6M-NEXT: mov r5, r1684; V6M-NEXT: mov r4, r0685; V6M-NEXT: movs r0, #1686; V6M-NEXT: movs r6, #0687; V6M-NEXT: mov r1, r6688; V6M-NEXT: bl __aeabi_llsl689; V6M-NEXT: subs r0, r0, #1690; V6M-NEXT: sbcs r1, r6691; V6M-NEXT: ands r1, r5692; V6M-NEXT: ands r0, r4693; V6M-NEXT: pop {r4, r5, r6, pc}694 %onebit = shl i64 1, %numlowbits695 %mask = add nsw i64 %onebit, -1696 %masked = and i64 %val, %mask ; swapped order697 ret i64 %masked698}699 700; ---------------------------------------------------------------------------- ;701; Pattern b. 32-bit702; ---------------------------------------------------------------------------- ;703 704define i32 @bzhi32_b0(i32 %val, i32 %numlowbits) nounwind {705; V7M-LABEL: bzhi32_b0:706; V7M: @ %bb.0:707; V7M-NEXT: mov.w r2, #-1708; V7M-NEXT: lsl.w r1, r2, r1709; V7M-NEXT: bics r0, r1710; V7M-NEXT: bx lr711;712; V7A-LABEL: bzhi32_b0:713; V7A: @ %bb.0:714; V7A-NEXT: mvn r2, #0715; V7A-NEXT: bic r0, r0, r2, lsl r1716; V7A-NEXT: bx lr717;718; V7A-T-LABEL: bzhi32_b0:719; V7A-T: @ %bb.0:720; V7A-T-NEXT: mov.w r2, #-1721; V7A-T-NEXT: lsl.w r1, r2, r1722; V7A-T-NEXT: bics r0, r1723; V7A-T-NEXT: bx lr724;725; V6M-LABEL: bzhi32_b0:726; V6M: @ %bb.0:727; V6M-NEXT: movs r2, #0728; V6M-NEXT: mvns r2, r2729; V6M-NEXT: lsls r2, r1730; V6M-NEXT: bics r0, r2731; V6M-NEXT: bx lr732 %notmask = shl i32 -1, %numlowbits733 %mask = xor i32 %notmask, -1734 %masked = and i32 %mask, %val735 ret i32 %masked736}737 738define i32 @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits) nounwind {739; V7M-LABEL: bzhi32_b1_indexzext:740; V7M: @ %bb.0:741; V7M-NEXT: mov.w r2, #-1742; V7M-NEXT: lsl.w r1, r2, r1743; V7M-NEXT: bics r0, r1744; V7M-NEXT: bx lr745;746; V7A-LABEL: bzhi32_b1_indexzext:747; V7A: @ %bb.0:748; V7A-NEXT: mvn r2, #0749; V7A-NEXT: bic r0, r0, r2, lsl r1750; V7A-NEXT: bx lr751;752; V7A-T-LABEL: bzhi32_b1_indexzext:753; V7A-T: @ %bb.0:754; V7A-T-NEXT: mov.w r2, #-1755; V7A-T-NEXT: lsl.w r1, r2, r1756; V7A-T-NEXT: bics r0, r1757; V7A-T-NEXT: bx lr758;759; V6M-LABEL: bzhi32_b1_indexzext:760; V6M: @ %bb.0:761; V6M-NEXT: movs r2, #0762; V6M-NEXT: mvns r2, r2763; V6M-NEXT: lsls r2, r1764; V6M-NEXT: bics r0, r2765; V6M-NEXT: bx lr766 %conv = zext i8 %numlowbits to i32767 %notmask = shl i32 -1, %conv768 %mask = xor i32 %notmask, -1769 %masked = and i32 %mask, %val770 ret i32 %masked771}772 773define i32 @bzhi32_b2_load(ptr %w, i32 %numlowbits) nounwind {774; V7M-LABEL: bzhi32_b2_load:775; V7M: @ %bb.0:776; V7M-NEXT: ldr r0, [r0]777; V7M-NEXT: mov.w r2, #-1778; V7M-NEXT: lsl.w r1, r2, r1779; V7M-NEXT: bics r0, r1780; V7M-NEXT: bx lr781;782; V7A-LABEL: bzhi32_b2_load:783; V7A: @ %bb.0:784; V7A-NEXT: ldr r0, [r0]785; V7A-NEXT: mvn r2, #0786; V7A-NEXT: bic r0, r0, r2, lsl r1787; V7A-NEXT: bx lr788;789; V7A-T-LABEL: bzhi32_b2_load:790; V7A-T: @ %bb.0:791; V7A-T-NEXT: ldr r0, [r0]792; V7A-T-NEXT: mov.w r2, #-1793; V7A-T-NEXT: lsl.w r1, r2, r1794; V7A-T-NEXT: bics r0, r1795; V7A-T-NEXT: bx lr796;797; V6M-LABEL: bzhi32_b2_load:798; V6M: @ %bb.0:799; V6M-NEXT: movs r2, #0800; V6M-NEXT: mvns r2, r2801; V6M-NEXT: lsls r2, r1802; V6M-NEXT: ldr r0, [r0]803; V6M-NEXT: bics r0, r2804; V6M-NEXT: bx lr805 %val = load i32, ptr %w806 %notmask = shl i32 -1, %numlowbits807 %mask = xor i32 %notmask, -1808 %masked = and i32 %mask, %val809 ret i32 %masked810}811 812define i32 @bzhi32_b3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {813; V7M-LABEL: bzhi32_b3_load_indexzext:814; V7M: @ %bb.0:815; V7M-NEXT: ldr r0, [r0]816; V7M-NEXT: mov.w r2, #-1817; V7M-NEXT: lsl.w r1, r2, r1818; V7M-NEXT: bics r0, r1819; V7M-NEXT: bx lr820;821; V7A-LABEL: bzhi32_b3_load_indexzext:822; V7A: @ %bb.0:823; V7A-NEXT: ldr r0, [r0]824; V7A-NEXT: mvn r2, #0825; V7A-NEXT: bic r0, r0, r2, lsl r1826; V7A-NEXT: bx lr827;828; V7A-T-LABEL: bzhi32_b3_load_indexzext:829; V7A-T: @ %bb.0:830; V7A-T-NEXT: ldr r0, [r0]831; V7A-T-NEXT: mov.w r2, #-1832; V7A-T-NEXT: lsl.w r1, r2, r1833; V7A-T-NEXT: bics r0, r1834; V7A-T-NEXT: bx lr835;836; V6M-LABEL: bzhi32_b3_load_indexzext:837; V6M: @ %bb.0:838; V6M-NEXT: movs r2, #0839; V6M-NEXT: mvns r2, r2840; V6M-NEXT: lsls r2, r1841; V6M-NEXT: ldr r0, [r0]842; V6M-NEXT: bics r0, r2843; V6M-NEXT: bx lr844 %val = load i32, ptr %w845 %conv = zext i8 %numlowbits to i32846 %notmask = shl i32 -1, %conv847 %mask = xor i32 %notmask, -1848 %masked = and i32 %mask, %val849 ret i32 %masked850}851 852define i32 @bzhi32_b4_commutative(i32 %val, i32 %numlowbits) nounwind {853; V7M-LABEL: bzhi32_b4_commutative:854; V7M: @ %bb.0:855; V7M-NEXT: mov.w r2, #-1856; V7M-NEXT: lsl.w r1, r2, r1857; V7M-NEXT: bics r0, r1858; V7M-NEXT: bx lr859;860; V7A-LABEL: bzhi32_b4_commutative:861; V7A: @ %bb.0:862; V7A-NEXT: mvn r2, #0863; V7A-NEXT: bic r0, r0, r2, lsl r1864; V7A-NEXT: bx lr865;866; V7A-T-LABEL: bzhi32_b4_commutative:867; V7A-T: @ %bb.0:868; V7A-T-NEXT: mov.w r2, #-1869; V7A-T-NEXT: lsl.w r1, r2, r1870; V7A-T-NEXT: bics r0, r1871; V7A-T-NEXT: bx lr872;873; V6M-LABEL: bzhi32_b4_commutative:874; V6M: @ %bb.0:875; V6M-NEXT: movs r2, #0876; V6M-NEXT: mvns r2, r2877; V6M-NEXT: lsls r2, r1878; V6M-NEXT: bics r0, r2879; V6M-NEXT: bx lr880 %notmask = shl i32 -1, %numlowbits881 %mask = xor i32 %notmask, -1882 %masked = and i32 %val, %mask ; swapped order883 ret i32 %masked884}885 886; 64-bit887 888define i64 @bzhi64_b0(i64 %val, i64 %numlowbits) nounwind {889; V7M-LABEL: bzhi64_b0:890; V7M: @ %bb.0:891; V7M-NEXT: mov.w r3, #-1892; V7M-NEXT: lsl.w r12, r3, r2893; V7M-NEXT: subs r2, #32894; V7M-NEXT: it pl895; V7M-NEXT: movpl.w r12, #0896; V7M-NEXT: it pl897; V7M-NEXT: lslpl r3, r2898; V7M-NEXT: bic.w r0, r0, r12899; V7M-NEXT: bics r1, r3900; V7M-NEXT: bx lr901;902; V7A-LABEL: bzhi64_b0:903; V7A: @ %bb.0:904; V7A-NEXT: subs r12, r2, #32905; V7A-NEXT: mvn r3, #0906; V7A-NEXT: lsl r2, r3, r2907; V7A-NEXT: lslpl r3, r3, r12908; V7A-NEXT: movwpl r2, #0909; V7A-NEXT: bic r1, r1, r3910; V7A-NEXT: bic r0, r0, r2911; V7A-NEXT: bx lr912;913; V7A-T-LABEL: bzhi64_b0:914; V7A-T: @ %bb.0:915; V7A-T-NEXT: mov.w r3, #-1916; V7A-T-NEXT: lsl.w r12, r3, r2917; V7A-T-NEXT: subs r2, #32918; V7A-T-NEXT: it pl919; V7A-T-NEXT: movpl.w r12, #0920; V7A-T-NEXT: it pl921; V7A-T-NEXT: lslpl r3, r2922; V7A-T-NEXT: bic.w r0, r0, r12923; V7A-T-NEXT: bics r1, r3924; V7A-T-NEXT: bx lr925;926; V6M-LABEL: bzhi64_b0:927; V6M: @ %bb.0:928; V6M-NEXT: .save {r4, r5, r7, lr}929; V6M-NEXT: push {r4, r5, r7, lr}930; V6M-NEXT: mov r4, r1931; V6M-NEXT: mov r5, r0932; V6M-NEXT: movs r0, #0933; V6M-NEXT: mvns r0, r0934; V6M-NEXT: mov r1, r0935; V6M-NEXT: bl __aeabi_llsl936; V6M-NEXT: bics r5, r0937; V6M-NEXT: bics r4, r1938; V6M-NEXT: mov r0, r5939; V6M-NEXT: mov r1, r4940; V6M-NEXT: pop {r4, r5, r7, pc}941 %notmask = shl i64 -1, %numlowbits942 %mask = xor i64 %notmask, -1943 %masked = and i64 %mask, %val944 ret i64 %masked945}946 947define i64 @bzhi64_b1_indexzext(i64 %val, i8 zeroext %numlowbits) nounwind {948; V7M-LABEL: bzhi64_b1_indexzext:949; V7M: @ %bb.0:950; V7M-NEXT: mov.w r3, #-1951; V7M-NEXT: lsl.w r12, r3, r2952; V7M-NEXT: subs r2, #32953; V7M-NEXT: it pl954; V7M-NEXT: movpl.w r12, #0955; V7M-NEXT: it pl956; V7M-NEXT: lslpl r3, r2957; V7M-NEXT: bic.w r0, r0, r12958; V7M-NEXT: bics r1, r3959; V7M-NEXT: bx lr960;961; V7A-LABEL: bzhi64_b1_indexzext:962; V7A: @ %bb.0:963; V7A-NEXT: subs r12, r2, #32964; V7A-NEXT: mvn r3, #0965; V7A-NEXT: lsl r2, r3, r2966; V7A-NEXT: lslpl r3, r3, r12967; V7A-NEXT: movwpl r2, #0968; V7A-NEXT: bic r1, r1, r3969; V7A-NEXT: bic r0, r0, r2970; V7A-NEXT: bx lr971;972; V7A-T-LABEL: bzhi64_b1_indexzext:973; V7A-T: @ %bb.0:974; V7A-T-NEXT: mov.w r3, #-1975; V7A-T-NEXT: lsl.w r12, r3, r2976; V7A-T-NEXT: subs r2, #32977; V7A-T-NEXT: it pl978; V7A-T-NEXT: movpl.w r12, #0979; V7A-T-NEXT: it pl980; V7A-T-NEXT: lslpl r3, r2981; V7A-T-NEXT: bic.w r0, r0, r12982; V7A-T-NEXT: bics r1, r3983; V7A-T-NEXT: bx lr984;985; V6M-LABEL: bzhi64_b1_indexzext:986; V6M: @ %bb.0:987; V6M-NEXT: .save {r4, r5, r7, lr}988; V6M-NEXT: push {r4, r5, r7, lr}989; V6M-NEXT: mov r4, r1990; V6M-NEXT: mov r5, r0991; V6M-NEXT: movs r0, #0992; V6M-NEXT: mvns r0, r0993; V6M-NEXT: mov r1, r0994; V6M-NEXT: bl __aeabi_llsl995; V6M-NEXT: bics r5, r0996; V6M-NEXT: bics r4, r1997; V6M-NEXT: mov r0, r5998; V6M-NEXT: mov r1, r4999; V6M-NEXT: pop {r4, r5, r7, pc}1000 %conv = zext i8 %numlowbits to i641001 %notmask = shl i64 -1, %conv1002 %mask = xor i64 %notmask, -11003 %masked = and i64 %mask, %val1004 ret i64 %masked1005}1006 1007define i64 @bzhi64_b2_load(ptr %w, i64 %numlowbits) nounwind {1008; V7M-LABEL: bzhi64_b2_load:1009; V7M: @ %bb.0:1010; V7M-NEXT: mov.w r1, #-11011; V7M-NEXT: subs.w r12, r2, #321012; V7M-NEXT: lsl.w r3, r1, r21013; V7M-NEXT: it pl1014; V7M-NEXT: movpl r3, #01015; V7M-NEXT: ldrd r0, r2, [r0]1016; V7M-NEXT: it pl1017; V7M-NEXT: lslpl.w r1, r1, r121018; V7M-NEXT: bics r0, r31019; V7M-NEXT: bic.w r1, r2, r11020; V7M-NEXT: bx lr1021;1022; V7A-LABEL: bzhi64_b2_load:1023; V7A: @ %bb.0:1024; V7A-NEXT: .save {r4, lr}1025; V7A-NEXT: push {r4, lr}1026; V7A-NEXT: ldr r4, [r0]1027; V7A-NEXT: mvn r1, #01028; V7A-NEXT: ldr r3, [r0, #4]1029; V7A-NEXT: subs r0, r2, #321030; V7A-NEXT: lsl r2, r1, r21031; V7A-NEXT: lslpl r1, r1, r01032; V7A-NEXT: movwpl r2, #01033; V7A-NEXT: bic r1, r3, r11034; V7A-NEXT: bic r0, r4, r21035; V7A-NEXT: pop {r4, pc}1036;1037; V7A-T-LABEL: bzhi64_b2_load:1038; V7A-T: @ %bb.0:1039; V7A-T-NEXT: mov.w r1, #-11040; V7A-T-NEXT: ldrd r0, r12, [r0]1041; V7A-T-NEXT: lsl.w r3, r1, r21042; V7A-T-NEXT: subs r2, #321043; V7A-T-NEXT: it pl1044; V7A-T-NEXT: movpl r3, #01045; V7A-T-NEXT: it pl1046; V7A-T-NEXT: lslpl r1, r21047; V7A-T-NEXT: bics r0, r31048; V7A-T-NEXT: bic.w r1, r12, r11049; V7A-T-NEXT: bx lr1050;1051; V6M-LABEL: bzhi64_b2_load:1052; V6M: @ %bb.0:1053; V6M-NEXT: .save {r4, lr}1054; V6M-NEXT: push {r4, lr}1055; V6M-NEXT: mov r4, r01056; V6M-NEXT: movs r0, #01057; V6M-NEXT: mvns r0, r01058; V6M-NEXT: mov r1, r01059; V6M-NEXT: bl __aeabi_llsl1060; V6M-NEXT: ldm r4!, {r2, r3}1061; V6M-NEXT: bics r2, r01062; V6M-NEXT: bics r3, r11063; V6M-NEXT: mov r0, r21064; V6M-NEXT: mov r1, r31065; V6M-NEXT: pop {r4, pc}1066 %val = load i64, ptr %w1067 %notmask = shl i64 -1, %numlowbits1068 %mask = xor i64 %notmask, -11069 %masked = and i64 %mask, %val1070 ret i64 %masked1071}1072 1073define i64 @bzhi64_b3_load_indexzext(ptr %w, i8 zeroext %numlowbits) nounwind {1074; V7M-LABEL: bzhi64_b3_load_indexzext:1075; V7M: @ %bb.0:1076; V7M-NEXT: mov.w r2, #-11077; V7M-NEXT: subs.w r12, r1, #321078; V7M-NEXT: lsl.w r3, r2, r11079; V7M-NEXT: it pl1080; V7M-NEXT: movpl r3, #01081; V7M-NEXT: ldrd r0, r1, [r0]1082; V7M-NEXT: it pl1083; V7M-NEXT: lslpl.w r2, r2, r121084; V7M-NEXT: bics r1, r21085; V7M-NEXT: bics r0, r31086; V7M-NEXT: bx lr1087;1088; V7A-LABEL: bzhi64_b3_load_indexzext:1089; V7A: @ %bb.0:1090; V7A-NEXT: .save {r4, r6, r11, lr}1091; V7A-NEXT: push {r4, r6, r11, lr}1092; V7A-NEXT: mvn r2, #01093; V7A-NEXT: ldr r6, [r0]1094; V7A-NEXT: ldr r3, [r0, #4]1095; V7A-NEXT: subs r0, r1, #321096; V7A-NEXT: lsl r4, r2, r11097; V7A-NEXT: lslpl r2, r2, r01098; V7A-NEXT: movwpl r4, #01099; V7A-NEXT: bic r1, r3, r21100; V7A-NEXT: bic r0, r6, r41101; V7A-NEXT: pop {r4, r6, r11, pc}1102;1103; V7A-T-LABEL: bzhi64_b3_load_indexzext:1104; V7A-T: @ %bb.0:1105; V7A-T-NEXT: mov.w r2, #-11106; V7A-T-NEXT: ldrd r0, r12, [r0]1107; V7A-T-NEXT: lsl.w r3, r2, r11108; V7A-T-NEXT: subs r1, #321109; V7A-T-NEXT: it pl1110; V7A-T-NEXT: movpl r3, #01111; V7A-T-NEXT: it pl1112; V7A-T-NEXT: lslpl r2, r11113; V7A-T-NEXT: bics r0, r31114; V7A-T-NEXT: bic.w r1, r12, r21115; V7A-T-NEXT: bx lr1116;1117; V6M-LABEL: bzhi64_b3_load_indexzext:1118; V6M: @ %bb.0:1119; V6M-NEXT: .save {r4, lr}1120; V6M-NEXT: push {r4, lr}1121; V6M-NEXT: mov r2, r11122; V6M-NEXT: mov r4, r01123; V6M-NEXT: movs r0, #01124; V6M-NEXT: mvns r0, r01125; V6M-NEXT: mov r1, r01126; V6M-NEXT: bl __aeabi_llsl1127; V6M-NEXT: ldm r4!, {r2, r3}1128; V6M-NEXT: bics r2, r01129; V6M-NEXT: bics r3, r11130; V6M-NEXT: mov r0, r21131; V6M-NEXT: mov r1, r31132; V6M-NEXT: pop {r4, pc}1133 %val = load i64, ptr %w1134 %conv = zext i8 %numlowbits to i641135 %notmask = shl i64 -1, %conv1136 %mask = xor i64 %notmask, -11137 %masked = and i64 %mask, %val1138 ret i64 %masked1139}1140 1141define i64 @bzhi64_b4_commutative(i64 %val, i64 %numlowbits) nounwind {1142; V7M-LABEL: bzhi64_b4_commutative:1143; V7M: @ %bb.0:1144; V7M-NEXT: mov.w r3, #-11145; V7M-NEXT: lsl.w r12, r3, r21146; V7M-NEXT: subs r2, #321147; V7M-NEXT: it pl1148; V7M-NEXT: movpl.w r12, #01149; V7M-NEXT: it pl1150; V7M-NEXT: lslpl r3, r21151; V7M-NEXT: bic.w r0, r0, r121152; V7M-NEXT: bics r1, r31153; V7M-NEXT: bx lr1154;1155; V7A-LABEL: bzhi64_b4_commutative:1156; V7A: @ %bb.0:1157; V7A-NEXT: subs r12, r2, #321158; V7A-NEXT: mvn r3, #01159; V7A-NEXT: lsl r2, r3, r21160; V7A-NEXT: lslpl r3, r3, r121161; V7A-NEXT: movwpl r2, #01162; V7A-NEXT: bic r1, r1, r31163; V7A-NEXT: bic r0, r0, r21164; V7A-NEXT: bx lr1165;1166; V7A-T-LABEL: bzhi64_b4_commutative:1167; V7A-T: @ %bb.0:1168; V7A-T-NEXT: mov.w r3, #-11169; V7A-T-NEXT: lsl.w r12, r3, r21170; V7A-T-NEXT: subs r2, #321171; V7A-T-NEXT: it pl1172; V7A-T-NEXT: movpl.w r12, #01173; V7A-T-NEXT: it pl1174; V7A-T-NEXT: lslpl r3, r21175; V7A-T-NEXT: bic.w r0, r0, r121176; V7A-T-NEXT: bics r1, r31177; V7A-T-NEXT: bx lr1178;1179; V6M-LABEL: bzhi64_b4_commutative:1180; V6M: @ %bb.0:1181; V6M-NEXT: .save {r4, r5, r7, lr}1182; V6M-NEXT: push {r4, r5, r7, lr}1183; V6M-NEXT: mov r4, r11184; V6M-NEXT: mov r5, r01185; V6M-NEXT: movs r0, #01186; V6M-NEXT: mvns r0, r01187; V6M-NEXT: mov r1, r01188; V6M-NEXT: bl __aeabi_llsl1189; V6M-NEXT: bics r5, r01190; V6M-NEXT: bics r4, r11191; V6M-NEXT: mov r0, r51192; V6M-NEXT: mov r1, r41193; V6M-NEXT: pop {r4, r5, r7, pc}1194 %notmask = shl i64 -1, %numlowbits1195 %mask = xor i64 %notmask, -11196 %masked = and i64 %val, %mask ; swapped order1197 ret i64 %masked1198}1199 1200; ---------------------------------------------------------------------------- ;1201; Pattern c. 32-bit1202; ---------------------------------------------------------------------------- ;1203 1204define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {1205; V7M-LABEL: bzhi32_c0:1206; V7M: @ %bb.0:1207; V7M-NEXT: rsb.w r1, r1, #321208; V7M-NEXT: lsls r0, r11209; V7M-NEXT: lsrs r0, r11210; V7M-NEXT: bx lr1211;1212; V7A-LABEL: bzhi32_c0:1213; V7A: @ %bb.0:1214; V7A-NEXT: rsb r1, r1, #321215; V7A-NEXT: lsl r0, r0, r11216; V7A-NEXT: lsr r0, r0, r11217; V7A-NEXT: bx lr1218;1219; V7A-T-LABEL: bzhi32_c0:1220; V7A-T: @ %bb.0:1221; V7A-T-NEXT: rsb.w r1, r1, #321222; V7A-T-NEXT: lsls r0, r11223; V7A-T-NEXT: lsrs r0, r11224; V7A-T-NEXT: bx lr1225;1226; V6M-LABEL: bzhi32_c0:1227; V6M: @ %bb.0:1228; V6M-NEXT: movs r2, #321229; V6M-NEXT: subs r1, r2, r11230; V6M-NEXT: lsls r0, r11231; V6M-NEXT: lsrs r0, r11232; V6M-NEXT: bx lr1233 %numhighbits = sub i32 32, %numlowbits1234 %mask = lshr i32 -1, %numhighbits1235 %masked = and i32 %mask, %val1236 ret i32 %masked1237}1238 1239define i32 @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits) nounwind {1240; V7M-LABEL: bzhi32_c1_indexzext:1241; V7M: @ %bb.0:1242; V7M-NEXT: rsb.w r1, r1, #321243; V7M-NEXT: uxtb r1, r11244; V7M-NEXT: lsls r0, r11245; V7M-NEXT: lsrs r0, r11246; V7M-NEXT: bx lr1247;1248; V7A-LABEL: bzhi32_c1_indexzext:1249; V7A: @ %bb.0:1250; V7A-NEXT: rsb r1, r1, #321251; V7A-NEXT: uxtb r1, r11252; V7A-NEXT: lsl r0, r0, r11253; V7A-NEXT: lsr r0, r0, r11254; V7A-NEXT: bx lr1255;1256; V7A-T-LABEL: bzhi32_c1_indexzext:1257; V7A-T: @ %bb.0:1258; V7A-T-NEXT: rsb.w r1, r1, #321259; V7A-T-NEXT: uxtb r1, r11260; V7A-T-NEXT: lsls r0, r11261; V7A-T-NEXT: lsrs r0, r11262; V7A-T-NEXT: bx lr1263;1264; V6M-LABEL: bzhi32_c1_indexzext:1265; V6M: @ %bb.0:1266; V6M-NEXT: movs r2, #321267; V6M-NEXT: subs r1, r2, r11268; V6M-NEXT: uxtb r1, r11269; V6M-NEXT: lsls r0, r11270; V6M-NEXT: lsrs r0, r11271; V6M-NEXT: bx lr1272 %numhighbits = sub i8 32, %numlowbits1273 %sh_prom = zext i8 %numhighbits to i321274 %mask = lshr i32 -1, %sh_prom1275 %masked = and i32 %mask, %val1276 ret i32 %masked1277}1278 1279define i32 @bzhi32_c2_load(ptr %w, i32 %numlowbits) nounwind {1280; V7M-LABEL: bzhi32_c2_load:1281; V7M: @ %bb.0:1282; V7M-NEXT: ldr r0, [r0]1283; V7M-NEXT: rsb.w r1, r1, #321284; V7M-NEXT: lsls r0, r11285; V7M-NEXT: lsrs r0, r11286; V7M-NEXT: bx lr1287;1288; V7A-LABEL: bzhi32_c2_load:1289; V7A: @ %bb.0:1290; V7A-NEXT: ldr r0, [r0]1291; V7A-NEXT: rsb r1, r1, #321292; V7A-NEXT: lsl r0, r0, r11293; V7A-NEXT: lsr r0, r0, r11294; V7A-NEXT: bx lr1295;1296; V7A-T-LABEL: bzhi32_c2_load:1297; V7A-T: @ %bb.0:1298; V7A-T-NEXT: ldr r0, [r0]1299; V7A-T-NEXT: rsb.w r1, r1, #321300; V7A-T-NEXT: lsls r0, r11301; V7A-T-NEXT: lsrs r0, r11302; V7A-T-NEXT: bx lr1303;1304; V6M-LABEL: bzhi32_c2_load:1305; V6M: @ %bb.0:1306; V6M-NEXT: movs r2, #321307; V6M-NEXT: subs r1, r2, r11308; V6M-NEXT: ldr r0, [r0]1309; V6M-NEXT: lsls r0, r11310; V6M-NEXT: lsrs r0, r11311; V6M-NEXT: bx lr1312 %val = load i32, ptr %w1313 %numhighbits = sub i32 32, %numlowbits1314 %mask = lshr i32 -1, %numhighbits1315 %masked = and i32 %mask, %val1316 ret i32 %masked1317}1318 1319define i32 @bzhi32_c3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {1320; V7M-LABEL: bzhi32_c3_load_indexzext:1321; V7M: @ %bb.0:1322; V7M-NEXT: rsb.w r1, r1, #321323; V7M-NEXT: ldr r0, [r0]1324; V7M-NEXT: uxtb r1, r11325; V7M-NEXT: lsls r0, r11326; V7M-NEXT: lsrs r0, r11327; V7M-NEXT: bx lr1328;1329; V7A-LABEL: bzhi32_c3_load_indexzext:1330; V7A: @ %bb.0:1331; V7A-NEXT: rsb r1, r1, #321332; V7A-NEXT: ldr r0, [r0]1333; V7A-NEXT: uxtb r1, r11334; V7A-NEXT: lsl r0, r0, r11335; V7A-NEXT: lsr r0, r0, r11336; V7A-NEXT: bx lr1337;1338; V7A-T-LABEL: bzhi32_c3_load_indexzext:1339; V7A-T: @ %bb.0:1340; V7A-T-NEXT: rsb.w r1, r1, #321341; V7A-T-NEXT: ldr r0, [r0]1342; V7A-T-NEXT: uxtb r1, r11343; V7A-T-NEXT: lsls r0, r11344; V7A-T-NEXT: lsrs r0, r11345; V7A-T-NEXT: bx lr1346;1347; V6M-LABEL: bzhi32_c3_load_indexzext:1348; V6M: @ %bb.0:1349; V6M-NEXT: movs r2, #321350; V6M-NEXT: subs r1, r2, r11351; V6M-NEXT: uxtb r1, r11352; V6M-NEXT: ldr r0, [r0]1353; V6M-NEXT: lsls r0, r11354; V6M-NEXT: lsrs r0, r11355; V6M-NEXT: bx lr1356 %val = load i32, ptr %w1357 %numhighbits = sub i8 32, %numlowbits1358 %sh_prom = zext i8 %numhighbits to i321359 %mask = lshr i32 -1, %sh_prom1360 %masked = and i32 %mask, %val1361 ret i32 %masked1362}1363 1364define i32 @bzhi32_c4_commutative(i32 %val, i32 %numlowbits) nounwind {1365; V7M-LABEL: bzhi32_c4_commutative:1366; V7M: @ %bb.0:1367; V7M-NEXT: rsb.w r1, r1, #321368; V7M-NEXT: lsls r0, r11369; V7M-NEXT: lsrs r0, r11370; V7M-NEXT: bx lr1371;1372; V7A-LABEL: bzhi32_c4_commutative:1373; V7A: @ %bb.0:1374; V7A-NEXT: rsb r1, r1, #321375; V7A-NEXT: lsl r0, r0, r11376; V7A-NEXT: lsr r0, r0, r11377; V7A-NEXT: bx lr1378;1379; V7A-T-LABEL: bzhi32_c4_commutative:1380; V7A-T: @ %bb.0:1381; V7A-T-NEXT: rsb.w r1, r1, #321382; V7A-T-NEXT: lsls r0, r11383; V7A-T-NEXT: lsrs r0, r11384; V7A-T-NEXT: bx lr1385;1386; V6M-LABEL: bzhi32_c4_commutative:1387; V6M: @ %bb.0:1388; V6M-NEXT: movs r2, #321389; V6M-NEXT: subs r1, r2, r11390; V6M-NEXT: lsls r0, r11391; V6M-NEXT: lsrs r0, r11392; V6M-NEXT: bx lr1393 %numhighbits = sub i32 32, %numlowbits1394 %mask = lshr i32 -1, %numhighbits1395 %masked = and i32 %val, %mask ; swapped order1396 ret i32 %masked1397}1398 1399; 64-bit1400 1401define i64 @bzhi64_c0(i64 %val, i64 %numlowbits) nounwind {1402; V7M-LABEL: bzhi64_c0:1403; V7M: @ %bb.0:1404; V7M-NEXT: .save {r7, lr}1405; V7M-NEXT: push {r7, lr}1406; V7M-NEXT: rsbs.w lr, r2, #321407; V7M-NEXT: rsb.w r2, r2, #641408; V7M-NEXT: mov.w r12, #-11409; V7M-NEXT: mov.w r3, #-11410; V7M-NEXT: lsr.w r2, r12, r21411; V7M-NEXT: it pl1412; V7M-NEXT: lsrpl.w r3, r3, lr1413; V7M-NEXT: it pl1414; V7M-NEXT: movpl r2, #01415; V7M-NEXT: ands r0, r31416; V7M-NEXT: ands r1, r21417; V7M-NEXT: pop {r7, pc}1418;1419; V7A-LABEL: bzhi64_c0:1420; V7A: @ %bb.0:1421; V7A-NEXT: .save {r11, lr}1422; V7A-NEXT: push {r11, lr}1423; V7A-NEXT: rsbs lr, r2, #321424; V7A-NEXT: rsb r2, r2, #641425; V7A-NEXT: mvn r12, #01426; V7A-NEXT: mvn r3, #01427; V7A-NEXT: lsr r2, r12, r21428; V7A-NEXT: lsrpl r3, r3, lr1429; V7A-NEXT: movwpl r2, #01430; V7A-NEXT: and r0, r3, r01431; V7A-NEXT: and r1, r2, r11432; V7A-NEXT: pop {r11, pc}1433;1434; V7A-T-LABEL: bzhi64_c0:1435; V7A-T: @ %bb.0:1436; V7A-T-NEXT: .save {r7, lr}1437; V7A-T-NEXT: push {r7, lr}1438; V7A-T-NEXT: rsbs.w lr, r2, #321439; V7A-T-NEXT: rsb.w r2, r2, #641440; V7A-T-NEXT: mov.w r12, #-11441; V7A-T-NEXT: mov.w r3, #-11442; V7A-T-NEXT: lsr.w r2, r12, r21443; V7A-T-NEXT: it pl1444; V7A-T-NEXT: lsrpl.w r3, r3, lr1445; V7A-T-NEXT: it pl1446; V7A-T-NEXT: movpl r2, #01447; V7A-T-NEXT: ands r0, r31448; V7A-T-NEXT: ands r1, r21449; V7A-T-NEXT: pop {r7, pc}1450;1451; V6M-LABEL: bzhi64_c0:1452; V6M: @ %bb.0:1453; V6M-NEXT: .save {r4, r5, r7, lr}1454; V6M-NEXT: push {r4, r5, r7, lr}1455; V6M-NEXT: mov r4, r11456; V6M-NEXT: mov r5, r01457; V6M-NEXT: movs r0, #641458; V6M-NEXT: subs r2, r0, r21459; V6M-NEXT: movs r0, #01460; V6M-NEXT: mvns r0, r01461; V6M-NEXT: mov r1, r01462; V6M-NEXT: bl __aeabi_llsr1463; V6M-NEXT: ands r0, r51464; V6M-NEXT: ands r1, r41465; V6M-NEXT: pop {r4, r5, r7, pc}1466 %numhighbits = sub i64 64, %numlowbits1467 %mask = lshr i64 -1, %numhighbits1468 %masked = and i64 %mask, %val1469 ret i64 %masked1470}1471 1472define i64 @bzhi64_c1_indexzext(i64 %val, i8 %numlowbits) nounwind {1473; V7M-LABEL: bzhi64_c1_indexzext:1474; V7M: @ %bb.0:1475; V7M-NEXT: rsb.w r2, r2, #641476; V7M-NEXT: mov.w r3, #-11477; V7M-NEXT: uxtb r2, r21478; V7M-NEXT: subs.w r12, r2, #321479; V7M-NEXT: lsr.w r2, r3, r21480; V7M-NEXT: it pl1481; V7M-NEXT: lsrpl.w r3, r3, r121482; V7M-NEXT: it pl1483; V7M-NEXT: movpl r2, #01484; V7M-NEXT: ands r0, r31485; V7M-NEXT: ands r1, r21486; V7M-NEXT: bx lr1487;1488; V7A-LABEL: bzhi64_c1_indexzext:1489; V7A: @ %bb.0:1490; V7A-NEXT: .save {r11, lr}1491; V7A-NEXT: push {r11, lr}1492; V7A-NEXT: rsb lr, r2, #641493; V7A-NEXT: mvn r2, #311494; V7A-NEXT: mvn r3, #01495; V7A-NEXT: uxtb r12, lr1496; V7A-NEXT: uxtab r2, r2, lr1497; V7A-NEXT: lsr r12, r3, r121498; V7A-NEXT: cmp r2, #01499; V7A-NEXT: movwpl r12, #01500; V7A-NEXT: lsrpl r3, r3, r21501; V7A-NEXT: and r1, r12, r11502; V7A-NEXT: and r0, r3, r01503; V7A-NEXT: pop {r11, pc}1504;1505; V7A-T-LABEL: bzhi64_c1_indexzext:1506; V7A-T: @ %bb.0:1507; V7A-T-NEXT: .save {r7, lr}1508; V7A-T-NEXT: push {r7, lr}1509; V7A-T-NEXT: rsb.w lr, r2, #641510; V7A-T-NEXT: mvn r2, #311511; V7A-T-NEXT: mov.w r3, #-11512; V7A-T-NEXT: uxtb.w r12, lr1513; V7A-T-NEXT: uxtab r2, r2, lr1514; V7A-T-NEXT: lsr.w r12, r3, r121515; V7A-T-NEXT: cmp r2, #01516; V7A-T-NEXT: it pl1517; V7A-T-NEXT: movpl.w r12, #01518; V7A-T-NEXT: it pl1519; V7A-T-NEXT: lsrpl r3, r21520; V7A-T-NEXT: and.w r1, r1, r121521; V7A-T-NEXT: ands r0, r31522; V7A-T-NEXT: pop {r7, pc}1523;1524; V6M-LABEL: bzhi64_c1_indexzext:1525; V6M: @ %bb.0:1526; V6M-NEXT: .save {r4, r5, r7, lr}1527; V6M-NEXT: push {r4, r5, r7, lr}1528; V6M-NEXT: mov r4, r11529; V6M-NEXT: mov r5, r01530; V6M-NEXT: movs r0, #641531; V6M-NEXT: subs r0, r0, r21532; V6M-NEXT: uxtb r2, r01533; V6M-NEXT: movs r0, #01534; V6M-NEXT: mvns r0, r01535; V6M-NEXT: mov r1, r01536; V6M-NEXT: bl __aeabi_llsr1537; V6M-NEXT: ands r0, r51538; V6M-NEXT: ands r1, r41539; V6M-NEXT: pop {r4, r5, r7, pc}1540 %numhighbits = sub i8 64, %numlowbits1541 %sh_prom = zext i8 %numhighbits to i641542 %mask = lshr i64 -1, %sh_prom1543 %masked = and i64 %mask, %val1544 ret i64 %masked1545}1546 1547define i64 @bzhi64_c2_load(ptr %w, i64 %numlowbits) nounwind {1548; V7M-LABEL: bzhi64_c2_load:1549; V7M: @ %bb.0:1550; V7M-NEXT: rsbs.w r1, r2, #321551; V7M-NEXT: mov.w r3, #-11552; V7M-NEXT: rsb.w r2, r2, #641553; V7M-NEXT: it pl1554; V7M-NEXT: lsrpl r3, r11555; V7M-NEXT: ldrd r0, r1, [r0]1556; V7M-NEXT: mov.w r12, #-11557; V7M-NEXT: lsr.w r2, r12, r21558; V7M-NEXT: it pl1559; V7M-NEXT: movpl r2, #01560; V7M-NEXT: ands r0, r31561; V7M-NEXT: ands r1, r21562; V7M-NEXT: bx lr1563;1564; V7A-LABEL: bzhi64_c2_load:1565; V7A: @ %bb.0:1566; V7A-NEXT: .save {r5, lr}1567; V7A-NEXT: push {r5, lr}1568; V7A-NEXT: rsbs r1, r2, #321569; V7A-NEXT: mvn r3, #01570; V7A-NEXT: mvn r12, #01571; V7A-NEXT: ldm r0, {r0, r5}1572; V7A-NEXT: lsrpl r3, r3, r11573; V7A-NEXT: rsb r1, r2, #641574; V7A-NEXT: and r0, r3, r01575; V7A-NEXT: lsr r1, r12, r11576; V7A-NEXT: movwpl r1, #01577; V7A-NEXT: and r1, r1, r51578; V7A-NEXT: pop {r5, pc}1579;1580; V7A-T-LABEL: bzhi64_c2_load:1581; V7A-T: @ %bb.0:1582; V7A-T-NEXT: .save {r7, lr}1583; V7A-T-NEXT: push {r7, lr}1584; V7A-T-NEXT: rsbs.w r1, r2, #321585; V7A-T-NEXT: mov.w r3, #-11586; V7A-T-NEXT: ldrd r0, lr, [r0]1587; V7A-T-NEXT: it pl1588; V7A-T-NEXT: lsrpl r3, r11589; V7A-T-NEXT: rsb.w r1, r2, #641590; V7A-T-NEXT: mov.w r12, #-11591; V7A-T-NEXT: and.w r0, r0, r31592; V7A-T-NEXT: lsr.w r1, r12, r11593; V7A-T-NEXT: it pl1594; V7A-T-NEXT: movpl r1, #01595; V7A-T-NEXT: and.w r1, r1, lr1596; V7A-T-NEXT: pop {r7, pc}1597;1598; V6M-LABEL: bzhi64_c2_load:1599; V6M: @ %bb.0:1600; V6M-NEXT: .save {r4, lr}1601; V6M-NEXT: push {r4, lr}1602; V6M-NEXT: mov r4, r01603; V6M-NEXT: movs r0, #641604; V6M-NEXT: subs r2, r0, r21605; V6M-NEXT: movs r0, #01606; V6M-NEXT: mvns r0, r01607; V6M-NEXT: mov r1, r01608; V6M-NEXT: bl __aeabi_llsr1609; V6M-NEXT: ldm r4!, {r2, r3}1610; V6M-NEXT: ands r0, r21611; V6M-NEXT: ands r1, r31612; V6M-NEXT: pop {r4, pc}1613 %val = load i64, ptr %w1614 %numhighbits = sub i64 64, %numlowbits1615 %mask = lshr i64 -1, %numhighbits1616 %masked = and i64 %mask, %val1617 ret i64 %masked1618}1619 1620define i64 @bzhi64_c3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {1621; V7M-LABEL: bzhi64_c3_load_indexzext:1622; V7M: @ %bb.0:1623; V7M-NEXT: rsb.w r1, r1, #641624; V7M-NEXT: mov.w r3, #-11625; V7M-NEXT: uxtb r1, r11626; V7M-NEXT: subs.w r2, r1, #321627; V7M-NEXT: lsr.w r1, r3, r11628; V7M-NEXT: it pl1629; V7M-NEXT: lsrpl r3, r21630; V7M-NEXT: ldrd r0, r2, [r0]1631; V7M-NEXT: it pl1632; V7M-NEXT: movpl r1, #01633; V7M-NEXT: ands r1, r21634; V7M-NEXT: ands r0, r31635; V7M-NEXT: bx lr1636;1637; V7A-LABEL: bzhi64_c3_load_indexzext:1638; V7A: @ %bb.0:1639; V7A-NEXT: .save {r4, r6, r11, lr}1640; V7A-NEXT: push {r4, r6, r11, lr}1641; V7A-NEXT: rsb r1, r1, #641642; V7A-NEXT: mvn r4, #311643; V7A-NEXT: mvn r2, #01644; V7A-NEXT: ldr r6, [r0]1645; V7A-NEXT: ldr r3, [r0, #4]1646; V7A-NEXT: uxtb r0, r11647; V7A-NEXT: uxtab r4, r4, r11648; V7A-NEXT: lsr r0, r2, r01649; V7A-NEXT: cmp r4, #01650; V7A-NEXT: movwpl r0, #01651; V7A-NEXT: and r1, r0, r31652; V7A-NEXT: lsrpl r2, r2, r41653; V7A-NEXT: and r0, r2, r61654; V7A-NEXT: pop {r4, r6, r11, pc}1655;1656; V7A-T-LABEL: bzhi64_c3_load_indexzext:1657; V7A-T: @ %bb.0:1658; V7A-T-NEXT: .save {r7, lr}1659; V7A-T-NEXT: push {r7, lr}1660; V7A-T-NEXT: rsb.w r1, r1, #641661; V7A-T-NEXT: mvn r3, #311662; V7A-T-NEXT: ldrd r12, lr, [r0]1663; V7A-T-NEXT: mov.w r2, #-11664; V7A-T-NEXT: uxtb r0, r11665; V7A-T-NEXT: uxtab r3, r3, r11666; V7A-T-NEXT: lsr.w r0, r2, r01667; V7A-T-NEXT: cmp r3, #01668; V7A-T-NEXT: it pl1669; V7A-T-NEXT: movpl r0, #01670; V7A-T-NEXT: and.w r1, r0, lr1671; V7A-T-NEXT: it pl1672; V7A-T-NEXT: lsrpl r2, r31673; V7A-T-NEXT: and.w r0, r2, r121674; V7A-T-NEXT: pop {r7, pc}1675;1676; V6M-LABEL: bzhi64_c3_load_indexzext:1677; V6M: @ %bb.0:1678; V6M-NEXT: .save {r4, lr}1679; V6M-NEXT: push {r4, lr}1680; V6M-NEXT: mov r4, r01681; V6M-NEXT: movs r0, #641682; V6M-NEXT: subs r0, r0, r11683; V6M-NEXT: uxtb r2, r01684; V6M-NEXT: movs r0, #01685; V6M-NEXT: mvns r0, r01686; V6M-NEXT: mov r1, r01687; V6M-NEXT: bl __aeabi_llsr1688; V6M-NEXT: ldm r4!, {r2, r3}1689; V6M-NEXT: ands r0, r21690; V6M-NEXT: ands r1, r31691; V6M-NEXT: pop {r4, pc}1692 %val = load i64, ptr %w1693 %numhighbits = sub i8 64, %numlowbits1694 %sh_prom = zext i8 %numhighbits to i641695 %mask = lshr i64 -1, %sh_prom1696 %masked = and i64 %mask, %val1697 ret i64 %masked1698}1699 1700define i64 @bzhi64_c4_commutative(i64 %val, i64 %numlowbits) nounwind {1701; V7M-LABEL: bzhi64_c4_commutative:1702; V7M: @ %bb.0:1703; V7M-NEXT: .save {r7, lr}1704; V7M-NEXT: push {r7, lr}1705; V7M-NEXT: rsbs.w lr, r2, #321706; V7M-NEXT: rsb.w r2, r2, #641707; V7M-NEXT: mov.w r12, #-11708; V7M-NEXT: mov.w r3, #-11709; V7M-NEXT: lsr.w r2, r12, r21710; V7M-NEXT: it pl1711; V7M-NEXT: lsrpl.w r3, r3, lr1712; V7M-NEXT: it pl1713; V7M-NEXT: movpl r2, #01714; V7M-NEXT: ands r0, r31715; V7M-NEXT: ands r1, r21716; V7M-NEXT: pop {r7, pc}1717;1718; V7A-LABEL: bzhi64_c4_commutative:1719; V7A: @ %bb.0:1720; V7A-NEXT: .save {r11, lr}1721; V7A-NEXT: push {r11, lr}1722; V7A-NEXT: rsbs lr, r2, #321723; V7A-NEXT: rsb r2, r2, #641724; V7A-NEXT: mvn r12, #01725; V7A-NEXT: mvn r3, #01726; V7A-NEXT: lsr r2, r12, r21727; V7A-NEXT: lsrpl r3, r3, lr1728; V7A-NEXT: movwpl r2, #01729; V7A-NEXT: and r0, r0, r31730; V7A-NEXT: and r1, r1, r21731; V7A-NEXT: pop {r11, pc}1732;1733; V7A-T-LABEL: bzhi64_c4_commutative:1734; V7A-T: @ %bb.0:1735; V7A-T-NEXT: .save {r7, lr}1736; V7A-T-NEXT: push {r7, lr}1737; V7A-T-NEXT: rsbs.w lr, r2, #321738; V7A-T-NEXT: rsb.w r2, r2, #641739; V7A-T-NEXT: mov.w r12, #-11740; V7A-T-NEXT: mov.w r3, #-11741; V7A-T-NEXT: lsr.w r2, r12, r21742; V7A-T-NEXT: it pl1743; V7A-T-NEXT: lsrpl.w r3, r3, lr1744; V7A-T-NEXT: it pl1745; V7A-T-NEXT: movpl r2, #01746; V7A-T-NEXT: ands r0, r31747; V7A-T-NEXT: ands r1, r21748; V7A-T-NEXT: pop {r7, pc}1749;1750; V6M-LABEL: bzhi64_c4_commutative:1751; V6M: @ %bb.0:1752; V6M-NEXT: .save {r4, r5, r7, lr}1753; V6M-NEXT: push {r4, r5, r7, lr}1754; V6M-NEXT: mov r4, r11755; V6M-NEXT: mov r5, r01756; V6M-NEXT: movs r0, #641757; V6M-NEXT: subs r2, r0, r21758; V6M-NEXT: movs r0, #01759; V6M-NEXT: mvns r0, r01760; V6M-NEXT: mov r1, r01761; V6M-NEXT: bl __aeabi_llsr1762; V6M-NEXT: ands r0, r51763; V6M-NEXT: ands r1, r41764; V6M-NEXT: pop {r4, r5, r7, pc}1765 %numhighbits = sub i64 64, %numlowbits1766 %mask = lshr i64 -1, %numhighbits1767 %masked = and i64 %val, %mask ; swapped order1768 ret i64 %masked1769}1770 1771; ---------------------------------------------------------------------------- ;1772; Pattern d. 32-bit.1773; ---------------------------------------------------------------------------- ;1774 1775define i32 @bzhi32_d0(i32 %val, i32 %numlowbits) nounwind {1776; V7M-LABEL: bzhi32_d0:1777; V7M: @ %bb.0:1778; V7M-NEXT: rsb.w r1, r1, #321779; V7M-NEXT: lsls r0, r11780; V7M-NEXT: lsrs r0, r11781; V7M-NEXT: bx lr1782;1783; V7A-LABEL: bzhi32_d0:1784; V7A: @ %bb.0:1785; V7A-NEXT: rsb r1, r1, #321786; V7A-NEXT: lsl r0, r0, r11787; V7A-NEXT: lsr r0, r0, r11788; V7A-NEXT: bx lr1789;1790; V7A-T-LABEL: bzhi32_d0:1791; V7A-T: @ %bb.0:1792; V7A-T-NEXT: rsb.w r1, r1, #321793; V7A-T-NEXT: lsls r0, r11794; V7A-T-NEXT: lsrs r0, r11795; V7A-T-NEXT: bx lr1796;1797; V6M-LABEL: bzhi32_d0:1798; V6M: @ %bb.0:1799; V6M-NEXT: movs r2, #321800; V6M-NEXT: subs r1, r2, r11801; V6M-NEXT: lsls r0, r11802; V6M-NEXT: lsrs r0, r11803; V6M-NEXT: bx lr1804 %numhighbits = sub i32 32, %numlowbits1805 %highbitscleared = shl i32 %val, %numhighbits1806 %masked = lshr i32 %highbitscleared, %numhighbits1807 ret i32 %masked1808}1809 1810define i32 @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits) nounwind {1811; V7M-LABEL: bzhi32_d1_indexzext:1812; V7M: @ %bb.0:1813; V7M-NEXT: rsb.w r1, r1, #321814; V7M-NEXT: uxtb r1, r11815; V7M-NEXT: lsls r0, r11816; V7M-NEXT: lsrs r0, r11817; V7M-NEXT: bx lr1818;1819; V7A-LABEL: bzhi32_d1_indexzext:1820; V7A: @ %bb.0:1821; V7A-NEXT: rsb r1, r1, #321822; V7A-NEXT: uxtb r1, r11823; V7A-NEXT: lsl r0, r0, r11824; V7A-NEXT: lsr r0, r0, r11825; V7A-NEXT: bx lr1826;1827; V7A-T-LABEL: bzhi32_d1_indexzext:1828; V7A-T: @ %bb.0:1829; V7A-T-NEXT: rsb.w r1, r1, #321830; V7A-T-NEXT: uxtb r1, r11831; V7A-T-NEXT: lsls r0, r11832; V7A-T-NEXT: lsrs r0, r11833; V7A-T-NEXT: bx lr1834;1835; V6M-LABEL: bzhi32_d1_indexzext:1836; V6M: @ %bb.0:1837; V6M-NEXT: movs r2, #321838; V6M-NEXT: subs r1, r2, r11839; V6M-NEXT: uxtb r1, r11840; V6M-NEXT: lsls r0, r11841; V6M-NEXT: lsrs r0, r11842; V6M-NEXT: bx lr1843 %numhighbits = sub i8 32, %numlowbits1844 %sh_prom = zext i8 %numhighbits to i321845 %highbitscleared = shl i32 %val, %sh_prom1846 %masked = lshr i32 %highbitscleared, %sh_prom1847 ret i32 %masked1848}1849 1850define i32 @bzhi32_d2_load(ptr %w, i32 %numlowbits) nounwind {1851; V7M-LABEL: bzhi32_d2_load:1852; V7M: @ %bb.0:1853; V7M-NEXT: ldr r0, [r0]1854; V7M-NEXT: rsb.w r1, r1, #321855; V7M-NEXT: lsls r0, r11856; V7M-NEXT: lsrs r0, r11857; V7M-NEXT: bx lr1858;1859; V7A-LABEL: bzhi32_d2_load:1860; V7A: @ %bb.0:1861; V7A-NEXT: ldr r0, [r0]1862; V7A-NEXT: rsb r1, r1, #321863; V7A-NEXT: lsl r0, r0, r11864; V7A-NEXT: lsr r0, r0, r11865; V7A-NEXT: bx lr1866;1867; V7A-T-LABEL: bzhi32_d2_load:1868; V7A-T: @ %bb.0:1869; V7A-T-NEXT: ldr r0, [r0]1870; V7A-T-NEXT: rsb.w r1, r1, #321871; V7A-T-NEXT: lsls r0, r11872; V7A-T-NEXT: lsrs r0, r11873; V7A-T-NEXT: bx lr1874;1875; V6M-LABEL: bzhi32_d2_load:1876; V6M: @ %bb.0:1877; V6M-NEXT: movs r2, #321878; V6M-NEXT: subs r1, r2, r11879; V6M-NEXT: ldr r0, [r0]1880; V6M-NEXT: lsls r0, r11881; V6M-NEXT: lsrs r0, r11882; V6M-NEXT: bx lr1883 %val = load i32, ptr %w1884 %numhighbits = sub i32 32, %numlowbits1885 %highbitscleared = shl i32 %val, %numhighbits1886 %masked = lshr i32 %highbitscleared, %numhighbits1887 ret i32 %masked1888}1889 1890define i32 @bzhi32_d3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {1891; V7M-LABEL: bzhi32_d3_load_indexzext:1892; V7M: @ %bb.0:1893; V7M-NEXT: rsb.w r1, r1, #321894; V7M-NEXT: ldr r0, [r0]1895; V7M-NEXT: uxtb r1, r11896; V7M-NEXT: lsls r0, r11897; V7M-NEXT: lsrs r0, r11898; V7M-NEXT: bx lr1899;1900; V7A-LABEL: bzhi32_d3_load_indexzext:1901; V7A: @ %bb.0:1902; V7A-NEXT: rsb r1, r1, #321903; V7A-NEXT: ldr r0, [r0]1904; V7A-NEXT: uxtb r1, r11905; V7A-NEXT: lsl r0, r0, r11906; V7A-NEXT: lsr r0, r0, r11907; V7A-NEXT: bx lr1908;1909; V7A-T-LABEL: bzhi32_d3_load_indexzext:1910; V7A-T: @ %bb.0:1911; V7A-T-NEXT: rsb.w r1, r1, #321912; V7A-T-NEXT: ldr r0, [r0]1913; V7A-T-NEXT: uxtb r1, r11914; V7A-T-NEXT: lsls r0, r11915; V7A-T-NEXT: lsrs r0, r11916; V7A-T-NEXT: bx lr1917;1918; V6M-LABEL: bzhi32_d3_load_indexzext:1919; V6M: @ %bb.0:1920; V6M-NEXT: movs r2, #321921; V6M-NEXT: subs r1, r2, r11922; V6M-NEXT: uxtb r1, r11923; V6M-NEXT: ldr r0, [r0]1924; V6M-NEXT: lsls r0, r11925; V6M-NEXT: lsrs r0, r11926; V6M-NEXT: bx lr1927 %val = load i32, ptr %w1928 %numhighbits = sub i8 32, %numlowbits1929 %sh_prom = zext i8 %numhighbits to i321930 %highbitscleared = shl i32 %val, %sh_prom1931 %masked = lshr i32 %highbitscleared, %sh_prom1932 ret i32 %masked1933}1934 1935; 64-bit.1936 1937define i64 @bzhi64_d0(i64 %val, i64 %numlowbits) nounwind {1938; V7M-LABEL: bzhi64_d0:1939; V7M: @ %bb.0:1940; V7M-NEXT: .save {r7, lr}1941; V7M-NEXT: push {r7, lr}1942; V7M-NEXT: rsb.w r3, r2, #641943; V7M-NEXT: rsbs.w r2, r2, #321944; V7M-NEXT: rsb.w lr, r3, #321945; V7M-NEXT: lsl.w r12, r1, r31946; V7M-NEXT: lsr.w r1, r0, lr1947; V7M-NEXT: orr.w r1, r1, r121948; V7M-NEXT: it pl1949; V7M-NEXT: lslpl.w r1, r0, r21950; V7M-NEXT: lsl.w r0, r0, r31951; V7M-NEXT: it pl1952; V7M-NEXT: movpl r0, #01953; V7M-NEXT: lsl.w r12, r1, lr1954; V7M-NEXT: lsr.w r0, r0, r31955; V7M-NEXT: orr.w r0, r0, r121956; V7M-NEXT: it pl1957; V7M-NEXT: lsrpl.w r0, r1, r21958; V7M-NEXT: lsr.w r1, r1, r31959; V7M-NEXT: it pl1960; V7M-NEXT: movpl r1, #01961; V7M-NEXT: pop {r7, pc}1962;1963; V7A-LABEL: bzhi64_d0:1964; V7A: @ %bb.0:1965; V7A-NEXT: .save {r11, lr}1966; V7A-NEXT: push {r11, lr}1967; V7A-NEXT: rsb lr, r2, #641968; V7A-NEXT: rsbs r2, r2, #321969; V7A-NEXT: rsb r12, lr, #321970; V7A-NEXT: lsr r3, r0, r121971; V7A-NEXT: orr r1, r3, r1, lsl lr1972; V7A-NEXT: lslpl r1, r0, r21973; V7A-NEXT: lsl r0, r0, lr1974; V7A-NEXT: movwpl r0, #01975; V7A-NEXT: lsr r0, r0, lr1976; V7A-NEXT: orr r0, r0, r1, lsl r121977; V7A-NEXT: lsrpl r0, r1, r21978; V7A-NEXT: lsr r1, r1, lr1979; V7A-NEXT: movwpl r1, #01980; V7A-NEXT: pop {r11, pc}1981;1982; V7A-T-LABEL: bzhi64_d0:1983; V7A-T: @ %bb.0:1984; V7A-T-NEXT: .save {r7, lr}1985; V7A-T-NEXT: push {r7, lr}1986; V7A-T-NEXT: rsb.w r3, r2, #641987; V7A-T-NEXT: rsbs.w r2, r2, #321988; V7A-T-NEXT: rsb.w lr, r3, #321989; V7A-T-NEXT: lsl.w r12, r1, r31990; V7A-T-NEXT: lsr.w r1, r0, lr1991; V7A-T-NEXT: orr.w r1, r1, r121992; V7A-T-NEXT: it pl1993; V7A-T-NEXT: lslpl.w r1, r0, r21994; V7A-T-NEXT: lsl.w r0, r0, r31995; V7A-T-NEXT: it pl1996; V7A-T-NEXT: movpl r0, #01997; V7A-T-NEXT: lsl.w r12, r1, lr1998; V7A-T-NEXT: lsr.w r0, r0, r31999; V7A-T-NEXT: orr.w r0, r0, r122000; V7A-T-NEXT: it pl2001; V7A-T-NEXT: lsrpl.w r0, r1, r22002; V7A-T-NEXT: lsr.w r1, r1, r32003; V7A-T-NEXT: it pl2004; V7A-T-NEXT: movpl r1, #02005; V7A-T-NEXT: pop {r7, pc}2006;2007; V6M-LABEL: bzhi64_d0:2008; V6M: @ %bb.0:2009; V6M-NEXT: .save {r4, lr}2010; V6M-NEXT: push {r4, lr}2011; V6M-NEXT: movs r3, #642012; V6M-NEXT: subs r4, r3, r22013; V6M-NEXT: mov r2, r42014; V6M-NEXT: bl __aeabi_llsl2015; V6M-NEXT: mov r2, r42016; V6M-NEXT: bl __aeabi_llsr2017; V6M-NEXT: pop {r4, pc}2018 %numhighbits = sub i64 64, %numlowbits2019 %highbitscleared = shl i64 %val, %numhighbits2020 %masked = lshr i64 %highbitscleared, %numhighbits2021 ret i64 %masked2022}2023 2024define i64 @bzhi64_d1_indexzext(i64 %val, i8 %numlowbits) nounwind {2025; V7M-LABEL: bzhi64_d1_indexzext:2026; V7M: @ %bb.0:2027; V7M-NEXT: rsb.w r2, r2, #642028; V7M-NEXT: uxtb r2, r22029; V7M-NEXT: rsb.w r3, r2, #322030; V7M-NEXT: lsl.w r12, r1, r22031; V7M-NEXT: lsr.w r1, r0, r32032; V7M-NEXT: orr.w r1, r1, r122033; V7M-NEXT: subs.w r12, r2, #322034; V7M-NEXT: it pl2035; V7M-NEXT: lslpl.w r1, r0, r122036; V7M-NEXT: lsl.w r0, r0, r22037; V7M-NEXT: it pl2038; V7M-NEXT: movpl r0, #02039; V7M-NEXT: lsl.w r3, r1, r32040; V7M-NEXT: lsr.w r0, r0, r22041; V7M-NEXT: orr.w r0, r0, r32042; V7M-NEXT: it pl2043; V7M-NEXT: lsrpl.w r0, r1, r122044; V7M-NEXT: lsr.w r1, r1, r22045; V7M-NEXT: it pl2046; V7M-NEXT: movpl r1, #02047; V7M-NEXT: bx lr2048;2049; V7A-LABEL: bzhi64_d1_indexzext:2050; V7A: @ %bb.0:2051; V7A-NEXT: .save {r11, lr}2052; V7A-NEXT: push {r11, lr}2053; V7A-NEXT: rsb lr, r2, #642054; V7A-NEXT: uxtb r3, lr2055; V7A-NEXT: rsb r12, r3, #322056; V7A-NEXT: lsr r2, r0, r122057; V7A-NEXT: orr r1, r2, r1, lsl r32058; V7A-NEXT: mvn r2, #312059; V7A-NEXT: uxtab r2, r2, lr2060; V7A-NEXT: cmp r2, #02061; V7A-NEXT: lslpl r1, r0, r22062; V7A-NEXT: lsl r0, r0, r32063; V7A-NEXT: movwpl r0, #02064; V7A-NEXT: lsr r0, r0, r32065; V7A-NEXT: orr r0, r0, r1, lsl r122066; V7A-NEXT: lsrpl r0, r1, r22067; V7A-NEXT: lsr r1, r1, r32068; V7A-NEXT: movwpl r1, #02069; V7A-NEXT: pop {r11, pc}2070;2071; V7A-T-LABEL: bzhi64_d1_indexzext:2072; V7A-T: @ %bb.0:2073; V7A-T-NEXT: .save {r4, lr}2074; V7A-T-NEXT: push {r4, lr}2075; V7A-T-NEXT: rsb.w r4, r2, #642076; V7A-T-NEXT: mvn r2, #312077; V7A-T-NEXT: uxtb r3, r42078; V7A-T-NEXT: rsb.w lr, r3, #322079; V7A-T-NEXT: lsl.w r12, r1, r32080; V7A-T-NEXT: uxtab r2, r2, r42081; V7A-T-NEXT: lsr.w r1, r0, lr2082; V7A-T-NEXT: cmp r2, #02083; V7A-T-NEXT: orr.w r1, r1, r122084; V7A-T-NEXT: it pl2085; V7A-T-NEXT: lslpl.w r1, r0, r22086; V7A-T-NEXT: lsl.w r0, r0, r32087; V7A-T-NEXT: it pl2088; V7A-T-NEXT: movpl r0, #02089; V7A-T-NEXT: lsl.w r4, r1, lr2090; V7A-T-NEXT: lsr.w r0, r0, r32091; V7A-T-NEXT: orr.w r0, r0, r42092; V7A-T-NEXT: it pl2093; V7A-T-NEXT: lsrpl.w r0, r1, r22094; V7A-T-NEXT: lsr.w r1, r1, r32095; V7A-T-NEXT: it pl2096; V7A-T-NEXT: movpl r1, #02097; V7A-T-NEXT: pop {r4, pc}2098;2099; V6M-LABEL: bzhi64_d1_indexzext:2100; V6M: @ %bb.0:2101; V6M-NEXT: .save {r4, lr}2102; V6M-NEXT: push {r4, lr}2103; V6M-NEXT: movs r3, #642104; V6M-NEXT: subs r2, r3, r22105; V6M-NEXT: uxtb r4, r22106; V6M-NEXT: mov r2, r42107; V6M-NEXT: bl __aeabi_llsl2108; V6M-NEXT: mov r2, r42109; V6M-NEXT: bl __aeabi_llsr2110; V6M-NEXT: pop {r4, pc}2111 %numhighbits = sub i8 64, %numlowbits2112 %sh_prom = zext i8 %numhighbits to i642113 %highbitscleared = shl i64 %val, %sh_prom2114 %masked = lshr i64 %highbitscleared, %sh_prom2115 ret i64 %masked2116}2117 2118define i64 @bzhi64_d2_load(ptr %w, i64 %numlowbits) nounwind {2119; V7M-LABEL: bzhi64_d2_load:2120; V7M: @ %bb.0:2121; V7M-NEXT: .save {r7, lr}2122; V7M-NEXT: push {r7, lr}2123; V7M-NEXT: rsb.w r1, r2, #642124; V7M-NEXT: ldrd r0, r3, [r0]2125; V7M-NEXT: rsb.w lr, r1, #322126; V7M-NEXT: rsbs.w r2, r2, #322127; V7M-NEXT: lsl.w r12, r3, r12128; V7M-NEXT: lsr.w r3, r0, lr2129; V7M-NEXT: orr.w r3, r3, r122130; V7M-NEXT: it pl2131; V7M-NEXT: lslpl.w r3, r0, r22132; V7M-NEXT: lsl.w r0, r0, r12133; V7M-NEXT: it pl2134; V7M-NEXT: movpl r0, #02135; V7M-NEXT: lsl.w r12, r3, lr2136; V7M-NEXT: lsr.w r0, r0, r12137; V7M-NEXT: lsr.w r1, r3, r12138; V7M-NEXT: orr.w r0, r0, r122139; V7M-NEXT: it pl2140; V7M-NEXT: lsrpl.w r0, r3, r22141; V7M-NEXT: it pl2142; V7M-NEXT: movpl r1, #02143; V7M-NEXT: pop {r7, pc}2144;2145; V7A-LABEL: bzhi64_d2_load:2146; V7A: @ %bb.0:2147; V7A-NEXT: .save {r5, lr}2148; V7A-NEXT: push {r5, lr}2149; V7A-NEXT: rsb r3, r2, #642150; V7A-NEXT: ldm r0, {r0, r5}2151; V7A-NEXT: rsb r12, r3, #322152; V7A-NEXT: rsbs r2, r2, #322153; V7A-NEXT: lsr r1, r0, r122154; V7A-NEXT: orr r1, r1, r5, lsl r32155; V7A-NEXT: lslpl r1, r0, r22156; V7A-NEXT: lsl r0, r0, r32157; V7A-NEXT: movwpl r0, #02158; V7A-NEXT: lsr r0, r0, r32159; V7A-NEXT: orr r0, r0, r1, lsl r122160; V7A-NEXT: lsrpl r0, r1, r22161; V7A-NEXT: lsr r1, r1, r32162; V7A-NEXT: movwpl r1, #02163; V7A-NEXT: pop {r5, pc}2164;2165; V7A-T-LABEL: bzhi64_d2_load:2166; V7A-T: @ %bb.0:2167; V7A-T-NEXT: .save {r7, lr}2168; V7A-T-NEXT: push {r7, lr}2169; V7A-T-NEXT: rsb.w r3, r2, #642170; V7A-T-NEXT: ldrd r0, r1, [r0]2171; V7A-T-NEXT: rsb.w lr, r3, #322172; V7A-T-NEXT: rsbs.w r2, r2, #322173; V7A-T-NEXT: lsl.w r12, r1, r32174; V7A-T-NEXT: lsr.w r1, r0, lr2175; V7A-T-NEXT: orr.w r1, r1, r122176; V7A-T-NEXT: it pl2177; V7A-T-NEXT: lslpl.w r1, r0, r22178; V7A-T-NEXT: lsl.w r0, r0, r32179; V7A-T-NEXT: it pl2180; V7A-T-NEXT: movpl r0, #02181; V7A-T-NEXT: lsl.w r12, r1, lr2182; V7A-T-NEXT: lsr.w r0, r0, r32183; V7A-T-NEXT: orr.w r0, r0, r122184; V7A-T-NEXT: it pl2185; V7A-T-NEXT: lsrpl.w r0, r1, r22186; V7A-T-NEXT: lsr.w r1, r1, r32187; V7A-T-NEXT: it pl2188; V7A-T-NEXT: movpl r1, #02189; V7A-T-NEXT: pop {r7, pc}2190;2191; V6M-LABEL: bzhi64_d2_load:2192; V6M: @ %bb.0:2193; V6M-NEXT: .save {r4, lr}2194; V6M-NEXT: push {r4, lr}2195; V6M-NEXT: movs r1, #642196; V6M-NEXT: subs r4, r1, r22197; V6M-NEXT: ldr r2, [r0]2198; V6M-NEXT: ldr r1, [r0, #4]2199; V6M-NEXT: mov r0, r22200; V6M-NEXT: mov r2, r42201; V6M-NEXT: bl __aeabi_llsl2202; V6M-NEXT: mov r2, r42203; V6M-NEXT: bl __aeabi_llsr2204; V6M-NEXT: pop {r4, pc}2205 %val = load i64, ptr %w2206 %numhighbits = sub i64 64, %numlowbits2207 %highbitscleared = shl i64 %val, %numhighbits2208 %masked = lshr i64 %highbitscleared, %numhighbits2209 ret i64 %masked2210}2211 2212define i64 @bzhi64_d3_load_indexzext(ptr %w, i8 %numlowbits) nounwind {2213; V7M-LABEL: bzhi64_d3_load_indexzext:2214; V7M: @ %bb.0:2215; V7M-NEXT: rsb.w r1, r1, #642216; V7M-NEXT: ldrd r0, r2, [r0]2217; V7M-NEXT: uxtb r1, r12218; V7M-NEXT: rsb.w r3, r1, #322219; V7M-NEXT: lsl.w r12, r2, r12220; V7M-NEXT: lsr.w r2, r0, r32221; V7M-NEXT: orr.w r2, r2, r122222; V7M-NEXT: subs.w r12, r1, #322223; V7M-NEXT: it pl2224; V7M-NEXT: lslpl.w r2, r0, r122225; V7M-NEXT: lsl.w r0, r0, r12226; V7M-NEXT: it pl2227; V7M-NEXT: movpl r0, #02228; V7M-NEXT: lsl.w r3, r2, r32229; V7M-NEXT: lsr.w r0, r0, r12230; V7M-NEXT: lsr.w r1, r2, r12231; V7M-NEXT: orr.w r0, r0, r32232; V7M-NEXT: it pl2233; V7M-NEXT: lsrpl.w r0, r2, r122234; V7M-NEXT: it pl2235; V7M-NEXT: movpl r1, #02236; V7M-NEXT: bx lr2237;2238; V7A-LABEL: bzhi64_d3_load_indexzext:2239; V7A: @ %bb.0:2240; V7A-NEXT: .save {r5, lr}2241; V7A-NEXT: push {r5, lr}2242; V7A-NEXT: rsb r1, r1, #642243; V7A-NEXT: ldm r0, {r0, r5}2244; V7A-NEXT: uxtb r2, r12245; V7A-NEXT: rsb r12, r2, #322246; V7A-NEXT: lsr r3, r0, r122247; V7A-NEXT: orr r3, r3, r5, lsl r22248; V7A-NEXT: mvn r5, #312249; V7A-NEXT: uxtab r1, r5, r12250; V7A-NEXT: cmp r1, #02251; V7A-NEXT: lslpl r3, r0, r12252; V7A-NEXT: lsl r0, r0, r22253; V7A-NEXT: movwpl r0, #02254; V7A-NEXT: lsr r0, r0, r22255; V7A-NEXT: orr r0, r0, r3, lsl r122256; V7A-NEXT: lsrpl r0, r3, r12257; V7A-NEXT: lsr r1, r3, r22258; V7A-NEXT: movwpl r1, #02259; V7A-NEXT: pop {r5, pc}2260;2261; V7A-T-LABEL: bzhi64_d3_load_indexzext:2262; V7A-T: @ %bb.0:2263; V7A-T-NEXT: .save {r4, lr}2264; V7A-T-NEXT: push {r4, lr}2265; V7A-T-NEXT: rsb.w r4, r1, #642266; V7A-T-NEXT: ldrd r0, r2, [r0]2267; V7A-T-NEXT: mvn r1, #312268; V7A-T-NEXT: uxtb r3, r42269; V7A-T-NEXT: rsb.w lr, r3, #322270; V7A-T-NEXT: lsl.w r12, r2, r32271; V7A-T-NEXT: uxtab r1, r1, r42272; V7A-T-NEXT: lsr.w r2, r0, lr2273; V7A-T-NEXT: cmp r1, #02274; V7A-T-NEXT: orr.w r2, r2, r122275; V7A-T-NEXT: it pl2276; V7A-T-NEXT: lslpl.w r2, r0, r12277; V7A-T-NEXT: lsl.w r0, r0, r32278; V7A-T-NEXT: it pl2279; V7A-T-NEXT: movpl r0, #02280; V7A-T-NEXT: lsl.w r4, r2, lr2281; V7A-T-NEXT: lsr.w r0, r0, r32282; V7A-T-NEXT: orr.w r0, r0, r42283; V7A-T-NEXT: it pl2284; V7A-T-NEXT: lsrpl.w r0, r2, r12285; V7A-T-NEXT: lsr.w r1, r2, r32286; V7A-T-NEXT: it pl2287; V7A-T-NEXT: movpl r1, #02288; V7A-T-NEXT: pop {r4, pc}2289;2290; V6M-LABEL: bzhi64_d3_load_indexzext:2291; V6M: @ %bb.0:2292; V6M-NEXT: .save {r4, lr}2293; V6M-NEXT: push {r4, lr}2294; V6M-NEXT: movs r2, #642295; V6M-NEXT: subs r1, r2, r12296; V6M-NEXT: uxtb r4, r12297; V6M-NEXT: ldr r2, [r0]2298; V6M-NEXT: ldr r1, [r0, #4]2299; V6M-NEXT: mov r0, r22300; V6M-NEXT: mov r2, r42301; V6M-NEXT: bl __aeabi_llsl2302; V6M-NEXT: mov r2, r42303; V6M-NEXT: bl __aeabi_llsr2304; V6M-NEXT: pop {r4, pc}2305 %val = load i64, ptr %w2306 %numhighbits = sub i8 64, %numlowbits2307 %sh_prom = zext i8 %numhighbits to i642308 %highbitscleared = shl i64 %val, %sh_prom2309 %masked = lshr i64 %highbitscleared, %sh_prom2310 ret i64 %masked2311}2312 2313; ---------------------------------------------------------------------------- ;2314; Constant mask2315; ---------------------------------------------------------------------------- ;2316 2317; 32-bit2318 2319define i32 @bzhi32_constant_mask32(i32 %val) nounwind {2320; V7M-LABEL: bzhi32_constant_mask32:2321; V7M: @ %bb.0:2322; V7M-NEXT: bic r0, r0, #-21474836482323; V7M-NEXT: bx lr2324;2325; V7A-LABEL: bzhi32_constant_mask32:2326; V7A: @ %bb.0:2327; V7A-NEXT: bic r0, r0, #-21474836482328; V7A-NEXT: bx lr2329;2330; V7A-T-LABEL: bzhi32_constant_mask32:2331; V7A-T: @ %bb.0:2332; V7A-T-NEXT: bic r0, r0, #-21474836482333; V7A-T-NEXT: bx lr2334;2335; V6M-LABEL: bzhi32_constant_mask32:2336; V6M: @ %bb.0:2337; V6M-NEXT: movs r1, #12338; V6M-NEXT: lsls r1, r1, #312339; V6M-NEXT: bics r0, r12340; V6M-NEXT: bx lr2341 %masked = and i32 %val, 21474836472342 ret i32 %masked2343}2344 2345define i32 @bzhi32_constant_mask32_load(ptr %val) nounwind {2346; V7M-LABEL: bzhi32_constant_mask32_load:2347; V7M: @ %bb.0:2348; V7M-NEXT: ldr r0, [r0]2349; V7M-NEXT: bic r0, r0, #-21474836482350; V7M-NEXT: bx lr2351;2352; V7A-LABEL: bzhi32_constant_mask32_load:2353; V7A: @ %bb.0:2354; V7A-NEXT: ldr r0, [r0]2355; V7A-NEXT: bic r0, r0, #-21474836482356; V7A-NEXT: bx lr2357;2358; V7A-T-LABEL: bzhi32_constant_mask32_load:2359; V7A-T: @ %bb.0:2360; V7A-T-NEXT: ldr r0, [r0]2361; V7A-T-NEXT: bic r0, r0, #-21474836482362; V7A-T-NEXT: bx lr2363;2364; V6M-LABEL: bzhi32_constant_mask32_load:2365; V6M: @ %bb.0:2366; V6M-NEXT: movs r1, #12367; V6M-NEXT: lsls r1, r1, #312368; V6M-NEXT: ldr r0, [r0]2369; V6M-NEXT: bics r0, r12370; V6M-NEXT: bx lr2371 %val1 = load i32, ptr %val2372 %masked = and i32 %val1, 21474836472373 ret i32 %masked2374}2375 2376define i32 @bzhi32_constant_mask16(i32 %val) nounwind {2377; V7M-LABEL: bzhi32_constant_mask16:2378; V7M: @ %bb.0:2379; V7M-NEXT: bfc r0, #15, #172380; V7M-NEXT: bx lr2381;2382; V7A-LABEL: bzhi32_constant_mask16:2383; V7A: @ %bb.0:2384; V7A-NEXT: bfc r0, #15, #172385; V7A-NEXT: bx lr2386;2387; V7A-T-LABEL: bzhi32_constant_mask16:2388; V7A-T: @ %bb.0:2389; V7A-T-NEXT: bfc r0, #15, #172390; V7A-T-NEXT: bx lr2391;2392; V6M-LABEL: bzhi32_constant_mask16:2393; V6M: @ %bb.0:2394; V6M-NEXT: ldr r1, .LCPI41_02395; V6M-NEXT: ands r0, r12396; V6M-NEXT: bx lr2397; V6M-NEXT: .p2align 22398; V6M-NEXT: @ %bb.1:2399; V6M-NEXT: .LCPI41_0:2400; V6M-NEXT: .long 32767 @ 0x7fff2401 %masked = and i32 %val, 327672402 ret i32 %masked2403}2404 2405define i32 @bzhi32_constant_mask16_load(ptr %val) nounwind {2406; V7M-LABEL: bzhi32_constant_mask16_load:2407; V7M: @ %bb.0:2408; V7M-NEXT: ldr r0, [r0]2409; V7M-NEXT: bfc r0, #15, #172410; V7M-NEXT: bx lr2411;2412; V7A-LABEL: bzhi32_constant_mask16_load:2413; V7A: @ %bb.0:2414; V7A-NEXT: ldr r0, [r0]2415; V7A-NEXT: bfc r0, #15, #172416; V7A-NEXT: bx lr2417;2418; V7A-T-LABEL: bzhi32_constant_mask16_load:2419; V7A-T: @ %bb.0:2420; V7A-T-NEXT: ldr r0, [r0]2421; V7A-T-NEXT: bfc r0, #15, #172422; V7A-T-NEXT: bx lr2423;2424; V6M-LABEL: bzhi32_constant_mask16_load:2425; V6M: @ %bb.0:2426; V6M-NEXT: ldr r1, [r0]2427; V6M-NEXT: ldr r0, .LCPI42_02428; V6M-NEXT: ands r0, r12429; V6M-NEXT: bx lr2430; V6M-NEXT: .p2align 22431; V6M-NEXT: @ %bb.1:2432; V6M-NEXT: .LCPI42_0:2433; V6M-NEXT: .long 32767 @ 0x7fff2434 %val1 = load i32, ptr %val2435 %masked = and i32 %val1, 327672436 ret i32 %masked2437}2438 2439define i32 @bzhi32_constant_mask8(i32 %val) nounwind {2440; V7M-LABEL: bzhi32_constant_mask8:2441; V7M: @ %bb.0:2442; V7M-NEXT: and r0, r0, #1272443; V7M-NEXT: bx lr2444;2445; V7A-LABEL: bzhi32_constant_mask8:2446; V7A: @ %bb.0:2447; V7A-NEXT: and r0, r0, #1272448; V7A-NEXT: bx lr2449;2450; V7A-T-LABEL: bzhi32_constant_mask8:2451; V7A-T: @ %bb.0:2452; V7A-T-NEXT: and r0, r0, #1272453; V7A-T-NEXT: bx lr2454;2455; V6M-LABEL: bzhi32_constant_mask8:2456; V6M: @ %bb.0:2457; V6M-NEXT: movs r1, #1272458; V6M-NEXT: ands r0, r12459; V6M-NEXT: bx lr2460 %masked = and i32 %val, 1272461 ret i32 %masked2462}2463 2464define i32 @bzhi32_constant_mask8_load(ptr %val) nounwind {2465; V7M-LABEL: bzhi32_constant_mask8_load:2466; V7M: @ %bb.0:2467; V7M-NEXT: ldr r0, [r0]2468; V7M-NEXT: and r0, r0, #1272469; V7M-NEXT: bx lr2470;2471; V7A-LABEL: bzhi32_constant_mask8_load:2472; V7A: @ %bb.0:2473; V7A-NEXT: ldr r0, [r0]2474; V7A-NEXT: and r0, r0, #1272475; V7A-NEXT: bx lr2476;2477; V7A-T-LABEL: bzhi32_constant_mask8_load:2478; V7A-T: @ %bb.0:2479; V7A-T-NEXT: ldr r0, [r0]2480; V7A-T-NEXT: and r0, r0, #1272481; V7A-T-NEXT: bx lr2482;2483; V6M-LABEL: bzhi32_constant_mask8_load:2484; V6M: @ %bb.0:2485; V6M-NEXT: ldr r1, [r0]2486; V6M-NEXT: movs r0, #1272487; V6M-NEXT: ands r0, r12488; V6M-NEXT: bx lr2489 %val1 = load i32, ptr %val2490 %masked = and i32 %val1, 1272491 ret i32 %masked2492}2493 2494; 64-bit2495 2496define i64 @bzhi64_constant_mask64(i64 %val) nounwind {2497; V7M-LABEL: bzhi64_constant_mask64:2498; V7M: @ %bb.0:2499; V7M-NEXT: bic r1, r1, #-10737418242500; V7M-NEXT: bx lr2501;2502; V7A-LABEL: bzhi64_constant_mask64:2503; V7A: @ %bb.0:2504; V7A-NEXT: bic r1, r1, #-10737418242505; V7A-NEXT: bx lr2506;2507; V7A-T-LABEL: bzhi64_constant_mask64:2508; V7A-T: @ %bb.0:2509; V7A-T-NEXT: bic r1, r1, #-10737418242510; V7A-T-NEXT: bx lr2511;2512; V6M-LABEL: bzhi64_constant_mask64:2513; V6M: @ %bb.0:2514; V6M-NEXT: movs r2, #32515; V6M-NEXT: lsls r2, r2, #302516; V6M-NEXT: bics r1, r22517; V6M-NEXT: bx lr2518 %masked = and i64 %val, 46116860184273879032519 ret i64 %masked2520}2521 2522define i64 @bzhi64_constant_mask64_load(ptr %val) nounwind {2523; V7M-LABEL: bzhi64_constant_mask64_load:2524; V7M: @ %bb.0:2525; V7M-NEXT: ldrd r0, r1, [r0]2526; V7M-NEXT: bic r1, r1, #-10737418242527; V7M-NEXT: bx lr2528;2529; V7A-LABEL: bzhi64_constant_mask64_load:2530; V7A: @ %bb.0:2531; V7A-NEXT: ldrd r0, r1, [r0]2532; V7A-NEXT: bic r1, r1, #-10737418242533; V7A-NEXT: bx lr2534;2535; V7A-T-LABEL: bzhi64_constant_mask64_load:2536; V7A-T: @ %bb.0:2537; V7A-T-NEXT: ldrd r0, r1, [r0]2538; V7A-T-NEXT: bic r1, r1, #-10737418242539; V7A-T-NEXT: bx lr2540;2541; V6M-LABEL: bzhi64_constant_mask64_load:2542; V6M: @ %bb.0:2543; V6M-NEXT: movs r1, #32544; V6M-NEXT: lsls r3, r1, #302545; V6M-NEXT: ldr r2, [r0]2546; V6M-NEXT: ldr r1, [r0, #4]2547; V6M-NEXT: bics r1, r32548; V6M-NEXT: mov r0, r22549; V6M-NEXT: bx lr2550 %val1 = load i64, ptr %val2551 %masked = and i64 %val1, 46116860184273879032552 ret i64 %masked2553}2554 2555define i64 @bzhi64_constant_mask32(i64 %val) nounwind {2556; V7M-LABEL: bzhi64_constant_mask32:2557; V7M: @ %bb.0:2558; V7M-NEXT: bic r0, r0, #-21474836482559; V7M-NEXT: movs r1, #02560; V7M-NEXT: bx lr2561;2562; V7A-LABEL: bzhi64_constant_mask32:2563; V7A: @ %bb.0:2564; V7A-NEXT: bic r0, r0, #-21474836482565; V7A-NEXT: mov r1, #02566; V7A-NEXT: bx lr2567;2568; V7A-T-LABEL: bzhi64_constant_mask32:2569; V7A-T: @ %bb.0:2570; V7A-T-NEXT: bic r0, r0, #-21474836482571; V7A-T-NEXT: movs r1, #02572; V7A-T-NEXT: bx lr2573;2574; V6M-LABEL: bzhi64_constant_mask32:2575; V6M: @ %bb.0:2576; V6M-NEXT: movs r1, #12577; V6M-NEXT: lsls r1, r1, #312578; V6M-NEXT: bics r0, r12579; V6M-NEXT: movs r1, #02580; V6M-NEXT: bx lr2581 %masked = and i64 %val, 21474836472582 ret i64 %masked2583}2584 2585define i64 @bzhi64_constant_mask32_load(ptr %val) nounwind {2586; V7M-LABEL: bzhi64_constant_mask32_load:2587; V7M: @ %bb.0:2588; V7M-NEXT: ldr r0, [r0]2589; V7M-NEXT: movs r1, #02590; V7M-NEXT: bic r0, r0, #-21474836482591; V7M-NEXT: bx lr2592;2593; V7A-LABEL: bzhi64_constant_mask32_load:2594; V7A: @ %bb.0:2595; V7A-NEXT: ldr r0, [r0]2596; V7A-NEXT: mov r1, #02597; V7A-NEXT: bic r0, r0, #-21474836482598; V7A-NEXT: bx lr2599;2600; V7A-T-LABEL: bzhi64_constant_mask32_load:2601; V7A-T: @ %bb.0:2602; V7A-T-NEXT: ldr r0, [r0]2603; V7A-T-NEXT: movs r1, #02604; V7A-T-NEXT: bic r0, r0, #-21474836482605; V7A-T-NEXT: bx lr2606;2607; V6M-LABEL: bzhi64_constant_mask32_load:2608; V6M: @ %bb.0:2609; V6M-NEXT: movs r1, #12610; V6M-NEXT: lsls r1, r1, #312611; V6M-NEXT: ldr r0, [r0]2612; V6M-NEXT: bics r0, r12613; V6M-NEXT: movs r1, #02614; V6M-NEXT: bx lr2615 %val1 = load i64, ptr %val2616 %masked = and i64 %val1, 21474836472617 ret i64 %masked2618}2619 2620define i64 @bzhi64_constant_mask16(i64 %val) nounwind {2621; V7M-LABEL: bzhi64_constant_mask16:2622; V7M: @ %bb.0:2623; V7M-NEXT: bfc r0, #15, #172624; V7M-NEXT: movs r1, #02625; V7M-NEXT: bx lr2626;2627; V7A-LABEL: bzhi64_constant_mask16:2628; V7A: @ %bb.0:2629; V7A-NEXT: bfc r0, #15, #172630; V7A-NEXT: mov r1, #02631; V7A-NEXT: bx lr2632;2633; V7A-T-LABEL: bzhi64_constant_mask16:2634; V7A-T: @ %bb.0:2635; V7A-T-NEXT: bfc r0, #15, #172636; V7A-T-NEXT: movs r1, #02637; V7A-T-NEXT: bx lr2638;2639; V6M-LABEL: bzhi64_constant_mask16:2640; V6M: @ %bb.0:2641; V6M-NEXT: ldr r1, .LCPI49_02642; V6M-NEXT: ands r0, r12643; V6M-NEXT: movs r1, #02644; V6M-NEXT: bx lr2645; V6M-NEXT: .p2align 22646; V6M-NEXT: @ %bb.1:2647; V6M-NEXT: .LCPI49_0:2648; V6M-NEXT: .long 32767 @ 0x7fff2649 %masked = and i64 %val, 327672650 ret i64 %masked2651}2652 2653define i64 @bzhi64_constant_mask16_load(ptr %val) nounwind {2654; V7M-LABEL: bzhi64_constant_mask16_load:2655; V7M: @ %bb.0:2656; V7M-NEXT: ldr r0, [r0]2657; V7M-NEXT: movs r1, #02658; V7M-NEXT: bfc r0, #15, #172659; V7M-NEXT: bx lr2660;2661; V7A-LABEL: bzhi64_constant_mask16_load:2662; V7A: @ %bb.0:2663; V7A-NEXT: ldr r0, [r0]2664; V7A-NEXT: mov r1, #02665; V7A-NEXT: bfc r0, #15, #172666; V7A-NEXT: bx lr2667;2668; V7A-T-LABEL: bzhi64_constant_mask16_load:2669; V7A-T: @ %bb.0:2670; V7A-T-NEXT: ldr r0, [r0]2671; V7A-T-NEXT: movs r1, #02672; V7A-T-NEXT: bfc r0, #15, #172673; V7A-T-NEXT: bx lr2674;2675; V6M-LABEL: bzhi64_constant_mask16_load:2676; V6M: @ %bb.0:2677; V6M-NEXT: ldr r1, [r0]2678; V6M-NEXT: ldr r0, .LCPI50_02679; V6M-NEXT: ands r0, r12680; V6M-NEXT: movs r1, #02681; V6M-NEXT: bx lr2682; V6M-NEXT: .p2align 22683; V6M-NEXT: @ %bb.1:2684; V6M-NEXT: .LCPI50_0:2685; V6M-NEXT: .long 32767 @ 0x7fff2686 %val1 = load i64, ptr %val2687 %masked = and i64 %val1, 327672688 ret i64 %masked2689}2690 2691define i64 @bzhi64_constant_mask8(i64 %val) nounwind {2692; V7M-LABEL: bzhi64_constant_mask8:2693; V7M: @ %bb.0:2694; V7M-NEXT: and r0, r0, #1272695; V7M-NEXT: movs r1, #02696; V7M-NEXT: bx lr2697;2698; V7A-LABEL: bzhi64_constant_mask8:2699; V7A: @ %bb.0:2700; V7A-NEXT: and r0, r0, #1272701; V7A-NEXT: mov r1, #02702; V7A-NEXT: bx lr2703;2704; V7A-T-LABEL: bzhi64_constant_mask8:2705; V7A-T: @ %bb.0:2706; V7A-T-NEXT: and r0, r0, #1272707; V7A-T-NEXT: movs r1, #02708; V7A-T-NEXT: bx lr2709;2710; V6M-LABEL: bzhi64_constant_mask8:2711; V6M: @ %bb.0:2712; V6M-NEXT: movs r1, #1272713; V6M-NEXT: ands r0, r12714; V6M-NEXT: movs r1, #02715; V6M-NEXT: bx lr2716 %masked = and i64 %val, 1272717 ret i64 %masked2718}2719 2720define i64 @bzhi64_constant_mask8_load(ptr %val) nounwind {2721; V7M-LABEL: bzhi64_constant_mask8_load:2722; V7M: @ %bb.0:2723; V7M-NEXT: ldr r0, [r0]2724; V7M-NEXT: movs r1, #02725; V7M-NEXT: and r0, r0, #1272726; V7M-NEXT: bx lr2727;2728; V7A-LABEL: bzhi64_constant_mask8_load:2729; V7A: @ %bb.0:2730; V7A-NEXT: ldr r0, [r0]2731; V7A-NEXT: mov r1, #02732; V7A-NEXT: and r0, r0, #1272733; V7A-NEXT: bx lr2734;2735; V7A-T-LABEL: bzhi64_constant_mask8_load:2736; V7A-T: @ %bb.0:2737; V7A-T-NEXT: ldr r0, [r0]2738; V7A-T-NEXT: movs r1, #02739; V7A-T-NEXT: and r0, r0, #1272740; V7A-T-NEXT: bx lr2741;2742; V6M-LABEL: bzhi64_constant_mask8_load:2743; V6M: @ %bb.0:2744; V6M-NEXT: ldr r1, [r0]2745; V6M-NEXT: movs r0, #1272746; V6M-NEXT: ands r0, r12747; V6M-NEXT: movs r1, #02748; V6M-NEXT: bx lr2749 %val1 = load i64, ptr %val2750 %masked = and i64 %val1, 1272751 ret i64 %masked2752}2753