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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-- -mattr=+mve.fp < %s | FileCheck %s3 4define float @fadd_select_fneg_fneg_f32(i32 %arg0, float %x, float %y, float %z) {5; CHECK-LABEL: fadd_select_fneg_fneg_f32:6; CHECK: @ %bb.0:7; CHECK-NEXT: vmov s0, r28; CHECK-NEXT: cmp r0, #09; CHECK-NEXT: vmov s4, r110; CHECK-NEXT: vmov s2, r311; CHECK-NEXT: vseleq.f32 s0, s4, s012; CHECK-NEXT: vsub.f32 s0, s2, s013; CHECK-NEXT: vmov r0, s014; CHECK-NEXT: bx lr15 %cmp = icmp eq i32 %arg0, 016 %neg.x = fneg float %x17 %neg.y = fneg float %y18 %select = select i1 %cmp, float %neg.x, float %neg.y19 %add = fadd float %select, %z20 ret float %add21}22 23define half @fadd_select_fneg_fneg_f16(i32 %arg0, half %x, half %y, half %z) {24; CHECK-LABEL: fadd_select_fneg_fneg_f16:25; CHECK: @ %bb.0:26; CHECK-NEXT: vmov.f16 s0, r227; CHECK-NEXT: cmp r0, #028; CHECK-NEXT: vmov.f16 s2, r129; CHECK-NEXT: vseleq.f16 s0, s2, s030; CHECK-NEXT: vmov.f16 s2, r331; CHECK-NEXT: vsub.f16 s0, s2, s032; CHECK-NEXT: vmov r0, s033; CHECK-NEXT: bx lr34 %cmp = icmp eq i32 %arg0, 035 %neg.x = fneg half %x36 %neg.y = fneg half %y37 %select = select i1 %cmp, half %neg.x, half %neg.y38 %add = fadd half %select, %z39 ret half %add40}41 42define <2 x float> @fadd_select_fneg_fneg_v2f32(i32 %arg0, <2 x float> %x, <2 x float> %y, <2 x float> %z) {43; CHECK-LABEL: fadd_select_fneg_fneg_v2f32:44; CHECK: @ %bb.0:45; CHECK-NEXT: add r1, sp, #2446; CHECK-NEXT: cmp r0, #047; CHECK-NEXT: vldrw.u32 q0, [r1]48; CHECK-NEXT: beq .LBB2_249; CHECK-NEXT: @ %bb.1: @ %select.false50; CHECK-NEXT: add r0, sp, #851; CHECK-NEXT: vldrw.u32 q1, [r0]52; CHECK-NEXT: b .LBB2_353; CHECK-NEXT: .LBB2_2:54; CHECK-NEXT: vmov d2, r2, r355; CHECK-NEXT: .LBB2_3: @ %select.end56; CHECK-NEXT: vneg.f32 q1, q157; CHECK-NEXT: vadd.f32 q0, q1, q058; CHECK-NEXT: vmov r0, r1, d059; CHECK-NEXT: vmov r2, r3, d160; CHECK-NEXT: bx lr61 %cmp = icmp eq i32 %arg0, 062 %neg.x = fneg <2 x float> %x63 %neg.y = fneg <2 x float> %y64 %select = select i1 %cmp, <2 x float> %neg.x, <2 x float> %neg.y65 %add = fadd <2 x float> %select, %z66 ret <2 x float> %add67}68 69define <2 x half> @fadd_select_fneg_fneg_v2f16(i32 %arg0, <2 x half> %x, <2 x half> %y, <2 x half> %z) {70; CHECK-LABEL: fadd_select_fneg_fneg_v2f16:71; CHECK: @ %bb.0:72; CHECK-NEXT: add r1, sp, #2473; CHECK-NEXT: cmp r0, #074; CHECK-NEXT: vldrw.u32 q0, [r1]75; CHECK-NEXT: beq .LBB3_276; CHECK-NEXT: @ %bb.1: @ %select.false77; CHECK-NEXT: add r0, sp, #878; CHECK-NEXT: vldrw.u32 q1, [r0]79; CHECK-NEXT: b .LBB3_380; CHECK-NEXT: .LBB3_2:81; CHECK-NEXT: vmov d2, r2, r382; CHECK-NEXT: .LBB3_3: @ %select.end83; CHECK-NEXT: vneg.f16 q1, q184; CHECK-NEXT: vadd.f16 q0, q1, q085; CHECK-NEXT: vmov r0, r1, d086; CHECK-NEXT: vmov r2, r3, d187; CHECK-NEXT: bx lr88 %cmp = icmp eq i32 %arg0, 089 %neg.x = fneg <2 x half> %x90 %neg.y = fneg <2 x half> %y91 %select = select i1 %cmp, <2 x half> %neg.x, <2 x half> %neg.y92 %add = fadd <2 x half> %select, %z93 ret <2 x half> %add94}95 96define float @fadd_select_fsub_fsub_f32(i32 %arg0, float %x, float %y, float %z) {97; CHECK-LABEL: fadd_select_fsub_fsub_f32:98; CHECK: @ %bb.0:99; CHECK-NEXT: vmov.f32 s0, #2.000000e+00100; CHECK-NEXT: cmp r0, #0101; CHECK-NEXT: vmov s4, r2102; CHECK-NEXT: vmov s2, r1103; CHECK-NEXT: vmov s6, r3104; CHECK-NEXT: vsub.f32 s4, s4, s0105; CHECK-NEXT: vsub.f32 s0, s2, s0106; CHECK-NEXT: vseleq.f32 s0, s0, s4107; CHECK-NEXT: vadd.f32 s0, s0, s6108; CHECK-NEXT: vmov r0, s0109; CHECK-NEXT: bx lr110 %cmp = icmp eq i32 %arg0, 0111 %neg.x = fsub nsz float %x, 2.0112 %neg.y = fsub nsz float %y, 2.0113 %select = select i1 %cmp, float %neg.x, float %neg.y114 %add = fadd float %select, %z115 ret float %add116}117 118define float @fneg_select_fmul_fmul_f32(i32 %arg0, float %x, float %y) {119; CHECK-LABEL: fneg_select_fmul_fmul_f32:120; CHECK: @ %bb.0:121; CHECK-NEXT: vmov.f32 s0, #4.000000e+00122; CHECK-NEXT: cmp r0, #0123; CHECK-NEXT: vmov.f32 s2, #8.000000e+00124; CHECK-NEXT: vmov s4, r2125; CHECK-NEXT: vmov s6, r1126; CHECK-NEXT: vmul.f32 s0, s4, s0127; CHECK-NEXT: vmul.f32 s2, s6, s2128; CHECK-NEXT: vseleq.f32 s0, s2, s0129; CHECK-NEXT: vmov r0, s0130; CHECK-NEXT: eor r0, r0, #-2147483648131; CHECK-NEXT: bx lr132 %cmp = icmp eq i32 %arg0, 0133 %neg.x = fmul float %x, 8.0134 %neg.y = fmul float %y, 4.0135 %select = select i1 %cmp, float %neg.x, float %neg.y136 %neg = fneg float %select137 ret float %neg138}139 140define half @fadd_select_fsub_fsub_f16(i32 %arg0, half %x, half %y, half %z) {141; CHECK-LABEL: fadd_select_fsub_fsub_f16:142; CHECK: @ %bb.0:143; CHECK-NEXT: vmov.f16 s0, r2144; CHECK-NEXT: vmov.f16 s2, #2.000000e+00145; CHECK-NEXT: vmov.f16 s4, r1146; CHECK-NEXT: vsub.f16 s0, s0, s2147; CHECK-NEXT: vsub.f16 s2, s4, s2148; CHECK-NEXT: cmp r0, #0149; CHECK-NEXT: vseleq.f16 s0, s2, s0150; CHECK-NEXT: vmov.f16 s2, r3151; CHECK-NEXT: vadd.f16 s0, s0, s2152; CHECK-NEXT: vmov r0, s0153; CHECK-NEXT: bx lr154 %cmp = icmp eq i32 %arg0, 0155 %sub.x = fsub nsz half %x, 2.0156 %sub.y = fsub nsz half %y, 2.0157 %select = select i1 %cmp, half %sub.x, half %sub.y158 %add = fadd half %select, %z159 ret half %add160}161 162define half @fneg_select_fmul_fmul_f16(i32 %arg0, half %x, half %y) {163; CHECK-LABEL: fneg_select_fmul_fmul_f16:164; CHECK: @ %bb.0:165; CHECK-NEXT: vmov.f16 s0, r2166; CHECK-NEXT: vmov.f16 s2, #4.000000e+00167; CHECK-NEXT: vmul.f16 s0, s0, s2168; CHECK-NEXT: vmov.f16 s2, r1169; CHECK-NEXT: vmov.f16 s4, #8.000000e+00170; CHECK-NEXT: cmp r0, #0171; CHECK-NEXT: vmul.f16 s2, s2, s4172; CHECK-NEXT: vseleq.f16 s0, s2, s0173; CHECK-NEXT: vneg.f16 s0, s0174; CHECK-NEXT: vmov r0, s0175; CHECK-NEXT: bx lr176 %cmp = icmp eq i32 %arg0, 0177 %mul.x = fmul half %x, 8.0178 %mul.y = fmul half %y, 4.0179 %select = select i1 %cmp, half %mul.x, half %mul.y180 %neg = fneg half %select181 ret half %neg182}183 184define half @fadd_select_fsub_arg_f16(i32 %arg0, half %x, half %y, half %z) {185; CHECK-LABEL: fadd_select_fsub_arg_f16:186; CHECK: @ %bb.0:187; CHECK-NEXT: vmov.f16 s0, r1188; CHECK-NEXT: vmov.f16 s2, #-2.000000e+00189; CHECK-NEXT: vadd.f16 s0, s0, s2190; CHECK-NEXT: vmov.f16 s2, r2191; CHECK-NEXT: cmp r0, #0192; CHECK-NEXT: vseleq.f16 s0, s0, s2193; CHECK-NEXT: vmov.f16 s2, r3194; CHECK-NEXT: vadd.f16 s0, s0, s2195; CHECK-NEXT: vmov r0, s0196; CHECK-NEXT: bx lr197 %cmp = icmp eq i32 %arg0, 0198 %sub.x = fsub nsz half %x, 2.0199 %select = select i1 %cmp, half %sub.x, half %y200 %add = fadd half %select, %z201 ret half %add202}203 204define half @fadd_select_arg_fsub_f16(i32 %arg0, half %x, half %y, half %z) {205; CHECK-LABEL: fadd_select_arg_fsub_f16:206; CHECK: @ %bb.0:207; CHECK-NEXT: vmov.f16 s0, r2208; CHECK-NEXT: vmov.f16 s2, #-2.000000e+00209; CHECK-NEXT: vadd.f16 s0, s0, s2210; CHECK-NEXT: vmov.f16 s2, r1211; CHECK-NEXT: cmp r0, #0212; CHECK-NEXT: vseleq.f16 s0, s2, s0213; CHECK-NEXT: vmov.f16 s2, r3214; CHECK-NEXT: vadd.f16 s0, s0, s2215; CHECK-NEXT: vmov r0, s0216; CHECK-NEXT: bx lr217 %cmp = icmp eq i32 %arg0, 0218 %sub.y = fsub nsz half %y, 2.0219 %select = select i1 %cmp, half %x, half %sub.y220 %add = fadd half %select, %z221 ret half %add222}223 224define half @fadd_select_fsub_select_f16(i32 %arg0, half %x, half %y, half %z) {225; CHECK-LABEL: fadd_select_fsub_select_f16:226; CHECK: @ %bb.0:227; CHECK-NEXT: vmov.f16 s0, r1228; CHECK-NEXT: vmov.f16 s2, #2.000000e+00229; CHECK-NEXT: vsub.f16 s0, s0, s2230; CHECK-NEXT: vmov.f16 s4, r2231; CHECK-NEXT: cmp r0, #0232; CHECK-NEXT: vsub.f16 s2, s4, s2233; CHECK-NEXT: vseleq.f16 s0, s0, s4234; CHECK-NEXT: vseleq.f16 s0, s2, s0235; CHECK-NEXT: vmov.f16 s2, r3236; CHECK-NEXT: vadd.f16 s0, s0, s2237; CHECK-NEXT: vmov r0, s0238; CHECK-NEXT: bx lr239 %cmp = icmp eq i32 %arg0, 0240 %sub.x = fsub nsz half %x, 2.0241 %sub.y = fsub nsz half %y, 2.0242 %select0 = select i1 %cmp, half %sub.x, half %y243 %select1 = select i1 %cmp, half %sub.y, half %select0244 %add = fadd half %select1, %z245 ret half %add246}247 248define half @fadd_select_fneg_negk_f16(i32 %arg0, half %x, half %y) {249; CHECK-LABEL: fadd_select_fneg_negk_f16:250; CHECK: @ %bb.0:251; CHECK-NEXT: vmov.f16 s0, #4.000000e+00252; CHECK-NEXT: vmov.f16 s2, r1253; CHECK-NEXT: cmp r0, #0254; CHECK-NEXT: vseleq.f16 s0, s2, s0255; CHECK-NEXT: vmov.f16 s2, r2256; CHECK-NEXT: vsub.f16 s0, s2, s0257; CHECK-NEXT: vmov r0, s0258; CHECK-NEXT: bx lr259 %cmp = icmp eq i32 %arg0, 0260 %neg.x = fneg half %x261 %select = select i1 %cmp, half %neg.x, half -4.0262 %add = fadd half %select, %y263 ret half %add264}265 266define half @fadd_select_fneg_posk_f16(i32 %arg0, half %x, half %y) {267; CHECK-LABEL: fadd_select_fneg_posk_f16:268; CHECK: @ %bb.0:269; CHECK-NEXT: vmov.f16 s0, #-4.000000e+00270; CHECK-NEXT: vmov.f16 s2, r1271; CHECK-NEXT: cmp r0, #0272; CHECK-NEXT: vseleq.f16 s0, s2, s0273; CHECK-NEXT: vmov.f16 s2, r2274; CHECK-NEXT: vsub.f16 s0, s2, s0275; CHECK-NEXT: vmov r0, s0276; CHECK-NEXT: bx lr277 %cmp = icmp eq i32 %arg0, 0278 %neg.x = fneg half %x279 %select = select i1 %cmp, half %neg.x, half 4.0280 %add = fadd half %select, %y281 ret half %add282}283 284define <8 x half> @fadd_vselect_fneg_posk_v8f16(<8 x i32> %arg0, <8 x half> %x, <8 x half> %y) {285; CHECK-LABEL: fadd_vselect_fneg_posk_v8f16:286; CHECK: @ %bb.0:287; CHECK-NEXT: sub sp, sp, #16288; CHECK-NEXT: vmov d0, r0, r1289; CHECK-NEXT: add r0, sp, #16290; CHECK-NEXT: vmov d1, r2, r3291; CHECK-NEXT: vldrw.u32 q3, [r0]292; CHECK-NEXT: vcmp.i32 eq, q0, zr293; CHECK-NEXT: vmov.i8 q0, #0x0294; CHECK-NEXT: vmov.i8 q1, #0xff295; CHECK-NEXT: mov r0, sp296; CHECK-NEXT: vpsel q2, q1, q0297; CHECK-NEXT: vcmp.i32 eq, q3, zr298; CHECK-NEXT: vpsel q0, q1, q0299; CHECK-NEXT: vstrh.32 q2, [r0]300; CHECK-NEXT: vstrh.32 q0, [r0, #8]301; CHECK-NEXT: add r1, sp, #32302; CHECK-NEXT: vldrw.u32 q2, [r0]303; CHECK-NEXT: vldrw.u32 q0, [r1]304; CHECK-NEXT: vmov.i16 q1, #0xc400305; CHECK-NEXT: add r0, sp, #48306; CHECK-NEXT: vcmp.i16 ne, q2, zr307; CHECK-NEXT: vpsel q0, q0, q1308; CHECK-NEXT: vldrw.u32 q1, [r0]309; CHECK-NEXT: vsub.f16 q0, q1, q0310; CHECK-NEXT: vmov r0, r1, d0311; CHECK-NEXT: vmov r2, r3, d1312; CHECK-NEXT: add sp, sp, #16313; CHECK-NEXT: bx lr314 %cmp = icmp eq <8 x i32> %arg0, zeroinitializer315 %neg.x = fneg <8 x half> %x316 %select = select <8 x i1> %cmp, <8 x half> %neg.x, <8 x half> <half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0, half 4.0>317 %add = fadd <8 x half> %select, %y318 ret <8 x half> %add319}320