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1; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM2; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM3; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB4 5; Test add with non-legal types6 7define void @add_i1(i1 %a, i1 %b) nounwind ssp {8entry:9; ARM: add_i110; THUMB: add_i111 %a.addr = alloca i1, align 412 %0 = add i1 %a, %b13; ARM: add r0, r0, r114; THUMB: add r0, r115 store i1 %0, ptr %a.addr, align 416 ret void17}18 19define void @add_i8(i8 %a, i8 %b) nounwind ssp {20entry:21; ARM: add_i822; THUMB: add_i823 %a.addr = alloca i8, align 424 %0 = add i8 %a, %b25; ARM: add r0, r0, r126; THUMB: add r0, r127 store i8 %0, ptr %a.addr, align 428 ret void29}30 31define void @add_i16(i16 %a, i16 %b) nounwind ssp {32entry:33; ARM: add_i1634; THUMB: add_i1635 %a.addr = alloca i16, align 436 %0 = add i16 %a, %b37; ARM: add r0, r0, r138; THUMB: add r0, r139 store i16 %0, ptr %a.addr, align 440 ret void41}42 43; Test or with non-legal types44 45define void @or_i1(i1 %a, i1 %b) nounwind ssp {46entry:47; ARM: or_i148; THUMB: or_i149 %a.addr = alloca i1, align 450 %0 = or i1 %a, %b51; ARM: orr r0, r0, r152; THUMB: orrs r0, r153 store i1 %0, ptr %a.addr, align 454 ret void55}56 57define void @or_i8(i8 %a, i8 %b) nounwind ssp {58entry:59; ARM: or_i860; THUMB: or_i861 %a.addr = alloca i8, align 462 %0 = or i8 %a, %b63; ARM: orr r0, r0, r164; THUMB: orrs r0, r165 store i8 %0, ptr %a.addr, align 466 ret void67}68 69define void @or_i16(i16 %a, i16 %b) nounwind ssp {70entry:71; ARM: or_i1672; THUMB: or_i1673 %a.addr = alloca i16, align 474 %0 = or i16 %a, %b75; ARM: orr r0, r0, r176; THUMB: orrs r0, r177 store i16 %0, ptr %a.addr, align 478 ret void79}80 81; Test sub with non-legal types82 83define void @sub_i1(i1 %a, i1 %b) nounwind ssp {84entry:85; ARM: sub_i186; THUMB: sub_i187 %a.addr = alloca i1, align 488 %0 = sub i1 %a, %b89; ARM: sub r0, r0, r190; THUMB: subs r0, r0, r191 store i1 %0, ptr %a.addr, align 492 ret void93}94 95define void @sub_i8(i8 %a, i8 %b) nounwind ssp {96entry:97; ARM: sub_i898; THUMB: sub_i899 %a.addr = alloca i8, align 4100 %0 = sub i8 %a, %b101; ARM: sub r0, r0, r1102; THUMB: subs r0, r0, r1103 store i8 %0, ptr %a.addr, align 4104 ret void105}106 107define void @sub_i16(i16 %a, i16 %b) nounwind ssp {108entry:109; ARM: sub_i16110; THUMB: sub_i16111 %a.addr = alloca i16, align 4112 %0 = sub i16 %a, %b113; ARM: sub r0, r0, r1114; THUMB: subs r0, r0, r1115 store i16 %0, ptr %a.addr, align 4116 ret void117}118