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1; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM2; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM3; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB4 5; Test sitofp6 7define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {8entry:9; ARM: sitofp_single_i3210; ARM: vmov s0, r011; ARM: vcvt.f32.s32 s0, s012; THUMB: sitofp_single_i3213; THUMB: vmov s0, r014; THUMB: vcvt.f32.s32 s0, s015 %b.addr = alloca float, align 416 %conv = sitofp i32 %a to float17 store float %conv, ptr %b.addr, align 418 ret void19}20 21define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {22entry:23; ARM: sitofp_single_i1624; ARM: sxth r0, r025; ARM: vmov s0, r026; ARM: vcvt.f32.s32 s0, s027; THUMB: sitofp_single_i1628; THUMB: sxth r0, r029; THUMB: vmov s0, r030; THUMB: vcvt.f32.s32 s0, s031 %b.addr = alloca float, align 432 %conv = sitofp i16 %a to float33 store float %conv, ptr %b.addr, align 434 ret void35}36 37define void @sitofp_single_i8(i8 %a) nounwind ssp {38entry:39; ARM: sitofp_single_i840; ARM: sxtb r0, r041; ARM: vmov s0, r042; ARM: vcvt.f32.s32 s0, s043; THUMB: sitofp_single_i844; THUMB: sxtb r0, r045; THUMB: vmov s0, r046; THUMB: vcvt.f32.s32 s0, s047 %b.addr = alloca float, align 448 %conv = sitofp i8 %a to float49 store float %conv, ptr %b.addr, align 450 ret void51}52 53define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {54entry:55; ARM: sitofp_double_i3256; ARM: vmov s0, r057; ARM: vcvt.f64.s32 d16, s058; THUMB: sitofp_double_i3259; THUMB: vmov s0, r060; THUMB: vcvt.f64.s32 d16, s061 %b.addr = alloca double, align 862 %conv = sitofp i32 %a to double63 store double %conv, ptr %b.addr, align 864 ret void65}66 67define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {68entry:69; ARM: sitofp_double_i1670; ARM: sxth r0, r071; ARM: vmov s0, r072; ARM: vcvt.f64.s32 d16, s073; THUMB: sitofp_double_i1674; THUMB: sxth r0, r075; THUMB: vmov s0, r076; THUMB: vcvt.f64.s32 d16, s077 %b.addr = alloca double, align 878 %conv = sitofp i16 %a to double79 store double %conv, ptr %b.addr, align 880 ret void81}82 83define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {84entry:85; ARM: sitofp_double_i886; ARM: sxtb r0, r087; ARM: vmov s0, r088; ARM: vcvt.f64.s32 d16, s089; THUMB: sitofp_double_i890; THUMB: sxtb r0, r091; THUMB: vmov s0, r092; THUMB: vcvt.f64.s32 d16, s093 %b.addr = alloca double, align 894 %conv = sitofp i8 %a to double95 store double %conv, ptr %b.addr, align 896 ret void97}98 99; Test uitofp100 101define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {102entry:103; ARM: uitofp_single_i32104; ARM: vmov s0, r0105; ARM: vcvt.f32.u32 s0, s0106; THUMB: uitofp_single_i32107; THUMB: vmov s0, r0108; THUMB: vcvt.f32.u32 s0, s0109 %b.addr = alloca float, align 4110 %conv = uitofp i32 %a to float111 store float %conv, ptr %b.addr, align 4112 ret void113}114 115define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {116entry:117; ARM: uitofp_single_i16118; ARM: uxth r0, r0119; ARM: vmov s0, r0120; ARM: vcvt.f32.u32 s0, s0121; THUMB: uitofp_single_i16122; THUMB: uxth r0, r0123; THUMB: vmov s0, r0124; THUMB: vcvt.f32.u32 s0, s0125 %b.addr = alloca float, align 4126 %conv = uitofp i16 %a to float127 store float %conv, ptr %b.addr, align 4128 ret void129}130 131define void @uitofp_single_i8(i8 %a) nounwind ssp {132entry:133; ARM: uitofp_single_i8134; ARM: and r0, r0, #255135; ARM: vmov s0, r0136; ARM: vcvt.f32.u32 s0, s0137; THUMB: uitofp_single_i8138; THUMB: and r0, r0, #255139; THUMB: vmov s0, r0140; THUMB: vcvt.f32.u32 s0, s0141 %b.addr = alloca float, align 4142 %conv = uitofp i8 %a to float143 store float %conv, ptr %b.addr, align 4144 ret void145}146 147define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {148entry:149; ARM: uitofp_double_i32150; ARM: vmov s0, r0151; ARM: vcvt.f64.u32 d16, s0152; THUMB: uitofp_double_i32153; THUMB: vmov s0, r0154; THUMB: vcvt.f64.u32 d16, s0155 %b.addr = alloca double, align 8156 %conv = uitofp i32 %a to double157 store double %conv, ptr %b.addr, align 8158 ret void159}160 161define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {162entry:163; ARM: uitofp_double_i16164; ARM: uxth r0, r0165; ARM: vmov s0, r0166; ARM: vcvt.f64.u32 d16, s0167; THUMB: uitofp_double_i16168; THUMB: uxth r0, r0169; THUMB: vmov s0, r0170; THUMB: vcvt.f64.u32 d16, s0171 %b.addr = alloca double, align 8172 %conv = uitofp i16 %a to double173 store double %conv, ptr %b.addr, align 8174 ret void175}176 177define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {178entry:179; ARM: uitofp_double_i8180; ARM: and r0, r0, #255181; ARM: vmov s0, r0182; ARM: vcvt.f64.u32 d16, s0183; THUMB: uitofp_double_i8184; THUMB: and r0, r0, #255185; THUMB: vmov s0, r0186; THUMB: vcvt.f64.u32 d16, s0187 %b.addr = alloca double, align 8188 %conv = uitofp i8 %a to double189 store double %conv, ptr %b.addr, align 8190 ret void191}192 193; Test fptosi194 195define void @fptosi_float(float %a) nounwind ssp {196entry:197; ARM: fptosi_float198; ARM: vcvt.s32.f32 s0, s0199; THUMB: fptosi_float200; THUMB: vcvt.s32.f32 s0, s0201 %b.addr = alloca i32, align 4202 %conv = fptosi float %a to i32203 store i32 %conv, ptr %b.addr, align 4204 ret void205}206 207define void @fptosi_double(double %a) nounwind ssp {208entry:209; ARM: fptosi_double210; ARM: vcvt.s32.f64 s0, d16211; THUMB: fptosi_double212; THUMB: vcvt.s32.f64 s0, d16213 %b.addr = alloca i32, align 8214 %conv = fptosi double %a to i32215 store i32 %conv, ptr %b.addr, align 8216 ret void217}218 219; Test fptoui220 221define void @fptoui_float(float %a) nounwind ssp {222entry:223; ARM: fptoui_float224; ARM: vcvt.u32.f32 s0, s0225; THUMB: fptoui_float226; THUMB: vcvt.u32.f32 s0, s0227 %b.addr = alloca i32, align 4228 %conv = fptoui float %a to i32229 store i32 %conv, ptr %b.addr, align 4230 ret void231}232 233define void @fptoui_double(double %a) nounwind ssp {234entry:235; ARM: fptoui_double236; ARM: vcvt.u32.f64 s0, d16237; THUMB: fptoui_double238; THUMB: vcvt.u32.f64 s0, d16239 %b.addr = alloca i32, align 8240 %conv = fptoui double %a to i32241 store i32 %conv, ptr %b.addr, align 8242 ret void243}244