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1; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v72; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v73; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v74 5; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports6; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always7; using two shifts.8 9; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions10; and therefore must set flags. {{s?}} below denotes this, instead of11; duplicating tests.12 13; zext14 15define i8 @zext_1_8(i1 %a) nounwind ssp {16; v7-LABEL: zext_1_8:17; v7: and r0, r0, #118 %r = zext i1 %a to i819 ret i8 %r20}21 22define i16 @zext_1_16(i1 %a) nounwind ssp {23; v7-LABEL: zext_1_16:24; v7: and r0, r0, #125 %r = zext i1 %a to i1626 ret i16 %r27}28 29define i32 @zext_1_32(i1 %a) nounwind ssp {30; v7-LABEL: zext_1_32:31; v7: and r0, r0, #132 %r = zext i1 %a to i3233 ret i32 %r34}35 36define i16 @zext_8_16(i8 %a) nounwind ssp {37; v7-LABEL: zext_8_16:38; v7: and r0, r0, #25539 %r = zext i8 %a to i1640 ret i16 %r41}42 43define i32 @zext_8_32(i8 %a) nounwind ssp {44; v7-LABEL: zext_8_32:45; v7: and r0, r0, #25546 %r = zext i8 %a to i3247 ret i32 %r48}49 50define i32 @zext_16_32(i16 %a) nounwind ssp {51; v7-LABEL: zext_16_32:52; v7: uxth r0, r053 %r = zext i16 %a to i3254 ret i32 %r55}56 57; sext58 59define i8 @sext_1_8(i1 %a) nounwind ssp {60; v7-LABEL: sext_1_8:61; v7: lsl{{s?}} r0, r0, #3162; v7: asr{{s?}} r0, r0, #3163 %r = sext i1 %a to i864 ret i8 %r65}66 67define i16 @sext_1_16(i1 %a) nounwind ssp {68; v7-LABEL: sext_1_16:69; v7: lsl{{s?}} r0, r0, #3170; v7: asr{{s?}} r0, r0, #3171 %r = sext i1 %a to i1672 ret i16 %r73}74 75define i32 @sext_1_32(i1 %a) nounwind ssp {76; v7-LABEL: sext_1_32:77; v7: lsl{{s?}} r0, r0, #3178; v7: asr{{s?}} r0, r0, #3179 %r = sext i1 %a to i3280 ret i32 %r81}82 83define i16 @sext_8_16(i8 %a) nounwind ssp {84; v7-LABEL: sext_8_16:85; v7: sxtb r0, r086 %r = sext i8 %a to i1687 ret i16 %r88}89 90define i32 @sext_8_32(i8 %a) nounwind ssp {91; v7-LABEL: sext_8_32:92; v7: sxtb r0, r093 %r = sext i8 %a to i3294 ret i32 %r95}96 97define i32 @sext_16_32(i16 %a) nounwind ssp {98; v7-LABEL: sext_16_32:99; v7: sxth r0, r0100 %r = sext i16 %a to i32101 ret i32 %r102}103