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1; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM2; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM3; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB4 5define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind {6entry:7; ARM: icmp_i16_signed8; ARM: sxth r0, r09; ARM: sxth r1, r110; ARM: cmp r0, r111; THUMB: icmp_i16_signed12; THUMB: sxth r0, r013; THUMB: sxth r1, r114; THUMB: cmp r0, r115 %cmp = icmp slt i16 %a, %b16 %conv2 = zext i1 %cmp to i3217 ret i32 %conv218}19 20define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind {21entry:22; ARM: icmp_i16_unsigned23; ARM: uxth r0, r024; ARM: uxth r1, r125; ARM: cmp r0, r126; THUMB: icmp_i16_unsigned27; THUMB: uxth r0, r028; THUMB: uxth r1, r129; THUMB: cmp r0, r130 %cmp = icmp ult i16 %a, %b31 %conv2 = zext i1 %cmp to i3232 ret i32 %conv233}34 35define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind {36entry:37; ARM: icmp_i8_signed38; ARM: sxtb r0, r039; ARM: sxtb r1, r140; ARM: cmp r0, r141; THUMB: icmp_i8_signed42; THUMB: sxtb r0, r043; THUMB: sxtb r1, r144; THUMB: cmp r0, r145 %cmp = icmp sgt i8 %a, %b46 %conv2 = zext i1 %cmp to i3247 ret i32 %conv248}49 50define i32 @icmp_i8_unsigned(i8 %a, i8 %b) nounwind {51entry:52; ARM: icmp_i8_unsigned53; ARM: and r0, r0, #25554; ARM: and r1, r1, #25555; ARM: cmp r0, r156; THUMB: icmp_i8_unsigned57; THUMB: and r0, r0, #25558; THUMB: and r1, r1, #25559; THUMB: cmp r0, r160 %cmp = icmp ugt i8 %a, %b61 %conv2 = zext i1 %cmp to i3262 ret i32 %conv263}64 65define i32 @icmp_i1_unsigned(i1 %a, i1 %b) nounwind {66entry:67; ARM: icmp_i1_unsigned68; ARM: and r0, r0, #169; ARM: and r1, r1, #170; ARM: cmp r0, r171; THUMB: icmp_i1_unsigned72; THUMB: and r0, r0, #173; THUMB: and r1, r1, #174; THUMB: cmp r0, r175 %cmp = icmp ult i1 %a, %b76 %conv2 = zext i1 %cmp to i3277 ret i32 %conv278}79