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1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM3; rdar://104180094 5define zeroext i16 @t1(ptr nocapture %a) nounwind uwtable readonly ssp {6entry:7; ARM-LABEL: t1:8 %add.ptr = getelementptr inbounds i16, ptr %a, i64 -89 %0 = load i16, ptr %add.ptr, align 210; ARM: ldrh r0, [r0, #-16]11 ret i16 %012}13 14define zeroext i16 @t2(ptr nocapture %a) nounwind uwtable readonly ssp {15entry:16; ARM-LABEL: t2:17 %add.ptr = getelementptr inbounds i16, ptr %a, i64 -1618 %0 = load i16, ptr %add.ptr, align 219; ARM: ldrh r0, [r0, #-32]20 ret i16 %021}22 23define zeroext i16 @t3(ptr nocapture %a) nounwind uwtable readonly ssp {24entry:25; ARM-LABEL: t3:26 %add.ptr = getelementptr inbounds i16, ptr %a, i64 -12727 %0 = load i16, ptr %add.ptr, align 228; ARM: ldrh r0, [r0, #-254]29 ret i16 %030}31 32define zeroext i16 @t4(ptr nocapture %a) nounwind uwtable readonly ssp {33entry:34; ARM-LABEL: t4:35 %add.ptr = getelementptr inbounds i16, ptr %a, i64 -12836 %0 = load i16, ptr %add.ptr, align 237; ARM: mvn r{{[1-9]}}, #25538; ARM: add r0, r0, r{{[1-9]}}39; ARM: ldrh r0, [r0]40 ret i16 %041}42 43define zeroext i16 @t5(ptr nocapture %a) nounwind uwtable readonly ssp {44entry:45; ARM-LABEL: t5:46 %add.ptr = getelementptr inbounds i16, ptr %a, i64 847 %0 = load i16, ptr %add.ptr, align 248; ARM: ldrh r0, [r0, #16]49 ret i16 %050}51 52define zeroext i16 @t6(ptr nocapture %a) nounwind uwtable readonly ssp {53entry:54; ARM-LABEL: t6:55 %add.ptr = getelementptr inbounds i16, ptr %a, i64 1656 %0 = load i16, ptr %add.ptr, align 257; ARM: ldrh r0, [r0, #32]58 ret i16 %059}60 61define zeroext i16 @t7(ptr nocapture %a) nounwind uwtable readonly ssp {62entry:63; ARM-LABEL: t7:64 %add.ptr = getelementptr inbounds i16, ptr %a, i64 12765 %0 = load i16, ptr %add.ptr, align 266; ARM: ldrh r0, [r0, #254]67 ret i16 %068}69 70define zeroext i16 @t8(ptr nocapture %a) nounwind uwtable readonly ssp {71entry:72; ARM-LABEL: t8:73 %add.ptr = getelementptr inbounds i16, ptr %a, i64 12874 %0 = load i16, ptr %add.ptr, align 275; ARM: add r0, r0, #25676; ARM: ldrh r0, [r0]77 ret i16 %078}79 80define void @t9(ptr nocapture %a) nounwind uwtable ssp {81entry:82; ARM-LABEL: t9:83 %add.ptr = getelementptr inbounds i16, ptr %a, i64 -884 store i16 0, ptr %add.ptr, align 285; ARM: movw [[REG0:r[0-9]+]], #086; ARM: strh [[REG0]], [{{r[0-9]+}}, #-16]87 ret void88}89 90; mvn r1, #25591; strh r2, [r0, r1]92define void @t10(ptr nocapture %a) nounwind uwtable ssp {93entry:94; ARM-LABEL: t10:95 %add.ptr = getelementptr inbounds i16, ptr %a, i64 -12896 store i16 0, ptr %add.ptr, align 297; ARM: mov r1, r098; ARM: movw [[REG1:r[0-9]+]], #099; ARM: mvn [[REG2:r[0-9]+]], #255100; ARM: add [[REG0:r[0-9]+]], r1, [[REG2]]101; ARM: strh [[REG1]], [[[REG0]]]102 ret void103}104 105define void @t11(ptr nocapture %a) nounwind uwtable ssp {106entry:107; ARM-LABEL: t11:108 %add.ptr = getelementptr inbounds i16, ptr %a, i64 8109 store i16 0, ptr %add.ptr, align 2110; ARM: movw [[REG1:r[0-9]+]], #0111; ARM: strh [[REG1]], [{{r[0-9]+}}, #16]112 ret void113}114 115; mov r1, #256116; strh r2, [r0, r1]117define void @t12(ptr nocapture %a) nounwind uwtable ssp {118entry:119; ARM-LABEL: t12:120 %add.ptr = getelementptr inbounds i16, ptr %a, i64 128121 store i16 0, ptr %add.ptr, align 2122; ARM: mov r1, r0123; ARM: movw [[REG1:r[0-9]+]], #0124; ARM: add [[REG0:r[0-9]+]], r1, #256125; ARM: strh [[REG1]], [[[REG0]]]126 ret void127}128 129define signext i8 @t13(ptr nocapture %a) nounwind uwtable readonly ssp {130entry:131; ARM-LABEL: t13:132 %add.ptr = getelementptr inbounds i8, ptr %a, i64 -8133 %0 = load i8, ptr %add.ptr, align 2134; ARM: ldrsb r0, [r0, #-8]135 ret i8 %0136}137 138define signext i8 @t14(ptr nocapture %a) nounwind uwtable readonly ssp {139entry:140; ARM-LABEL: t14:141 %add.ptr = getelementptr inbounds i8, ptr %a, i64 -255142 %0 = load i8, ptr %add.ptr, align 2143; ARM: ldrsb r0, [r0, #-255]144 ret i8 %0145}146 147define signext i8 @t15(ptr nocapture %a) nounwind uwtable readonly ssp {148entry:149; ARM-LABEL: t15:150 %add.ptr = getelementptr inbounds i8, ptr %a, i64 -256151 %0 = load i8, ptr %add.ptr, align 2152; ARM: mvn r{{[1-9]}}, #255153; ARM: add r0, r0, r{{[1-9]}}154; ARM: ldrsb r0, [r0]155 ret i8 %0156}157