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1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ALL2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ALL3 4; FIXME Add tests for thumbv7, they currently fail MI verification because5; of a mismatch in register classes in uses.6 7; This test verifies that load/store instructions are properly generated,8; and that they pass MI verification (wasn't the case until 2013-06-08).9 10@a = global i8 1, align 111@b = global i16 2, align 212@c = global i32 4, align 413 14; ldr15 16define i8 @t1() nounwind uwtable ssp {17; ALL: @t118; ALL: ldrb19; ALL: add20 %1 = load i8, ptr @a, align 121 %2 = add nsw i8 %1, 122 ret i8 %223}24 25define i16 @t2() nounwind uwtable ssp {26; ALL: @t227; ALL: ldrh28; ALL: add29 %1 = load i16, ptr @b, align 230 %2 = add nsw i16 %1, 131 ret i16 %232}33 34define i32 @t3() nounwind uwtable ssp {35; ALL: @t336; ALL: ldr37; ALL: add38 %1 = load i32, ptr @c, align 439 %2 = add nsw i32 %1, 140 ret i32 %241}42 43; str44 45define void @t4(i8 %v) nounwind uwtable ssp {46; ALL: @t447; ALL: add48; ALL: strb49 %1 = add nsw i8 %v, 150 store i8 %1, ptr @a, align 151 ret void52}53 54define void @t5(i16 %v) nounwind uwtable ssp {55; ALL: @t556; ALL: add57; ALL: strh58 %1 = add nsw i16 %v, 159 store i16 %1, ptr @b, align 260 ret void61}62 63define void @t6(i32 %v) nounwind uwtable ssp {64; ALL: @t665; ALL: add66; ALL: str67 %1 = add nsw i32 %v, 168 store i32 %1, ptr @c, align 469 ret void70}71