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1; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM2; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM3 4define i32 @shl() nounwind ssp {5entry:6; ARM: shl7; ARM: lsl r0, r0, #28 %shl = shl i32 -1, 29 ret i32 %shl10}11 12define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {13entry:14; ARM: shl_reg15; ARM: lsl r0, r0, r116 %shl = shl i32 %src1, %src217 ret i32 %shl18}19 20define i32 @lshr() nounwind ssp {21entry:22; ARM: lshr23; ARM: lsr r0, r0, #224 %lshr = lshr i32 -1, 225 ret i32 %lshr26}27 28define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {29entry:30; ARM: lshr_reg31; ARM: lsr r0, r0, r132 %lshr = lshr i32 %src1, %src233 ret i32 %lshr34}35 36define i32 @ashr() nounwind ssp {37entry:38; ARM: ashr39; ARM: asr r0, r0, #240 %ashr = ashr i32 -1, 241 ret i32 %ashr42}43 44define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {45entry:46; ARM: ashr_reg47; ARM: asr r0, r0, r148 %ashr = ashr i32 %src1, %src249 ret i32 %ashr50}51 52