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1; RUN: llc -mtriple=arm-eabihf -mattr=+vfp2 %s -o - \2; RUN: | FileCheck %s -check-prefix=VFP23 4; RUN: llc -mtriple=arm-eabihf -mattr=+vfp3 %s -o - \5; RUN: | FileCheck %s -check-prefix=VFP36 7; RUN: llc -mtriple=arm-eabihf -mattr=+neon %s -o - \8; RUN: | FileCheck %s -check-prefix=NEON9 10; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - \11; RUN: | FileCheck %s -check-prefix=A812 13; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -regalloc=basic %s -o - \14; RUN: | FileCheck %s -check-prefix=A815 16; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 --denormal-fp-math=preserve-sign %s -o - \17; RUN: | FileCheck %s -check-prefix=A8U18 19; RUN: llc -mtriple=arm-darwin -mcpu=cortex-a8 %s -o - \20; RUN: | FileCheck %s -check-prefix=A8U-DARWIN21 22define float @t1(float %acc, float %a, float %b) nounwind {23entry:24; VFP2-LABEL: t1:25; VFP2: vnmla.f3226 27; VFP3-LABEL: t1:28; VFP3: vnmla.f3229 30; NEON-LABEL: t1:31; NEON: vnmla.f3232 33; A8U-LABEL: t1:34; A8U: vmov.i32 d{{[0-9]+}}, #0x8000000035; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}36; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}37 38; A8U-DARWIN-LABEL: t1:39; A8U-DARWIN: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}40; A8U-DARWIN: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}41 42; A8-LABEL: t1:43; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}44; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}45 %0 = fmul float %a, %b46 %1 = fsub float -0.0, %047 %2 = fsub float %1, %acc48 ret float %249}50 51define float @t2(float %acc, float %a, float %b) nounwind {52entry:53; VFP2-LABEL: t2:54; VFP2: vnmla.f3255 56; VFP3-LABEL: t2:57; VFP3: vnmla.f3258 59; NEON-LABEL: t2:60; NEON: vnmla.f3261 62; A8U-LABEL: t2:63; A8U: vmov.i32 d{{[0-9]+}}, #0x8000000064; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}65; A8U: vsub.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}66 67; A8U-DARWIN-LABEL: t2:68; A8U-DARWIN: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}69; A8U-DARWIN: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}70 71; A8-LABEL: t2:72; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}73; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}74 %0 = fmul float %a, %b75 %1 = fmul float -1.0, %076 %2 = fsub float %1, %acc77 ret float %278}79 80define double @t3(double %acc, double %a, double %b) nounwind {81entry:82; VFP2-LABEL: t3:83; VFP2: vnmla.f6484 85; VFP3-LABEL: t3:86; VFP3: vnmla.f6487 88; NEON-LABEL: t3:89; NEON: vnmla.f6490 91; A8U-LABEL: t3:92; A8U: vsub.f64 d93; A8U: vsub.f64 d94 95; A8U-DARWIN-LABEL: t3:96; A8U-DARWIN: vnmul.f64 d97; A8U-DARWIN: vsub.f64 d98 99; A8-LABEL: t3:100; A8: vnmul.f64 d101; A8: vsub.f64 d102 %0 = fmul double %a, %b103 %1 = fsub double -0.0, %0104 %2 = fsub double %1, %acc105 ret double %2106}107 108define double @t4(double %acc, double %a, double %b) nounwind {109entry:110; VFP2-LABEL: t4:111; VFP2: vnmla.f64112 113; VFP3-LABEL: t4:114; VFP3: vnmla.f64115 116; NEON-LABEL: t4:117; NEON: vnmla.f64118 119; A8U-LABEL: t4:120; A8U: vsub.f64 d121; A8U: vsub.f64 d122 123; A8U-DARWIN-LABEL: t4:124; A8U-DARWIN: vnmul.f64 d125; A8U-DARWIN: vsub.f64 d126 127; A8-LABEL: t4:128; A8: vnmul.f64 d129; A8: vsub.f64 d130 %0 = fmul double %a, %b131 %1 = fmul double -1.0, %0132 %2 = fsub double %1, %acc133 ret double %2134}135 136define double @t5(double %acc, double %a, double %b) nounwind {137entry:138; VFP2-LABEL: t5:139; VFP2: vnmla.f64140 141; VFP3-LABEL: t5:142; VFP3: vnmla.f64143 144; NEON-LABEL: t5:145; NEON: vnmla.f64146 147; A8U-LABEL: t5:148; A8U: vmul.f64 d149; A8U: vsub.f64 d150 151; A8-LABEL: t5:152; A8: vmul.f64 d153; A8: vsub.f64 d154 155 %0 = fsub double -0.0, %acc156 %1 = fmul double %a, %b157 %2 = fsub double %0, %1158 ret double %2159}160 161define float @t6(float %acc, float %a, float %b) nounwind {162entry:163; VFP2-LABEL: t6:164; VFP2: vnmla.f32165 166; VFP3-LABEL: t6:167; VFP3: vnmla.f32168 169; NEON-LABEL: t6:170; NEON: vnmla.f32171 172; A8U-LABEL: t6:173; A8U: vmul.f32 d174; A8U: vsub.f32 d175 176; A8-LABEL: t6:177; A8: vmul.f32 s178; A8: vsub.f32 s179 180 %0 = fsub float -0.0, %acc181 %1 = fmul float %a, %b182 %2 = fsub float %0, %1183 ret float %2184}185