369 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard < %s | FileCheck %s --check-prefix=CHECKHARD3; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft < %s | FileCheck %s --check-prefix=CHECKSOFT4 5define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {6; CHECKHARD-LABEL: test_vget_lane_f16_1:7; CHECKHARD: @ %bb.0: @ %entry8; CHECKHARD-NEXT: vcvtt.f32.f16 s0, s09; CHECKHARD-NEXT: bx lr10;11; CHECKSOFT-LABEL: test_vget_lane_f16_1:12; CHECKSOFT: @ %bb.0: @ %entry13; CHECKSOFT-NEXT: vmov d0, r0, r114; CHECKSOFT-NEXT: vcvtt.f32.f16 s0, s015; CHECKSOFT-NEXT: vmov r0, s016; CHECKSOFT-NEXT: bx lr17entry:18 %elt = extractelement <4 x half> %a, i32 119 %conv = fpext half %elt to float20 ret float %conv21}22 23define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {24; CHECKHARD-LABEL: test_vget_lane_f16_2:25; CHECKHARD: @ %bb.0: @ %entry26; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s127; CHECKHARD-NEXT: bx lr28;29; CHECKSOFT-LABEL: test_vget_lane_f16_2:30; CHECKSOFT: @ %bb.0: @ %entry31; CHECKSOFT-NEXT: vmov d0, r0, r132; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s133; CHECKSOFT-NEXT: vmov r0, s034; CHECKSOFT-NEXT: bx lr35entry:36 %elt = extractelement <4 x half> %a, i32 237 %conv = fpext half %elt to float38 ret float %conv39}40 41define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {42; CHECKHARD-LABEL: test_vget_laneq_f16_6:43; CHECKHARD: @ %bb.0: @ %entry44; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s345; CHECKHARD-NEXT: bx lr46;47; CHECKSOFT-LABEL: test_vget_laneq_f16_6:48; CHECKSOFT: @ %bb.0: @ %entry49; CHECKSOFT-NEXT: vmov d1, r2, r350; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s351; CHECKSOFT-NEXT: vmov r0, s052; CHECKSOFT-NEXT: bx lr53entry:54 %elt = extractelement <8 x half> %a, i32 655 %conv = fpext half %elt to float56 ret float %conv57}58 59define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {60; CHECKHARD-LABEL: test_vget_laneq_f16_7:61; CHECKHARD: @ %bb.0: @ %entry62; CHECKHARD-NEXT: vcvtt.f32.f16 s0, s363; CHECKHARD-NEXT: bx lr64;65; CHECKSOFT-LABEL: test_vget_laneq_f16_7:66; CHECKSOFT: @ %bb.0: @ %entry67; CHECKSOFT-NEXT: vmov d1, r2, r368; CHECKSOFT-NEXT: vcvtt.f32.f16 s0, s369; CHECKSOFT-NEXT: vmov r0, s070; CHECKSOFT-NEXT: bx lr71entry:72 %elt = extractelement <8 x half> %a, i32 773 %conv = fpext half %elt to float74 ret float %conv75}76 77define <4 x half> @insert_v4f16(half %a) {78; CHECKHARD-LABEL: insert_v4f16:79; CHECKHARD: @ %bb.0: @ %entry80; CHECKHARD-NEXT: @ kill: def $s0 killed $s0 def $d081; CHECKHARD-NEXT: bx lr82;83; CHECKSOFT-LABEL: insert_v4f16:84; CHECKSOFT: @ %bb.0: @ %entry85; CHECKSOFT-NEXT: vmov.f16 s0, r086; CHECKSOFT-NEXT: vmov r0, r1, d087; CHECKSOFT-NEXT: bx lr88entry:89 %res = insertelement <4 x half> undef, half %a, i32 090 ret <4 x half> %res91}92 93define <8 x half> @insert_v8f16(half %a) {94; CHECKHARD-LABEL: insert_v8f16:95; CHECKHARD: @ %bb.0: @ %entry96; CHECKHARD-NEXT: @ kill: def $s0 killed $s0 def $q097; CHECKHARD-NEXT: bx lr98;99; CHECKSOFT-LABEL: insert_v8f16:100; CHECKSOFT: @ %bb.0: @ %entry101; CHECKSOFT-NEXT: vmov.f16 s0, r0102; CHECKSOFT-NEXT: vmov r2, r3, d1103; CHECKSOFT-NEXT: vmov r0, r1, d0104; CHECKSOFT-NEXT: bx lr105entry:106 %res = insertelement <8 x half> undef, half %a, i32 0107 ret <8 x half> %res108}109 110define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {111; CHECKHARD-LABEL: test_vset_lane_f16:112; CHECKHARD: @ %bb.0: @ %entry113; CHECKHARD-NEXT: vcvtt.f16.f32 s1, s2114; CHECKHARD-NEXT: bx lr115;116; CHECKSOFT-LABEL: test_vset_lane_f16:117; CHECKSOFT: @ %bb.0: @ %entry118; CHECKSOFT-NEXT: vmov d0, r0, r1119; CHECKSOFT-NEXT: vmov s2, r2120; CHECKSOFT-NEXT: vcvtt.f16.f32 s1, s2121; CHECKSOFT-NEXT: vmov r0, r1, d0122; CHECKSOFT-NEXT: bx lr123entry:124 %b = fptrunc float %fb to half125 %x = insertelement <4 x half> %a, half %b, i32 3126 ret <4 x half> %x127}128 129define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {130; CHECKHARD-LABEL: test_vset_laneq_f16_1:131; CHECKHARD: @ %bb.0: @ %entry132; CHECKHARD-NEXT: vcvtt.f16.f32 s0, s4133; CHECKHARD-NEXT: bx lr134;135; CHECKSOFT-LABEL: test_vset_laneq_f16_1:136; CHECKSOFT: @ %bb.0: @ %entry137; CHECKSOFT-NEXT: vmov d1, r2, r3138; CHECKSOFT-NEXT: vldr s4, [sp]139; CHECKSOFT-NEXT: vmov d0, r0, r1140; CHECKSOFT-NEXT: vcvtt.f16.f32 s0, s4141; CHECKSOFT-NEXT: vmov r2, r3, d1142; CHECKSOFT-NEXT: vmov r0, r1, d0143; CHECKSOFT-NEXT: bx lr144entry:145 %b = fptrunc float %fb to half146 %x = insertelement <8 x half> %a, half %b, i32 1147 ret <8 x half> %x148}149 150define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {151; CHECKHARD-LABEL: test_vset_laneq_f16_7:152; CHECKHARD: @ %bb.0: @ %entry153; CHECKHARD-NEXT: vcvtt.f16.f32 s3, s4154; CHECKHARD-NEXT: bx lr155;156; CHECKSOFT-LABEL: test_vset_laneq_f16_7:157; CHECKSOFT: @ %bb.0: @ %entry158; CHECKSOFT-NEXT: vmov d1, r2, r3159; CHECKSOFT-NEXT: vldr s4, [sp]160; CHECKSOFT-NEXT: vmov d0, r0, r1161; CHECKSOFT-NEXT: vcvtt.f16.f32 s3, s4162; CHECKSOFT-NEXT: vmov r0, r1, d0163; CHECKSOFT-NEXT: vmov r2, r3, d1164; CHECKSOFT-NEXT: bx lr165entry:166 %b = fptrunc float %fb to half167 %x = insertelement <8 x half> %a, half %b, i32 7168 ret <8 x half> %x169}170 171define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {172; CHECKHARD-LABEL: shuffle3step_f16:173; CHECKHARD: @ %bb.0: @ %entry174; CHECKHARD-NEXT: vmov r1, s0175; CHECKHARD-NEXT: vmovx.f16 s12, s1176; CHECKHARD-NEXT: vmov r0, s12177; CHECKHARD-NEXT: vrev32.16 d16, d3178; CHECKHARD-NEXT: vext.16 d17, d4, d5, #2179; CHECKHARD-NEXT: vmovx.f16 s12, s4180; CHECKHARD-NEXT: vext.16 d16, d16, d3, #1181; CHECKHARD-NEXT: vext.16 d16, d17, d16, #2182; CHECKHARD-NEXT: vext.16 d16, d16, d17, #1183; CHECKHARD-NEXT: vext.16 d17, d16, d16, #1184; CHECKHARD-NEXT: vmov.16 d16[0], r1185; CHECKHARD-NEXT: vmov.16 d16[1], r0186; CHECKHARD-NEXT: vmov r0, s3187; CHECKHARD-NEXT: vmov.16 d16[2], r0188; CHECKHARD-NEXT: vmov r0, s12189; CHECKHARD-NEXT: vmovx.f16 s12, s0190; CHECKHARD-NEXT: vmov r1, s12191; CHECKHARD-NEXT: vmovx.f16 s12, s3192; CHECKHARD-NEXT: vmov.16 d16[3], r0193; CHECKHARD-NEXT: vmov r0, s2194; CHECKHARD-NEXT: vmov.16 d18[0], r1195; CHECKHARD-NEXT: vmov.16 d18[1], r0196; CHECKHARD-NEXT: vmov r0, s12197; CHECKHARD-NEXT: vdup.16 q3, d3[1]198; CHECKHARD-NEXT: vmov r1, s12199; CHECKHARD-NEXT: vmovx.f16 s12, s9200; CHECKHARD-NEXT: vmov.16 d18[2], r0201; CHECKHARD-NEXT: vmov r0, s5202; CHECKHARD-NEXT: vmov.16 d18[3], r0203; CHECKHARD-NEXT: vmov r0, s8204; CHECKHARD-NEXT: vmov.16 d19[0], r1205; CHECKHARD-NEXT: vmov.16 d19[1], r0206; CHECKHARD-NEXT: vmov r0, s12207; CHECKHARD-NEXT: vmov.16 d19[2], r0208; CHECKHARD-NEXT: vmov r0, s11209; CHECKHARD-NEXT: vmov.16 d19[3], r0210; CHECKHARD-NEXT: vadd.f16 q8, q8, q9211; CHECKHARD-NEXT: vext.16 d18, d0, d1, #2212; CHECKHARD-NEXT: vmovx.f16 s0, s8213; CHECKHARD-NEXT: vmov r0, s0214; CHECKHARD-NEXT: vdup.16 q0, d3[2]215; CHECKHARD-NEXT: vext.16 d19, d18, d2, #3216; CHECKHARD-NEXT: vmov r1, s0217; CHECKHARD-NEXT: vext.16 d18, d2, d18, #1218; CHECKHARD-NEXT: vmovx.f16 s0, s11219; CHECKHARD-NEXT: vext.16 d18, d18, d19, #2220; CHECKHARD-NEXT: vext.16 d18, d18, d18, #1221; CHECKHARD-NEXT: vmov.16 d19[0], r1222; CHECKHARD-NEXT: vmov.16 d19[1], r0223; CHECKHARD-NEXT: vmov r0, s10224; CHECKHARD-NEXT: vmov.16 d19[2], r0225; CHECKHARD-NEXT: vmov r0, s0226; CHECKHARD-NEXT: vmov.16 d19[3], r0227; CHECKHARD-NEXT: vadd.f16 q0, q8, q9228; CHECKHARD-NEXT: bx lr229;230; CHECKSOFT-LABEL: shuffle3step_f16:231; CHECKSOFT: @ %bb.0: @ %entry232; CHECKSOFT-NEXT: vmov r1, s0233; CHECKSOFT-NEXT: vmovx.f16 s12, s1234; CHECKSOFT-NEXT: vmov r0, s12235; CHECKSOFT-NEXT: vrev32.16 d16, d3236; CHECKSOFT-NEXT: vext.16 d17, d4, d5, #2237; CHECKSOFT-NEXT: vmovx.f16 s12, s4238; CHECKSOFT-NEXT: vext.16 d16, d16, d3, #1239; CHECKSOFT-NEXT: vext.16 d16, d17, d16, #2240; CHECKSOFT-NEXT: vext.16 d16, d16, d17, #1241; CHECKSOFT-NEXT: vext.16 d17, d16, d16, #1242; CHECKSOFT-NEXT: vmov.16 d16[0], r1243; CHECKSOFT-NEXT: vmov.16 d16[1], r0244; CHECKSOFT-NEXT: vmov r0, s3245; CHECKSOFT-NEXT: vmov.16 d16[2], r0246; CHECKSOFT-NEXT: vmov r0, s12247; CHECKSOFT-NEXT: vmovx.f16 s12, s0248; CHECKSOFT-NEXT: vmov r1, s12249; CHECKSOFT-NEXT: vmovx.f16 s12, s3250; CHECKSOFT-NEXT: vmov.16 d16[3], r0251; CHECKSOFT-NEXT: vmov r0, s2252; CHECKSOFT-NEXT: vmov.16 d18[0], r1253; CHECKSOFT-NEXT: vmov.16 d18[1], r0254; CHECKSOFT-NEXT: vmov r0, s12255; CHECKSOFT-NEXT: vdup.16 q3, d3[1]256; CHECKSOFT-NEXT: vmov r1, s12257; CHECKSOFT-NEXT: vmovx.f16 s12, s9258; CHECKSOFT-NEXT: vmov.16 d18[2], r0259; CHECKSOFT-NEXT: vmov r0, s5260; CHECKSOFT-NEXT: vmov.16 d18[3], r0261; CHECKSOFT-NEXT: vmov r0, s8262; CHECKSOFT-NEXT: vmov.16 d19[0], r1263; CHECKSOFT-NEXT: vmov.16 d19[1], r0264; CHECKSOFT-NEXT: vmov r0, s12265; CHECKSOFT-NEXT: vmov.16 d19[2], r0266; CHECKSOFT-NEXT: vmov r0, s11267; CHECKSOFT-NEXT: vmov.16 d19[3], r0268; CHECKSOFT-NEXT: vadd.f16 q8, q8, q9269; CHECKSOFT-NEXT: vext.16 d18, d0, d1, #2270; CHECKSOFT-NEXT: vmovx.f16 s0, s8271; CHECKSOFT-NEXT: vmov r0, s0272; CHECKSOFT-NEXT: vdup.16 q0, d3[2]273; CHECKSOFT-NEXT: vext.16 d19, d18, d2, #3274; CHECKSOFT-NEXT: vmov r1, s0275; CHECKSOFT-NEXT: vext.16 d18, d2, d18, #1276; CHECKSOFT-NEXT: vmovx.f16 s0, s11277; CHECKSOFT-NEXT: vext.16 d18, d18, d19, #2278; CHECKSOFT-NEXT: vext.16 d18, d18, d18, #1279; CHECKSOFT-NEXT: vmov.16 d19[0], r1280; CHECKSOFT-NEXT: vmov.16 d19[1], r0281; CHECKSOFT-NEXT: vmov r0, s10282; CHECKSOFT-NEXT: vmov.16 d19[2], r0283; CHECKSOFT-NEXT: vmov r0, s0284; CHECKSOFT-NEXT: vmov.16 d19[3], r0285; CHECKSOFT-NEXT: vadd.f16 q0, q8, q9286; CHECKSOFT-NEXT: bx lr287entry:288 %s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>289 %s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>290 %s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>291 %a = fadd <8 x half> %s1, %s2292 %r = fadd <8 x half> %a, %s3293 ret <8 x half> %r294}295 296define i16 @extract_v4i16(<4 x half> %a) {297; CHECKHARD-LABEL: extract_v4i16:298; CHECKHARD: @ %bb.0: @ %entry299; CHECKHARD-NEXT: vmov.u16 r0, d0[0]300; CHECKHARD-NEXT: bx lr301;302; CHECKSOFT-LABEL: extract_v4i16:303; CHECKSOFT: @ %bb.0: @ %entry304; CHECKSOFT-NEXT: vmov d16, r0, r1305; CHECKSOFT-NEXT: vmov.u16 r0, d16[0]306; CHECKSOFT-NEXT: bx lr307entry:308 %elt = extractelement <4 x half> %a, i32 0309 %t = bitcast half %elt to i16310 ret i16 %t311}312 313define i16 @extract_v8i16(<8 x half> %a) {314; CHECKHARD-LABEL: extract_v8i16:315; CHECKHARD: @ %bb.0: @ %entry316; CHECKHARD-NEXT: vmov.u16 r0, d0[0]317; CHECKHARD-NEXT: bx lr318;319; CHECKSOFT-LABEL: extract_v8i16:320; CHECKSOFT: @ %bb.0: @ %entry321; CHECKSOFT-NEXT: vmov d16, r0, r1322; CHECKSOFT-NEXT: vmov.u16 r0, d16[0]323; CHECKSOFT-NEXT: bx lr324entry:325 %elt = extractelement <8 x half> %a, i32 0326 %t = bitcast half %elt to i16327 ret i16 %t328}329 330define i32 @extract_v4s32(<4 x half> %a) {331; CHECKHARD-LABEL: extract_v4s32:332; CHECKHARD: @ %bb.0: @ %entry333; CHECKHARD-NEXT: vmov.u16 r0, d0[0]334; CHECKHARD-NEXT: sxth r0, r0335; CHECKHARD-NEXT: bx lr336;337; CHECKSOFT-LABEL: extract_v4s32:338; CHECKSOFT: @ %bb.0: @ %entry339; CHECKSOFT-NEXT: vmov d16, r0, r1340; CHECKSOFT-NEXT: vmov.u16 r0, d16[0]341; CHECKSOFT-NEXT: sxth r0, r0342; CHECKSOFT-NEXT: bx lr343entry:344 %elt = extractelement <4 x half> %a, i32 0345 %t = bitcast half %elt to i16346 %s = sext i16 %t to i32347 ret i32 %s348}349 350define i32 @extract_v8s32(<8 x half> %a) {351; CHECKHARD-LABEL: extract_v8s32:352; CHECKHARD: @ %bb.0: @ %entry353; CHECKHARD-NEXT: vmov.u16 r0, d0[0]354; CHECKHARD-NEXT: sxth r0, r0355; CHECKHARD-NEXT: bx lr356;357; CHECKSOFT-LABEL: extract_v8s32:358; CHECKSOFT: @ %bb.0: @ %entry359; CHECKSOFT-NEXT: vmov d16, r0, r1360; CHECKSOFT-NEXT: vmov.u16 r0, d16[0]361; CHECKSOFT-NEXT: sxth r0, r0362; CHECKSOFT-NEXT: bx lr363entry:364 %elt = extractelement <8 x half> %a, i32 0365 %t = bitcast half %elt to i16366 %s = sext i16 %t to i32367 ret i32 %s368}369