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1# RUN: llc -mtriple=thumbv7-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s2#3# This checks alignment of a new block when a big basic block is split up.4#5--- |6 ; ModuleID = '<stdin>'7 source_filename = "<stdin>"8 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"9 target triple = "thumbv7-arm--eabi"10 11 declare i32 @llvm.arm.space(i32, i32) #012 13 define dso_local i32 @THUMB(i32 %A.coerce) local_unnamed_addr #1 {14 entry:15 %F = alloca float, align 416 %S = alloca half, align 217 %tmp.0.extract.trunc = trunc i32 %A.coerce to i1618 %0 = bitcast i16 %tmp.0.extract.trunc to half19 store volatile float 4.200000e+01, ptr %F, align 420 store volatile half 0xH3C00, ptr %S, align 221 %S.0.S.0.142 = load volatile half, ptr %S, align 222 %1 = call i32 @llvm.arm.space(i32 1230, i32 undef)23 %add42 = fadd half %S.0.S.0.142, 0xH2E6624 store volatile half %add42, ptr %S, align 225 %2 = call i32 @llvm.arm.space(i32 1330, i32 undef)26 %S.0.S.0.119 = load volatile half, ptr %S, align 227 %3 = bitcast half %add42 to i1628 %tmp87.0.insert.ext = zext i16 %3 to i3229 ret i32 %tmp87.0.insert.ext30 }31 32 attributes #0 = { nounwind }33 attributes #1 = { minsize nounwind optsize "target-features"="+crc,+crypto,+dsp,+fp-armv8,+fullfp16,+hwdiv,+hwdiv-arm,+neon,+ras,+strict-align,+thumb-mode" }34 35...36---37name: THUMB38alignment: 239tracksRegLiveness: true40frameInfo:41 stackSize: 842 maxAlignment: 443 maxCallFrameSize: 044stack:45 - { id: 0, name: F, offset: -4, size: 4, alignment: 4, stack-id: default, local-offset: -4 }46 - { id: 1, name: S, offset: -6, size: 2, alignment: 2, stack-id: default, local-offset: -6 }47constants:48 - id: 049 value: i32 110991769650 alignment: 451 - id: 152 value: half 0xH2E6653 alignment: 254 55#CHECK: t2B %[[BB3:bb.[0-9]]]56#CHECK: bb.{{.}} (align 4):57#CHECK: successors:58#CHECK: CONSTPOOL_ENTRY 2, %const.{{.}}, 459#CHECK: bb.{{.}} (align 2):60#CHECK: successors:61#CHECK: CONSTPOOL_ENTRY 3, %const.{{.}}, 262#CHECK: [[BB3]].entry (align 2):63 64body: |65 bb.0.entry:66 $sp = frame-setup tSUBspi $sp, 2, 14, $noreg67 frame-setup CFI_INSTRUCTION def_cfa_offset 868 renamable $r0 = tLDRpci %const.0, 14, $noreg :: (load (s32) from constant-pool)69 renamable $s0 = FCONSTH 112, 14, $noreg70 tSTRspi killed renamable $r0, $sp, 1, 14, $noreg :: (volatile store (s32) into %ir.F)71 VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S)72 renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load (s16) from %ir.S)73 renamable $s0 = VLDRH %const.1, 0, 14, $noreg :: (load (s16) from constant-pool)74 dead renamable $r0 = SPACE 1230, undef renamable $r075 renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg, implicit $fpscr_rm76 VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store (s16) into %ir.S)77 renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg78 dead renamable $r1 = SPACE 1330, undef renamable $r079 dead renamable $s0 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load (s16) from %ir.S)80 $sp = tADDspi $sp, 2, 14, $noreg81 tBX_RET 14, $noreg, implicit killed $r082 83...84