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1; RUN: llc -mattr=+fp16 < %s | FileCheck %s2 3target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"4target triple = "armv7a--none-eabi"5 6; CHECK-LABEL: test_vec3:7; CHECK-DAG: vmov.f32 [[SREG1:s[0-9]+]], #1.200000e+018; CHECK-DAG: vcvt.f32.s32 [[SREG2:s[0-9]+]],9; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]]10; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]]11; CHECK: vadd.f32 [[SREG5:s[0-9]+]], [[SREG4]], [[SREG1]]12; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]]13; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG6]]14; CHECK-DAG: uxth [[RREG2:r[0-9]+]], [[RREG1]]15; CHECK-DAG: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #1616; CHECK-DAG: strh [[RREG1]], [r0, #4]17; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]]18; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32]19; CHECK-NEXT: bx lr20define void @test_vec3(ptr %arr, i32 %i) #0 {21 %H = sitofp i32 %i to half22 %S = fadd half %H, 0xH4A0023 %1 = insertelement <3 x half> undef, half %S, i32 024 %2 = insertelement <3 x half> %1, half %S, i32 125 %3 = insertelement <3 x half> %2, half %S, i32 226 store <3 x half> %3, ptr %arr, align 827 ret void28}29 30; CHECK-LABEL: test_bitcast:31; CHECK: pkhbt32; CHECK: uxth33define void @test_bitcast(<3 x half> %inp, ptr %arr) #0 {34 %bc = bitcast <3 x half> %inp to <3 x i16>35 store <3 x i16> %bc, ptr %arr, align 836 ret void37}38 39attributes #0 = { nounwind }40