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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple armv8a-none-none-eabihf -mattr=fullfp16 < %s | FileCheck %s3 4define <4 x half> @fptrunc_vector_f32_f16(<4 x float> %a) {5; CHECK-LABEL: fptrunc_vector_f32_f16:6; CHECK: @ %bb.0: @ %bb7; CHECK-NEXT: vcvt.f16.f32 d0, q08; CHECK-NEXT: bx lr9bb:10 %z = fptrunc <4 x float> %a to <4 x half>11 ret <4 x half> %z12}13 14define <4 x half> @fptrunc_vector_f64_f16(<4 x double> %a) {15; CHECK-LABEL: fptrunc_vector_f64_f16:16; CHECK: @ %bb.0: @ %bb17; CHECK-NEXT: vcvtb.f16.f64 s0, d018; CHECK-NEXT: vcvtb.f16.f64 s8, d119; CHECK-NEXT: vmov r1, s020; CHECK-NEXT: vcvtb.f16.f64 s2, d221; CHECK-NEXT: vmov r0, s822; CHECK-NEXT: vmov.16 d0[0], r123; CHECK-NEXT: vmov.16 d0[1], r024; CHECK-NEXT: vmov r0, s225; CHECK-NEXT: vcvtb.f16.f64 s2, d326; CHECK-NEXT: vmov.16 d0[2], r027; CHECK-NEXT: vmov r0, s228; CHECK-NEXT: vmov.16 d0[3], r029; CHECK-NEXT: bx lr30bb:31 %z = fptrunc <4 x double> %a to <4 x half>32 ret <4 x half> %z33}34 35define <4 x float> @fpext_vector_f16_f32(<4 x half> %a) {36; CHECK-LABEL: fpext_vector_f16_f32:37; CHECK: @ %bb.0: @ %bb38; CHECK-NEXT: vcvt.f32.f16 q0, d039; CHECK-NEXT: bx lr40bb:41 %z = fpext <4 x half> %a to <4 x float>42 ret <4 x float> %z43}44 45define <4 x double> @fpext_vector_f16_f64(<4 x half> %a) {46; CHECK-LABEL: fpext_vector_f16_f64:47; CHECK: @ %bb.0: @ %bb48; CHECK-NEXT: vmovx.f16 s4, s049; CHECK-NEXT: vmovx.f16 s2, s150; CHECK-NEXT: vcvtb.f64.f16 d17, s451; CHECK-NEXT: vcvtb.f64.f16 d3, s252; CHECK-NEXT: vcvtb.f64.f16 d16, s053; CHECK-NEXT: vcvtb.f64.f16 d2, s154; CHECK-NEXT: vorr q0, q8, q855; CHECK-NEXT: bx lr56bb:57 %z = fpext <4 x half> %a to <4 x double>58 ret <4 x double> %z59}60