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1; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s2; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s3 4define <4 x half> @vld1d_lane_f16(ptr %pa, <4 x half> %v4) nounwind {5; CHECK-LABEL: vld1d_lane_f16:6; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]7entry:8 %a = load half, ptr %pa9 %res = insertelement <4 x half> %v4, half %a, i32 310 ret <4 x half> %res11}12 13define <8 x half> @vld1q_lane_f16_1(ptr %pa, <8 x half> %v8) nounwind {14; CHECK-LABEL: vld1q_lane_f16_1:15; CHECK: vld1.16 {d{{[0-9]+}}[1]}, [r0:16]16entry:17 %a = load half, ptr %pa18 %res = insertelement <8 x half> %v8, half %a, i32 119 ret <8 x half> %res20}21 22define <8 x half> @vld1q_lane_f16_7(ptr %pa, <8 x half> %v8) nounwind {23; CHECK-LABEL: vld1q_lane_f16_7:24; CHECK: vld1.16 {d{{[0-9]+}}[3]}, [r0:16]25entry:26 %a = load half, ptr %pa27 %res = insertelement <8 x half> %v8, half %a, i32 728 ret <8 x half> %res29}30 31define void @vst1d_lane_f16(ptr %pa, <4 x half> %v4) nounwind {32; CHECK-LABEL: vst1d_lane_f16:33; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]34entry:35 %a = extractelement <4 x half> %v4, i32 336 store half %a, ptr %pa37 ret void38}39 40define void @vst1q_lane_f16_7(ptr %pa, <8 x half> %v8) nounwind {41; CHECK-LABEL: vst1q_lane_f16_7:42; CHECK: vst1.16 {d{{[0-9]+}}[3]}, [r0:16]43entry:44 %a = extractelement <8 x half> %v8, i32 745 store half %a, ptr %pa46 ret void47}48 49define void @vst1q_lane_f16_1(ptr %pa, <8 x half> %v8) nounwind {50; CHECK-LABEL: vst1q_lane_f16_1:51; CHECK: vst1.16 {d{{[0-9]+}}[1]}, [r0:16]52entry:53 %a = extractelement <8 x half> %v8, i32 154 store half %a, ptr %pa55 ret void56}57