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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv8-eabi -mattr=+fullfp16 | FileCheck %s3; RUN: llc < %s -mtriple thumbv7a -mattr=+fullfp16 | FileCheck %s4 5define half @fp16_vminnm_o(half %a, half %b) {6; CHECK-LABEL: fp16_vminnm_o:7; CHECK: @ %bb.0: @ %entry8; CHECK-NEXT: vmov.f16 s0, r09; CHECK-NEXT: vmov.f16 s2, r110; CHECK-NEXT: vcmp.f16 s2, s011; CHECK-NEXT: vmrs APSR_nzcv, fpscr12; CHECK-NEXT: vselgt.f16 s0, s0, s213; CHECK-NEXT: vmov r0, s014; CHECK-NEXT: bx lr15entry:16 %cmp = fcmp olt half %a, %b17 %cond = select i1 %cmp, half %a, half %b18 ret half %cond19}20 21define half @fp16_vminnm_o_rev(half %a, half %b) {22; CHECK-LABEL: fp16_vminnm_o_rev:23; CHECK: @ %bb.0: @ %entry24; CHECK-NEXT: vmov.f16 s0, r125; CHECK-NEXT: vmov.f16 s2, r026; CHECK-NEXT: vcmp.f16 s2, s027; CHECK-NEXT: vmrs APSR_nzcv, fpscr28; CHECK-NEXT: vselgt.f16 s0, s2, s029; CHECK-NEXT: vmov r0, s030; CHECK-NEXT: bx lr31entry:32 %cmp = fcmp ogt half %a, %b33 %cond = select i1 %cmp, half %a, half %b34 ret half %cond35}36 37define half @fp16_vminnm_u(half %a, half %b) {38; CHECK-LABEL: fp16_vminnm_u:39; CHECK: @ %bb.0: @ %entry40; CHECK-NEXT: vmov.f16 s0, r141; CHECK-NEXT: vmov.f16 s2, r042; CHECK-NEXT: vcmp.f16 s2, s043; CHECK-NEXT: vmrs APSR_nzcv, fpscr44; CHECK-NEXT: vselge.f16 s0, s0, s245; CHECK-NEXT: vmov r0, s046; CHECK-NEXT: bx lr47entry:48 %cmp = fcmp ult half %a, %b49 %cond = select i1 %cmp, half %a, half %b50 ret half %cond51}52 53define half @fp16_vminnm_ule(half %a, half %b) {54; CHECK-LABEL: fp16_vminnm_ule:55; CHECK: @ %bb.0: @ %entry56; CHECK-NEXT: vmov.f16 s0, r157; CHECK-NEXT: vmov.f16 s2, r058; CHECK-NEXT: vcmp.f16 s2, s059; CHECK-NEXT: vmrs APSR_nzcv, fpscr60; CHECK-NEXT: vselgt.f16 s0, s0, s261; CHECK-NEXT: vmov r0, s062; CHECK-NEXT: bx lr63entry:64 %cmp = fcmp ule half %a, %b65 %cond = select i1 %cmp, half %a, half %b66 ret half %cond67}68 69define half @fp16_vminnm_u_rev(half %a, half %b) {70; CHECK-LABEL: fp16_vminnm_u_rev:71; CHECK: @ %bb.0: @ %entry72; CHECK-NEXT: vmov.f16 s0, r073; CHECK-NEXT: vmov.f16 s2, r174; CHECK-NEXT: vcmp.f16 s2, s075; CHECK-NEXT: vmrs APSR_nzcv, fpscr76; CHECK-NEXT: vselge.f16 s0, s0, s277; CHECK-NEXT: vmov r0, s078; CHECK-NEXT: bx lr79entry:80 %cmp = fcmp ugt half %a, %b81 %cond = select i1 %cmp, half %b, half %a82 ret half %cond83}84 85define half @fp16_vmaxnm_o(half %a, half %b) {86; CHECK-LABEL: fp16_vmaxnm_o:87; CHECK: @ %bb.0: @ %entry88; CHECK-NEXT: vmov.f16 s0, r189; CHECK-NEXT: vmov.f16 s2, r090; CHECK-NEXT: vcmp.f16 s2, s091; CHECK-NEXT: vmrs APSR_nzcv, fpscr92; CHECK-NEXT: vselgt.f16 s0, s2, s093; CHECK-NEXT: vmov r0, s094; CHECK-NEXT: bx lr95entry:96 %cmp = fcmp ogt half %a, %b97 %cond = select i1 %cmp, half %a, half %b98 ret half %cond99}100 101define half @fp16_vmaxnm_oge(half %a, half %b) {102; CHECK-LABEL: fp16_vmaxnm_oge:103; CHECK: @ %bb.0: @ %entry104; CHECK-NEXT: vmov.f16 s0, r1105; CHECK-NEXT: vmov.f16 s2, r0106; CHECK-NEXT: vcmp.f16 s2, s0107; CHECK-NEXT: vmrs APSR_nzcv, fpscr108; CHECK-NEXT: vselge.f16 s0, s2, s0109; CHECK-NEXT: vmov r0, s0110; CHECK-NEXT: bx lr111entry:112 %cmp = fcmp oge half %a, %b113 %cond = select i1 %cmp, half %a, half %b114 ret half %cond115}116 117define half @fp16_vmaxnm_o_rev(half %a, half %b) {118; CHECK-LABEL: fp16_vmaxnm_o_rev:119; CHECK: @ %bb.0: @ %entry120; CHECK-NEXT: vmov.f16 s0, r0121; CHECK-NEXT: vmov.f16 s2, r1122; CHECK-NEXT: vcmp.f16 s2, s0123; CHECK-NEXT: vmrs APSR_nzcv, fpscr124; CHECK-NEXT: vselgt.f16 s0, s2, s0125; CHECK-NEXT: vmov r0, s0126; CHECK-NEXT: bx lr127entry:128 %cmp = fcmp olt half %a, %b129 %cond = select i1 %cmp, half %b, half %a130 ret half %cond131}132 133define half @fp16_vmaxnm_ole_rev(half %a, half %b) {134; CHECK-LABEL: fp16_vmaxnm_ole_rev:135; CHECK: @ %bb.0: @ %entry136; CHECK-NEXT: vmov.f16 s0, r0137; CHECK-NEXT: vmov.f16 s2, r1138; CHECK-NEXT: vcmp.f16 s2, s0139; CHECK-NEXT: vmrs APSR_nzcv, fpscr140; CHECK-NEXT: vselge.f16 s0, s2, s0141; CHECK-NEXT: vmov r0, s0142; CHECK-NEXT: bx lr143entry:144 %cmp = fcmp ole half %a, %b145 %cond = select i1 %cmp, half %b, half %a146 ret half %cond147}148 149define half @fp16_vmaxnm_u(half %a, half %b) {150; CHECK-LABEL: fp16_vmaxnm_u:151; CHECK: @ %bb.0: @ %entry152; CHECK-NEXT: vmov.f16 s0, r0153; CHECK-NEXT: vmov.f16 s2, r1154; CHECK-NEXT: vcmp.f16 s2, s0155; CHECK-NEXT: vmrs APSR_nzcv, fpscr156; CHECK-NEXT: vselge.f16 s0, s2, s0157; CHECK-NEXT: vmov r0, s0158; CHECK-NEXT: bx lr159entry:160 %cmp = fcmp ugt half %a, %b161 %cond = select i1 %cmp, half %a, half %b162 ret half %cond163}164 165define half @fp16_vmaxnm_uge(half %a, half %b) {166; CHECK-LABEL: fp16_vmaxnm_uge:167; CHECK: @ %bb.0: @ %entry168; CHECK-NEXT: vmov.f16 s0, r0169; CHECK-NEXT: vmov.f16 s2, r1170; CHECK-NEXT: vcmp.f16 s2, s0171; CHECK-NEXT: vmrs APSR_nzcv, fpscr172; CHECK-NEXT: vselgt.f16 s0, s2, s0173; CHECK-NEXT: vmov r0, s0174; CHECK-NEXT: bx lr175entry:176 %cmp = fcmp uge half %a, %b177 %cond = select i1 %cmp, half %a, half %b178 ret half %cond179}180 181define half @fp16_vmaxnm_u_rev(half %a, half %b) {182; CHECK-LABEL: fp16_vmaxnm_u_rev:183; CHECK: @ %bb.0: @ %entry184; CHECK-NEXT: vmov.f16 s0, r1185; CHECK-NEXT: vmov.f16 s2, r0186; CHECK-NEXT: vcmp.f16 s2, s0187; CHECK-NEXT: vmrs APSR_nzcv, fpscr188; CHECK-NEXT: vselge.f16 s0, s2, s0189; CHECK-NEXT: vmov r0, s0190; CHECK-NEXT: bx lr191entry:192 %cmp = fcmp ult half %a, %b193 %cond = select i1 %cmp, half %b, half %a194 ret half %cond195}196 197; known non-NaNs198 199define half @fp16_vminnm_NNNo(half %a) {200; CHECK-LABEL: fp16_vminnm_NNNo:201; CHECK: @ %bb.0: @ %entry202; CHECK-NEXT: vmov.f16 s0, r0203; CHECK-NEXT: vmov.f16 s2, #1.200000e+01204; CHECK-NEXT: vminnm.f16 s0, s0, s2205; CHECK-NEXT: vldr.16 s2, .LCPI12_0206; CHECK-NEXT: vcmp.f16 s0, s2207; CHECK-NEXT: vmrs APSR_nzcv, fpscr208; CHECK-NEXT: vselgt.f16 s0, s2, s0209; CHECK-NEXT: vmov r0, s0210; CHECK-NEXT: bx lr211; CHECK-NEXT: .p2align 1212; CHECK-NEXT: @ %bb.1:213; CHECK-NEXT: .LCPI12_0:214; CHECK-NEXT: .short 0x5040 @ half 34215entry:216 %cmp1 = fcmp olt half %a, 12.217 %cond1 = select i1 %cmp1, half %a, half 12.218 %cmp2 = fcmp olt half 34., %cond1219 %cond2 = select i1 %cmp2, half 34., half %cond1220 ret half %cond2221}222 223define half @fp16_vminnm_NNNo_rev(half %a) {224; CHECK-LABEL: fp16_vminnm_NNNo_rev:225; CHECK: @ %bb.0: @ %entry226; CHECK-NEXT: vldr.16 s2, .LCPI13_0227; CHECK-NEXT: vmov.f16 s0, r0228; CHECK-NEXT: vcmp.f16 s0, s2229; CHECK-NEXT: vmrs APSR_nzcv, fpscr230; CHECK-NEXT: vselgt.f16 s0, s2, s0231; CHECK-NEXT: vldr.16 s2, .LCPI13_1232; CHECK-NEXT: vminnm.f16 s0, s0, s2233; CHECK-NEXT: vmov r0, s0234; CHECK-NEXT: bx lr235; CHECK-NEXT: .p2align 1236; CHECK-NEXT: @ %bb.1:237; CHECK-NEXT: .LCPI13_0:238; CHECK-NEXT: .short 0x5300 @ half 56239; CHECK-NEXT: .LCPI13_1:240; CHECK-NEXT: .short 0x54e0 @ half 78241entry:242 %cmp1 = fcmp ogt half %a, 56.243 %cond1 = select i1 %cmp1, half 56., half %a244 %cmp2 = fcmp ogt half 78., %cond1245 %cond2 = select i1 %cmp2, half %cond1, half 78.246 ret half %cond2247}248 249define half @fp16_vminnm_NNNu(half %b) {250; CHECK-LABEL: fp16_vminnm_NNNu:251; CHECK: @ %bb.0: @ %entry252; CHECK-NEXT: vmov.f16 s0, r0253; CHECK-NEXT: vmov.f16 s2, #1.200000e+01254; CHECK-NEXT: vminnm.f16 s0, s0, s2255; CHECK-NEXT: vldr.16 s2, .LCPI14_0256; CHECK-NEXT: vcmp.f16 s0, s2257; CHECK-NEXT: vmrs APSR_nzcv, fpscr258; CHECK-NEXT: vselge.f16 s0, s2, s0259; CHECK-NEXT: vmov r0, s0260; CHECK-NEXT: bx lr261; CHECK-NEXT: .p2align 1262; CHECK-NEXT: @ %bb.1:263; CHECK-NEXT: .LCPI14_0:264; CHECK-NEXT: .short 0x5040 @ half 34265entry:266 %cmp1 = fcmp ult half 12., %b267 %cond1 = select i1 %cmp1, half 12., half %b268 %cmp2 = fcmp ult half %cond1, 34.269 %cond2 = select i1 %cmp2, half %cond1, half 34.270 ret half %cond2271}272 273define half @fp16_vminnm_NNNule(half %b) {274; CHECK-LABEL: fp16_vminnm_NNNule:275; CHECK: @ %bb.0: @ %entry276; CHECK-NEXT: vldr.16 s2, .LCPI15_0277; CHECK-NEXT: vmov.f16 s0, r0278; CHECK-NEXT: vminnm.f16 s0, s0, s2279; CHECK-NEXT: vldr.16 s2, .LCPI15_1280; CHECK-NEXT: vcmp.f16 s0, s2281; CHECK-NEXT: vmrs APSR_nzcv, fpscr282; CHECK-NEXT: vselgt.f16 s0, s2, s0283; CHECK-NEXT: vmov r0, s0284; CHECK-NEXT: bx lr285; CHECK-NEXT: .p2align 1286; CHECK-NEXT: @ %bb.1:287; CHECK-NEXT: .LCPI15_0:288; CHECK-NEXT: .short 0x5040 @ half 34289; CHECK-NEXT: .LCPI15_1:290; CHECK-NEXT: .short 0x5300 @ half 56291 292entry:293 %cmp1 = fcmp ule half 34., %b294 %cond1 = select i1 %cmp1, half 34., half %b295 %cmp2 = fcmp ule half %cond1, 56.296 %cond2 = select i1 %cmp2, half %cond1, half 56.297 ret half %cond2298}299 300define half @fp16_vminnm_NNNu_rev(half %b) {301; CHECK-LABEL: fp16_vminnm_NNNu_rev:302; CHECK: @ %bb.0: @ %entry303; CHECK-NEXT: vldr.16 s2, .LCPI16_0304; CHECK-NEXT: vmov.f16 s0, r0305; CHECK-NEXT: vcmp.f16 s0, s2306; CHECK-NEXT: vmrs APSR_nzcv, fpscr307; CHECK-NEXT: vselge.f16 s0, s2, s0308; CHECK-NEXT: vldr.16 s2, .LCPI16_1309; CHECK-NEXT: vminnm.f16 s0, s0, s2310; CHECK-NEXT: vmov r0, s0311; CHECK-NEXT: bx lr312; CHECK-NEXT: .p2align 1313; CHECK-NEXT: @ %bb.1:314; CHECK-NEXT: .LCPI16_0:315; CHECK-NEXT: .short 0x5300 @ half 56316; CHECK-NEXT: .LCPI16_1:317; CHECK-NEXT: .short 0x54e0 @ half 78318 319 320entry:321 %cmp1 = fcmp ugt half 56., %b322 %cond1 = select i1 %cmp1, half %b, half 56.323 %cmp2 = fcmp ugt half %cond1, 78.324 %cond2 = select i1 %cmp2, half 78., half %cond1325 ret half %cond2326}327 328define half @fp16_vmaxnm_NNNo(half %a) {329; CHECK-LABEL: fp16_vmaxnm_NNNo:330; CHECK: @ %bb.0: @ %entry331; CHECK-NEXT: vmov.f16 s0, r0332; CHECK-NEXT: vmov.f16 s2, #1.200000e+01333; CHECK-NEXT: vmaxnm.f16 s0, s0, s2334; CHECK-NEXT: vldr.16 s2, .LCPI17_0335; CHECK-NEXT: vcmp.f16 s2, s0336; CHECK-NEXT: vmrs APSR_nzcv, fpscr337; CHECK-NEXT: vselgt.f16 s0, s2, s0338; CHECK-NEXT: vmov r0, s0339; CHECK-NEXT: bx lr340; CHECK-NEXT: .p2align 1341; CHECK-NEXT: @ %bb.1:342; CHECK-NEXT: .LCPI17_0:343; CHECK-NEXT: .short 0x5040 @ half 34344entry:345 %cmp1 = fcmp ogt half %a, 12.346 %cond1 = select i1 %cmp1, half %a, half 12.347 %cmp2 = fcmp ogt half 34., %cond1348 %cond2 = select i1 %cmp2, half 34., half %cond1349 ret half %cond2350}351 352define half @fp16_vmaxnm_NNNoge(half %a) {353; CHECK-LABEL: fp16_vmaxnm_NNNoge:354; CHECK: @ %bb.0: @ %entry355; CHECK-NEXT: vldr.16 s2, .LCPI18_0356; CHECK-NEXT: vmov.f16 s0, r0357; CHECK-NEXT: vmaxnm.f16 s0, s0, s2358; CHECK-NEXT: vldr.16 s2, .LCPI18_1359; CHECK-NEXT: vcmp.f16 s2, s0360; CHECK-NEXT: vmrs APSR_nzcv, fpscr361; CHECK-NEXT: vselge.f16 s0, s2, s0362; CHECK-NEXT: vmov r0, s0363; CHECK-NEXT: bx lr364; CHECK-NEXT: .p2align 1365; CHECK-NEXT: @ %bb.1:366; CHECK-NEXT: .LCPI18_0:367; CHECK-NEXT: .short 0x5040 @ half 34368; CHECK-NEXT: .LCPI18_1:369; CHECK-NEXT: .short 0x5300 @ half 56370entry:371 %cmp1 = fcmp oge half %a, 34.372 %cond1 = select i1 %cmp1, half %a, half 34.373 %cmp2 = fcmp oge half 56., %cond1374 %cond2 = select i1 %cmp2, half 56., half %cond1375 ret half %cond2376}377 378define half @fp16_vmaxnm_NNNo_rev(half %a) {379; CHECK-LABEL: fp16_vmaxnm_NNNo_rev:380; CHECK: @ %bb.0: @ %entry381; CHECK-NEXT: vldr.16 s2, .LCPI19_0382; CHECK-NEXT: vmov.f16 s0, r0383; CHECK-NEXT: vcmp.f16 s2, s0384; CHECK-NEXT: vmrs APSR_nzcv, fpscr385; CHECK-NEXT: vselgt.f16 s0, s2, s0386; CHECK-NEXT: vldr.16 s2, .LCPI19_1387; CHECK-NEXT: vmaxnm.f16 s0, s0, s2388; CHECK-NEXT: vmov r0, s0389; CHECK-NEXT: bx lr390; CHECK-NEXT: .p2align 1391; CHECK-NEXT: @ %bb.1:392; CHECK-NEXT: .LCPI19_0:393; CHECK-NEXT: .short 0x5300 @ half 56394; CHECK-NEXT: .LCPI19_1:395; CHECK-NEXT: .short 0x54e0 @ half 78396entry:397 %cmp1 = fcmp olt half %a, 56.398 %cond1 = select i1 %cmp1, half 56., half %a399 %cmp2 = fcmp olt half 78., %cond1400 %cond2 = select i1 %cmp2, half %cond1, half 78.401 ret half %cond2402}403 404define half @fp16_vmaxnm_NNNole_rev(half %a) {405; CHECK-LABEL: fp16_vmaxnm_NNNole_rev:406; CHECK: @ %bb.0: @ %entry407; CHECK-NEXT: vldr.16 s2, .LCPI20_0408; CHECK-NEXT: vmov.f16 s0, r0409; CHECK-NEXT: vcmp.f16 s2, s0410; CHECK-NEXT: vmrs APSR_nzcv, fpscr411; CHECK-NEXT: vselge.f16 s0, s2, s0412; CHECK-NEXT: vldr.16 s2, .LCPI20_1413; CHECK-NEXT: vmaxnm.f16 s0, s0, s2414; CHECK-NEXT: vmov r0, s0415; CHECK-NEXT: bx lr416; CHECK-NEXT: .p2align 1417; CHECK-NEXT: @ %bb.1:418; CHECK-NEXT: .LCPI20_0:419; CHECK-NEXT: .short 0x54e0 @ half 78420; CHECK-NEXT: .LCPI20_1:421; CHECK-NEXT: .short 0x55a0 @ half 90422entry:423 %cmp1 = fcmp ole half %a, 78.424 %cond1 = select i1 %cmp1, half 78., half %a425 %cmp2 = fcmp ole half 90., %cond1426 %cond2 = select i1 %cmp2, half %cond1, half 90.427 ret half %cond2428}429 430define half @fp16_vmaxnm_NNNu(half %b) {431; CHECK-LABEL: fp16_vmaxnm_NNNu:432; CHECK: @ %bb.0: @ %entry433; CHECK-NEXT: vmov.f16 s0, r0434; CHECK-NEXT: vmov.f16 s2, #1.200000e+01435; CHECK-NEXT: vmaxnm.f16 s0, s0, s2436; CHECK-NEXT: vldr.16 s2, .LCPI21_0437; CHECK-NEXT: vcmp.f16 s2, s0438; CHECK-NEXT: vmrs APSR_nzcv, fpscr439; CHECK-NEXT: vselge.f16 s0, s2, s0440; CHECK-NEXT: vmov r0, s0441; CHECK-NEXT: bx lr442; CHECK-NEXT: .p2align 1443; CHECK-NEXT: @ %bb.1:444; CHECK-NEXT: .LCPI21_0:445; CHECK-NEXT: .short 0x5040 @ half 34446entry:447 %cmp1 = fcmp ugt half 12., %b448 %cond1 = select i1 %cmp1, half 12., half %b449 %cmp2 = fcmp ugt half %cond1, 34.450 %cond2 = select i1 %cmp2, half %cond1, half 34.451 ret half %cond2452}453 454define half @fp16_vmaxnm_NNNuge(half %b) {455; CHECK-LABEL: fp16_vmaxnm_NNNuge:456; CHECK: @ %bb.0: @ %entry457; CHECK-NEXT: vldr.16 s2, .LCPI22_0458; CHECK-NEXT: vmov.f16 s0, r0459; CHECK-NEXT: vmaxnm.f16 s0, s0, s2460; CHECK-NEXT: vldr.16 s2, .LCPI22_1461; CHECK-NEXT: vcmp.f16 s2, s0462; CHECK-NEXT: vmrs APSR_nzcv, fpscr463; CHECK-NEXT: vselgt.f16 s0, s2, s0464; CHECK-NEXT: vmov r0, s0465; CHECK-NEXT: bx lr466; CHECK-NEXT: .p2align 1467; CHECK-NEXT: @ %bb.1:468; CHECK-NEXT: .LCPI22_0:469; CHECK-NEXT: .short 0x5040 @ half 34470; CHECK-NEXT: .LCPI22_1:471; CHECK-NEXT: .short 0x5300 @ half 56472entry:473 %cmp1 = fcmp uge half 34., %b474 %cond1 = select i1 %cmp1, half 34., half %b475 %cmp2 = fcmp uge half %cond1, 56.476 %cond2 = select i1 %cmp2, half %cond1, half 56.477 ret half %cond2478}479 480define half @fp16_vminmaxnm_neg0(half %a) {481; CHECK-LABEL: fp16_vminmaxnm_neg0:482; CHECK: @ %bb.0: @ %entry483; CHECK-NEXT: vldr.16 s0, .LCPI23_0484; CHECK-NEXT: vmov.f16 s2, r0485; CHECK-NEXT: vminnm.f16 s2, s2, s0486; CHECK-NEXT: vcmp.f16 s0, s2487; CHECK-NEXT: vmrs APSR_nzcv, fpscr488; CHECK-NEXT: vselge.f16 s0, s0, s2489; CHECK-NEXT: vmov r0, s0490; CHECK-NEXT: bx lr491; CHECK-NEXT: .p2align 1492; CHECK-NEXT: @ %bb.1:493; CHECK-NEXT: .LCPI23_0:494; CHECK-NEXT: .short 0x8000 @ half -0495entry:496 %cmp1 = fcmp olt half %a, -0.497 %cond1 = select i1 %cmp1, half %a, half -0.498 %cmp2 = fcmp ugt half %cond1, -0.499 %cond2 = select i1 %cmp2, half %cond1, half -0.500 ret half %cond2501}502 503define half @fp16_vminmaxnm_e_0(half %a) {504; CHECK-LABEL: fp16_vminmaxnm_e_0:505; CHECK: @ %bb.0: @ %entry506; CHECK-NEXT: vmov.f16 s0, r0507; CHECK-NEXT: vldr.16 s2, .LCPI24_0508; CHECK-NEXT: vcmp.f16 s0, #0509; CHECK-NEXT: vmrs APSR_nzcv, fpscr510; CHECK-NEXT: vselge.f16 s0, s2, s0511; CHECK-NEXT: vmaxnm.f16 s0, s0, s2512; CHECK-NEXT: vmov r0, s0513; CHECK-NEXT: bx lr514; CHECK-NEXT: .p2align 1515; CHECK-NEXT: @ %bb.1:516; CHECK-NEXT: .LCPI24_0:517; CHECK-NEXT: .short 0x0000 @ half 0518entry:519 %cmp1 = fcmp nsz ole half 0., %a520 %cond1 = select nsz i1 %cmp1, half 0., half %a521 %cmp2 = fcmp nsz uge half 0., %cond1522 %cond2 = select nsz i1 %cmp2, half 0., half %cond1523 ret half %cond2524}525 526define half @fp16_vminmaxnm_e_neg0(half %a) {527; CHECK-LABEL: fp16_vminmaxnm_e_neg0:528; CHECK: @ %bb.0: @ %entry529; CHECK-NEXT: vldr.16 s0, .LCPI25_0530; CHECK-NEXT: vmov.f16 s2, r0531; CHECK-NEXT: vminnm.f16 s2, s2, s0532; CHECK-NEXT: vcmp.f16 s0, s2533; CHECK-NEXT: vmrs APSR_nzcv, fpscr534; CHECK-NEXT: vselge.f16 s0, s0, s2535; CHECK-NEXT: vmov r0, s0536; CHECK-NEXT: bx lr537; CHECK-NEXT: .p2align 1538; CHECK-NEXT: @ %bb.1:539; CHECK-NEXT: .LCPI25_0:540; CHECK-NEXT: .short 0x8000 @ half -0541entry:542 %cmp1 = fcmp nsz ule half -0., %a543 %cond1 = select nsz i1 %cmp1, half -0., half %a544 %cmp2 = fcmp nsz oge half -0., %cond1545 %cond2 = select i1 %cmp2, half -0., half %cond1546 ret half %cond2547}548