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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv7a-none-eabihf -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-NEON3; RUN: llc < %s -mtriple=armv8a-none-eabihf -mattr=+neon,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP164 5; i32 saturate6 7define <2 x i32> @stest_f64i32(<2 x double> %x) {8; CHECK-LABEL: stest_f64i32:9; CHECK:       @ %bb.0: @ %entry10; CHECK-NEXT:    .save {r4, r5, r11, lr}11; CHECK-NEXT:    push {r4, r5, r11, lr}12; CHECK-NEXT:    .vsave {d8, d9}13; CHECK-NEXT:    vpush {d8, d9}14; CHECK-NEXT:    vorr q4, q0, q015; CHECK-NEXT:    vmov r0, r1, d916; CHECK-NEXT:    bl __aeabi_d2lz17; CHECK-NEXT:    mov r4, r018; CHECK-NEXT:    mov r5, r119; CHECK-NEXT:    vmov r0, r1, d820; CHECK-NEXT:    vmov.32 d9[0], r421; CHECK-NEXT:    bl __aeabi_d2lz22; CHECK-NEXT:    vmov.32 d8[0], r023; CHECK-NEXT:    mvn r3, #-214748364824; CHECK-NEXT:    subs r4, r4, r325; CHECK-NEXT:    adr r2, .LCPI0_026; CHECK-NEXT:    vmov.32 d9[1], r527; CHECK-NEXT:    sbcs r5, r5, #028; CHECK-NEXT:    mov r5, #029; CHECK-NEXT:    mvn r4, #030; CHECK-NEXT:    movwlt r5, #131; CHECK-NEXT:    cmp r5, #032; CHECK-NEXT:    mvnne r5, #033; CHECK-NEXT:    subs r0, r0, r334; CHECK-NEXT:    sbcs r0, r1, #035; CHECK-NEXT:    vmov.32 d8[1], r136; CHECK-NEXT:    mov r0, #037; CHECK-NEXT:    vmov.i32 q10, #0x8000000038; CHECK-NEXT:    movwlt r0, #139; CHECK-NEXT:    cmp r0, #040; CHECK-NEXT:    vdup.32 d19, r541; CHECK-NEXT:    mvnne r0, #042; CHECK-NEXT:    vld1.64 {d16, d17}, [r2:128]43; CHECK-NEXT:    mov r2, #044; CHECK-NEXT:    vdup.32 d18, r045; CHECK-NEXT:    vbit q8, q4, q946; CHECK-NEXT:    vmov r0, r1, d1747; CHECK-NEXT:    vmov r3, r5, d1648; CHECK-NEXT:    rsbs r0, r0, #-214748364849; CHECK-NEXT:    sbcs r0, r4, r150; CHECK-NEXT:    mov r0, #051; CHECK-NEXT:    movwlt r0, #152; CHECK-NEXT:    cmp r0, #053; CHECK-NEXT:    mvnne r0, #054; CHECK-NEXT:    rsbs r1, r3, #-214748364855; CHECK-NEXT:    sbcs r1, r4, r556; CHECK-NEXT:    vdup.32 d19, r057; CHECK-NEXT:    movwlt r2, #158; CHECK-NEXT:    cmp r2, #059; CHECK-NEXT:    mvnne r2, #060; CHECK-NEXT:    vdup.32 d18, r261; CHECK-NEXT:    vbif q8, q10, q962; CHECK-NEXT:    vmovn.i64 d0, q863; CHECK-NEXT:    vpop {d8, d9}64; CHECK-NEXT:    pop {r4, r5, r11, pc}65; CHECK-NEXT:    .p2align 466; CHECK-NEXT:  @ %bb.1:67; CHECK-NEXT:  .LCPI0_0:68; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff69; CHECK-NEXT:    .long 0 @ 0x070; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff71; CHECK-NEXT:    .long 0 @ 0x072entry:73  %conv = fptosi <2 x double> %x to <2 x i64>74  %0 = icmp slt <2 x i64> %conv, <i64 2147483647, i64 2147483647>75  %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>76  %1 = icmp sgt <2 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648>77  %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>78  %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>79  ret <2 x i32> %conv680}81 82define <2 x i32> @utest_f64i32(<2 x double> %x) {83; CHECK-LABEL: utest_f64i32:84; CHECK:       @ %bb.0: @ %entry85; CHECK-NEXT:    .save {r4, r5, r11, lr}86; CHECK-NEXT:    push {r4, r5, r11, lr}87; CHECK-NEXT:    .vsave {d8, d9}88; CHECK-NEXT:    vpush {d8, d9}89; CHECK-NEXT:    vorr q4, q0, q090; CHECK-NEXT:    vmov r0, r1, d991; CHECK-NEXT:    bl __aeabi_d2ulz92; CHECK-NEXT:    mov r4, r093; CHECK-NEXT:    mov r5, r194; CHECK-NEXT:    vmov r0, r1, d895; CHECK-NEXT:    vmov.32 d9[0], r496; CHECK-NEXT:    bl __aeabi_d2ulz97; CHECK-NEXT:    mvn r3, #098; CHECK-NEXT:    subs r4, r4, r399; CHECK-NEXT:    sbcs r5, r5, #0100; CHECK-NEXT:    vmov.32 d8[0], r0101; CHECK-NEXT:    mov r5, #0102; CHECK-NEXT:    mov r2, #0103; CHECK-NEXT:    movwlo r5, #1104; CHECK-NEXT:    cmp r5, #0105; CHECK-NEXT:    mvnne r5, #0106; CHECK-NEXT:    subs r0, r0, r3107; CHECK-NEXT:    sbcs r0, r1, #0108; CHECK-NEXT:    vdup.32 d17, r5109; CHECK-NEXT:    movwlo r2, #1110; CHECK-NEXT:    cmp r2, #0111; CHECK-NEXT:    mvnne r2, #0112; CHECK-NEXT:    vdup.32 d16, r2113; CHECK-NEXT:    vand q9, q4, q8114; CHECK-NEXT:    vorn q8, q9, q8115; CHECK-NEXT:    vmovn.i64 d0, q8116; CHECK-NEXT:    vpop {d8, d9}117; CHECK-NEXT:    pop {r4, r5, r11, pc}118entry:119  %conv = fptoui <2 x double> %x to <2 x i64>120  %0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>121  %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>122  %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>123  ret <2 x i32> %conv6124}125 126define <2 x i32> @ustest_f64i32(<2 x double> %x) {127; CHECK-LABEL: ustest_f64i32:128; CHECK:       @ %bb.0: @ %entry129; CHECK-NEXT:    .save {r4, r5, r11, lr}130; CHECK-NEXT:    push {r4, r5, r11, lr}131; CHECK-NEXT:    .vsave {d8, d9}132; CHECK-NEXT:    vpush {d8, d9}133; CHECK-NEXT:    vorr q4, q0, q0134; CHECK-NEXT:    vmov r0, r1, d9135; CHECK-NEXT:    bl __aeabi_d2lz136; CHECK-NEXT:    mov r4, r0137; CHECK-NEXT:    mov r5, r1138; CHECK-NEXT:    vmov r0, r1, d8139; CHECK-NEXT:    vmov.32 d9[0], r4140; CHECK-NEXT:    bl __aeabi_d2lz141; CHECK-NEXT:    vmov.32 d8[0], r0142; CHECK-NEXT:    mvn r3, #0143; CHECK-NEXT:    subs r4, r4, r3144; CHECK-NEXT:    vmov.i64 q9, #0xffffffff145; CHECK-NEXT:    vmov.32 d9[1], r5146; CHECK-NEXT:    sbcs r5, r5, #0147; CHECK-NEXT:    mov r5, #0148; CHECK-NEXT:    mov r2, #0149; CHECK-NEXT:    movwlt r5, #1150; CHECK-NEXT:    cmp r5, #0151; CHECK-NEXT:    mvnne r5, #0152; CHECK-NEXT:    subs r0, r0, r3153; CHECK-NEXT:    sbcs r0, r1, #0154; CHECK-NEXT:    vmov.32 d8[1], r1155; CHECK-NEXT:    mov r0, #0156; CHECK-NEXT:    movwlt r0, #1157; CHECK-NEXT:    cmp r0, #0158; CHECK-NEXT:    vdup.32 d17, r5159; CHECK-NEXT:    mvnne r0, #0160; CHECK-NEXT:    vdup.32 d16, r0161; CHECK-NEXT:    vbsl q8, q4, q9162; CHECK-NEXT:    vmov r0, r1, d17163; CHECK-NEXT:    vmov r3, r5, d16164; CHECK-NEXT:    rsbs r0, r0, #0165; CHECK-NEXT:    rscs r0, r1, #0166; CHECK-NEXT:    mov r0, #0167; CHECK-NEXT:    movwlt r0, #1168; CHECK-NEXT:    cmp r0, #0169; CHECK-NEXT:    mvnne r0, #0170; CHECK-NEXT:    rsbs r1, r3, #0171; CHECK-NEXT:    rscs r1, r5, #0172; CHECK-NEXT:    vmov.32 d19[0], r0173; CHECK-NEXT:    movwlt r2, #1174; CHECK-NEXT:    cmp r2, #0175; CHECK-NEXT:    mvnne r2, #0176; CHECK-NEXT:    vmov.32 d18[0], r2177; CHECK-NEXT:    vand q8, q9, q8178; CHECK-NEXT:    vmovn.i64 d0, q8179; CHECK-NEXT:    vpop {d8, d9}180; CHECK-NEXT:    pop {r4, r5, r11, pc}181entry:182  %conv = fptosi <2 x double> %x to <2 x i64>183  %0 = icmp slt <2 x i64> %conv, <i64 4294967295, i64 4294967295>184  %spec.store.select = select <2 x i1> %0, <2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>185  %1 = icmp sgt <2 x i64> %spec.store.select, zeroinitializer186  %spec.store.select7 = select <2 x i1> %1, <2 x i64> %spec.store.select, <2 x i64> zeroinitializer187  %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>188  ret <2 x i32> %conv6189}190 191define <4 x i32> @stest_f32i32(<4 x float> %x) {192; CHECK-LABEL: stest_f32i32:193; CHECK:       @ %bb.0: @ %entry194; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}195; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}196; CHECK-NEXT:    .pad #4197; CHECK-NEXT:    sub sp, sp, #4198; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}199; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}200; CHECK-NEXT:    vorr q4, q0, q0201; CHECK-NEXT:    vmov r0, s19202; CHECK-NEXT:    bl __aeabi_f2lz203; CHECK-NEXT:    mov r6, r0204; CHECK-NEXT:    vmov r0, s18205; CHECK-NEXT:    mov r7, r1206; CHECK-NEXT:    adr r1, .LCPI3_0207; CHECK-NEXT:    vld1.64 {d10, d11}, [r1:128]208; CHECK-NEXT:    vmov r5, s17209; CHECK-NEXT:    mov r4, #0210; CHECK-NEXT:    mvn r9, #-2147483648211; CHECK-NEXT:    vmov.32 d13[0], r6212; CHECK-NEXT:    bl __aeabi_f2lz213; CHECK-NEXT:    subs r2, r6, r9214; CHECK-NEXT:    vmov.32 d12[0], r0215; CHECK-NEXT:    sbcs r2, r7, #0216; CHECK-NEXT:    vmov r8, s16217; CHECK-NEXT:    mov r2, #0218; CHECK-NEXT:    vmov.32 d13[1], r7219; CHECK-NEXT:    movwlt r2, #1220; CHECK-NEXT:    cmp r2, #0221; CHECK-NEXT:    mvnne r2, #0222; CHECK-NEXT:    subs r0, r0, r9223; CHECK-NEXT:    sbcs r0, r1, #0224; CHECK-NEXT:    vdup.32 d17, r2225; CHECK-NEXT:    mov r0, #0226; CHECK-NEXT:    vmov.32 d12[1], r1227; CHECK-NEXT:    movwlt r0, #1228; CHECK-NEXT:    cmp r0, #0229; CHECK-NEXT:    mvnne r0, #0230; CHECK-NEXT:    vdup.32 d16, r0231; CHECK-NEXT:    mov r0, r5232; CHECK-NEXT:    vorr q4, q8, q8233; CHECK-NEXT:    vbsl q4, q6, q5234; CHECK-NEXT:    bl __aeabi_f2lz235; CHECK-NEXT:    vmov.32 d13[0], r0236; CHECK-NEXT:    subs r0, r0, r9237; CHECK-NEXT:    sbcs r0, r1, #0238; CHECK-NEXT:    mov r6, #0239; CHECK-NEXT:    movwlt r6, #1240; CHECK-NEXT:    cmp r6, #0241; CHECK-NEXT:    mov r0, r8242; CHECK-NEXT:    vmov r11, r10, d8243; CHECK-NEXT:    vmov.32 d13[1], r1244; CHECK-NEXT:    mvnne r6, #0245; CHECK-NEXT:    vmov r5, r7, d9246; CHECK-NEXT:    bl __aeabi_f2lz247; CHECK-NEXT:    vmov.32 d12[0], r0248; CHECK-NEXT:    subs r0, r0, r9249; CHECK-NEXT:    sbcs r0, r1, #0250; CHECK-NEXT:    mov r0, #0251; CHECK-NEXT:    vdup.32 d17, r6252; CHECK-NEXT:    movwlt r0, #1253; CHECK-NEXT:    cmp r0, #0254; CHECK-NEXT:    mvnne r0, #0255; CHECK-NEXT:    vmov.32 d12[1], r1256; CHECK-NEXT:    rsbs r3, r11, #-2147483648257; CHECK-NEXT:    vdup.32 d16, r0258; CHECK-NEXT:    mvn r0, #0259; CHECK-NEXT:    vbsl q8, q6, q5260; CHECK-NEXT:    adr r1, .LCPI3_1261; CHECK-NEXT:    vld1.64 {d18, d19}, [r1:128]262; CHECK-NEXT:    sbcs r3, r0, r10263; CHECK-NEXT:    mov r3, #0264; CHECK-NEXT:    vmov r1, r2, d17265; CHECK-NEXT:    movwlt r3, #1266; CHECK-NEXT:    cmp r3, #0267; CHECK-NEXT:    mvnne r3, #0268; CHECK-NEXT:    rsbs r6, r5, #-2147483648269; CHECK-NEXT:    vmov r6, r5, d16270; CHECK-NEXT:    sbcs r7, r0, r7271; CHECK-NEXT:    mov r7, #0272; CHECK-NEXT:    movwlt r7, #1273; CHECK-NEXT:    cmp r7, #0274; CHECK-NEXT:    mvnne r7, #0275; CHECK-NEXT:    vdup.32 d23, r7276; CHECK-NEXT:    vdup.32 d22, r3277; CHECK-NEXT:    vbsl q11, q4, q9278; CHECK-NEXT:    vmovn.i64 d1, q11279; CHECK-NEXT:    rsbs r1, r1, #-2147483648280; CHECK-NEXT:    sbcs r1, r0, r2281; CHECK-NEXT:    mov r1, #0282; CHECK-NEXT:    movwlt r1, #1283; CHECK-NEXT:    cmp r1, #0284; CHECK-NEXT:    mvnne r1, #0285; CHECK-NEXT:    rsbs r2, r6, #-2147483648286; CHECK-NEXT:    sbcs r0, r0, r5287; CHECK-NEXT:    vdup.32 d21, r1288; CHECK-NEXT:    movwlt r4, #1289; CHECK-NEXT:    cmp r4, #0290; CHECK-NEXT:    mvnne r4, #0291; CHECK-NEXT:    vdup.32 d20, r4292; CHECK-NEXT:    vbif q8, q9, q10293; CHECK-NEXT:    vmovn.i64 d0, q8294; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}295; CHECK-NEXT:    add sp, sp, #4296; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}297; CHECK-NEXT:    .p2align 4298; CHECK-NEXT:  @ %bb.1:299; CHECK-NEXT:  .LCPI3_0:300; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff301; CHECK-NEXT:    .long 0 @ 0x0302; CHECK-NEXT:    .long 2147483647 @ 0x7fffffff303; CHECK-NEXT:    .long 0 @ 0x0304; CHECK-NEXT:  .LCPI3_1:305; CHECK-NEXT:    .long 2147483648 @ 0x80000000306; CHECK-NEXT:    .long 4294967295 @ 0xffffffff307; CHECK-NEXT:    .long 2147483648 @ 0x80000000308; CHECK-NEXT:    .long 4294967295 @ 0xffffffff309entry:310  %conv = fptosi <4 x float> %x to <4 x i64>311  %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>312  %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>313  %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>314  %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>315  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>316  ret <4 x i32> %conv6317}318 319define <4 x i32> @utest_f32i32(<4 x float> %x) {320; CHECK-LABEL: utest_f32i32:321; CHECK:       @ %bb.0: @ %entry322; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}323; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}324; CHECK-NEXT:    .vsave {d8, d9, d10, d11}325; CHECK-NEXT:    vpush {d8, d9, d10, d11}326; CHECK-NEXT:    vorr q4, q0, q0327; CHECK-NEXT:    vmov r0, s17328; CHECK-NEXT:    bl __aeabi_f2ulz329; CHECK-NEXT:    mov r10, r0330; CHECK-NEXT:    vmov r0, s16331; CHECK-NEXT:    mov r8, r1332; CHECK-NEXT:    vmov r5, s19333; CHECK-NEXT:    vmov r7, s18334; CHECK-NEXT:    vmov.32 d9[0], r10335; CHECK-NEXT:    bl __aeabi_f2ulz336; CHECK-NEXT:    mov r6, r0337; CHECK-NEXT:    vmov.32 d8[0], r0338; CHECK-NEXT:    mov r0, r5339; CHECK-NEXT:    mov r9, r1340; CHECK-NEXT:    bl __aeabi_f2ulz341; CHECK-NEXT:    mov r5, r0342; CHECK-NEXT:    vmov.32 d11[0], r0343; CHECK-NEXT:    mov r0, r7344; CHECK-NEXT:    mov r4, r1345; CHECK-NEXT:    bl __aeabi_f2ulz346; CHECK-NEXT:    mvn r3, #0347; CHECK-NEXT:    vmov.32 d10[0], r0348; CHECK-NEXT:    subs r0, r0, r3349; CHECK-NEXT:    mov r2, #0350; CHECK-NEXT:    sbcs r0, r1, #0351; CHECK-NEXT:    mov r0, #0352; CHECK-NEXT:    movwlo r0, #1353; CHECK-NEXT:    cmp r0, #0354; CHECK-NEXT:    mvnne r0, #0355; CHECK-NEXT:    subs r1, r5, r3356; CHECK-NEXT:    sbcs r1, r4, #0357; CHECK-NEXT:    mov r1, #0358; CHECK-NEXT:    movwlo r1, #1359; CHECK-NEXT:    cmp r1, #0360; CHECK-NEXT:    mvnne r1, #0361; CHECK-NEXT:    subs r7, r10, r3362; CHECK-NEXT:    sbcs r7, r8, #0363; CHECK-NEXT:    vdup.32 d19, r1364; CHECK-NEXT:    mov r7, #0365; CHECK-NEXT:    vdup.32 d18, r0366; CHECK-NEXT:    movwlo r7, #1367; CHECK-NEXT:    cmp r7, #0368; CHECK-NEXT:    mvnne r7, #0369; CHECK-NEXT:    subs r3, r6, r3370; CHECK-NEXT:    sbcs r3, r9, #0371; CHECK-NEXT:    vdup.32 d17, r7372; CHECK-NEXT:    movwlo r2, #1373; CHECK-NEXT:    cmp r2, #0374; CHECK-NEXT:    mvnne r2, #0375; CHECK-NEXT:    vand q10, q5, q9376; CHECK-NEXT:    vdup.32 d16, r2377; CHECK-NEXT:    vand q11, q4, q8378; CHECK-NEXT:    vorn q9, q10, q9379; CHECK-NEXT:    vorn q8, q11, q8380; CHECK-NEXT:    vmovn.i64 d1, q9381; CHECK-NEXT:    vmovn.i64 d0, q8382; CHECK-NEXT:    vpop {d8, d9, d10, d11}383; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}384entry:385  %conv = fptoui <4 x float> %x to <4 x i64>386  %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>387  %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>388  %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>389  ret <4 x i32> %conv6390}391 392define <4 x i32> @ustest_f32i32(<4 x float> %x) {393; CHECK-LABEL: ustest_f32i32:394; CHECK:       @ %bb.0: @ %entry395; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}396; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}397; CHECK-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}398; CHECK-NEXT:    vpush {d8, d9, d10, d11, d12, d13}399; CHECK-NEXT:    vorr q4, q0, q0400; CHECK-NEXT:    vmov r0, s19401; CHECK-NEXT:    bl __aeabi_f2lz402; CHECK-NEXT:    mov r6, r0403; CHECK-NEXT:    vmov r0, s18404; CHECK-NEXT:    mov r7, r1405; CHECK-NEXT:    vmov r5, s17406; CHECK-NEXT:    vmov r8, s16407; CHECK-NEXT:    vmov.32 d9[0], r6408; CHECK-NEXT:    bl __aeabi_f2lz409; CHECK-NEXT:    mvn r9, #0410; CHECK-NEXT:    subs r2, r6, r9411; CHECK-NEXT:    sbcs r2, r7, #0412; CHECK-NEXT:    vmov.32 d8[0], r0413; CHECK-NEXT:    mov r2, #0414; CHECK-NEXT:    vmov.i64 q5, #0xffffffff415; CHECK-NEXT:    movwlt r2, #1416; CHECK-NEXT:    cmp r2, #0417; CHECK-NEXT:    mvnne r2, #0418; CHECK-NEXT:    subs r0, r0, r9419; CHECK-NEXT:    sbcs r0, r1, #0420; CHECK-NEXT:    vmov.32 d9[1], r7421; CHECK-NEXT:    mov r0, #0422; CHECK-NEXT:    mov r4, #0423; CHECK-NEXT:    movwlt r0, #1424; CHECK-NEXT:    cmp r0, #0425; CHECK-NEXT:    vmov.32 d8[1], r1426; CHECK-NEXT:    mvnne r0, #0427; CHECK-NEXT:    vdup.32 d17, r2428; CHECK-NEXT:    vdup.32 d16, r0429; CHECK-NEXT:    mov r0, r5430; CHECK-NEXT:    vbif q4, q5, q8431; CHECK-NEXT:    bl __aeabi_f2lz432; CHECK-NEXT:    mov r5, r0433; CHECK-NEXT:    vmov.32 d13[0], r0434; CHECK-NEXT:    mov r0, r8435; CHECK-NEXT:    mov r6, r1436; CHECK-NEXT:    vmov r7, r10, d8437; CHECK-NEXT:    bl __aeabi_f2lz438; CHECK-NEXT:    subs r2, r5, r9439; CHECK-NEXT:    vmov.32 d12[0], r0440; CHECK-NEXT:    sbcs r2, r6, #0441; CHECK-NEXT:    mov r2, #0442; CHECK-NEXT:    vmov.32 d13[1], r6443; CHECK-NEXT:    movwlt r2, #1444; CHECK-NEXT:    cmp r2, #0445; CHECK-NEXT:    mvnne r2, #0446; CHECK-NEXT:    subs r0, r0, r9447; CHECK-NEXT:    sbcs r0, r1, #0448; CHECK-NEXT:    vdup.32 d17, r2449; CHECK-NEXT:    mov r0, #0450; CHECK-NEXT:    vmov.32 d12[1], r1451; CHECK-NEXT:    movwlt r0, #1452; CHECK-NEXT:    cmp r0, #0453; CHECK-NEXT:    mvnne r0, #0454; CHECK-NEXT:    vmov r2, r3, d9455; CHECK-NEXT:    vdup.32 d16, r0456; CHECK-NEXT:    rsbs r7, r7, #0457; CHECK-NEXT:    vbsl q8, q6, q5458; CHECK-NEXT:    rscs r7, r10, #0459; CHECK-NEXT:    mov r7, #0460; CHECK-NEXT:    movwlt r7, #1461; CHECK-NEXT:    cmp r7, #0462; CHECK-NEXT:    vmov r0, r1, d17463; CHECK-NEXT:    mvnne r7, #0464; CHECK-NEXT:    vmov r6, r5, d16465; CHECK-NEXT:    rsbs r0, r0, #0466; CHECK-NEXT:    rscs r0, r1, #0467; CHECK-NEXT:    mov r0, #0468; CHECK-NEXT:    movwlt r0, #1469; CHECK-NEXT:    cmp r0, #0470; CHECK-NEXT:    mvnne r0, #0471; CHECK-NEXT:    rsbs r1, r2, #0472; CHECK-NEXT:    rscs r1, r3, #0473; CHECK-NEXT:    vmov.32 d19[0], r0474; CHECK-NEXT:    mov r1, #0475; CHECK-NEXT:    movwlt r1, #1476; CHECK-NEXT:    cmp r1, #0477; CHECK-NEXT:    mvnne r1, #0478; CHECK-NEXT:    rsbs r0, r6, #0479; CHECK-NEXT:    rscs r0, r5, #0480; CHECK-NEXT:    vmov.32 d21[0], r1481; CHECK-NEXT:    movwlt r4, #1482; CHECK-NEXT:    cmp r4, #0483; CHECK-NEXT:    vmov.32 d20[0], r7484; CHECK-NEXT:    mvnne r4, #0485; CHECK-NEXT:    vmov.32 d18[0], r4486; CHECK-NEXT:    vand q10, q10, q4487; CHECK-NEXT:    vand q8, q9, q8488; CHECK-NEXT:    vmovn.i64 d1, q10489; CHECK-NEXT:    vmovn.i64 d0, q8490; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13}491; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}492entry:493  %conv = fptosi <4 x float> %x to <4 x i64>494  %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>495  %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>496  %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer497  %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer498  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>499  ret <4 x i32> %conv6500}501 502define <4 x i32> @stest_f16i32(<4 x half> %x) {503; CHECK-NEON-LABEL: stest_f16i32:504; CHECK-NEON:       @ %bb.0: @ %entry505; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}506; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}507; CHECK-NEON-NEXT:    .pad #4508; CHECK-NEON-NEXT:    sub sp, sp, #4509; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}510; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}511; CHECK-NEON-NEXT:    vmov r0, s2512; CHECK-NEON-NEXT:    vmov.f32 s16, s3513; CHECK-NEON-NEXT:    vmov.f32 s18, s1514; CHECK-NEON-NEXT:    vmov.f32 s20, s0515; CHECK-NEON-NEXT:    bl __aeabi_h2f516; CHECK-NEON-NEXT:    bl __aeabi_f2lz517; CHECK-NEON-NEXT:    mov r6, r0518; CHECK-NEON-NEXT:    vmov r0, s16519; CHECK-NEON-NEXT:    mov r5, r1520; CHECK-NEON-NEXT:    bl __aeabi_h2f521; CHECK-NEON-NEXT:    bl __aeabi_f2lz522; CHECK-NEON-NEXT:    vmov r2, s18523; CHECK-NEON-NEXT:    adr r3, .LCPI6_0524; CHECK-NEON-NEXT:    vld1.64 {d8, d9}, [r3:128]525; CHECK-NEON-NEXT:    mvn r9, #-2147483648526; CHECK-NEON-NEXT:    subs r3, r6, r9527; CHECK-NEON-NEXT:    mov r4, #0528; CHECK-NEON-NEXT:    sbcs r3, r5, #0529; CHECK-NEON-NEXT:    vmov.32 d15[0], r0530; CHECK-NEON-NEXT:    movwlt r4, #1531; CHECK-NEON-NEXT:    cmp r4, #0532; CHECK-NEON-NEXT:    mvnne r4, #0533; CHECK-NEON-NEXT:    subs r0, r0, r9534; CHECK-NEON-NEXT:    sbcs r0, r1, #0535; CHECK-NEON-NEXT:    vmov.32 d14[0], r6536; CHECK-NEON-NEXT:    mov r0, #0537; CHECK-NEON-NEXT:    vmov r8, s20538; CHECK-NEON-NEXT:    movwlt r0, #1539; CHECK-NEON-NEXT:    cmp r0, #0540; CHECK-NEON-NEXT:    mvnne r0, #0541; CHECK-NEON-NEXT:    vmov.32 d15[1], r1542; CHECK-NEON-NEXT:    mov r7, #0543; CHECK-NEON-NEXT:    vdup.32 d11, r0544; CHECK-NEON-NEXT:    vmov.32 d14[1], r5545; CHECK-NEON-NEXT:    mov r0, r2546; CHECK-NEON-NEXT:    bl __aeabi_h2f547; CHECK-NEON-NEXT:    vdup.32 d10, r4548; CHECK-NEON-NEXT:    bl __aeabi_f2lz549; CHECK-NEON-NEXT:    vmov.32 d13[0], r0550; CHECK-NEON-NEXT:    subs r0, r0, r9551; CHECK-NEON-NEXT:    vbsl q5, q7, q4552; CHECK-NEON-NEXT:    sbcs r0, r1, #0553; CHECK-NEON-NEXT:    mov r6, #0554; CHECK-NEON-NEXT:    mov r0, r8555; CHECK-NEON-NEXT:    movwlt r6, #1556; CHECK-NEON-NEXT:    cmp r6, #0557; CHECK-NEON-NEXT:    vmov r11, r10, d10558; CHECK-NEON-NEXT:    vmov.32 d13[1], r1559; CHECK-NEON-NEXT:    mvnne r6, #0560; CHECK-NEON-NEXT:    vmov r5, r4, d11561; CHECK-NEON-NEXT:    bl __aeabi_h2f562; CHECK-NEON-NEXT:    bl __aeabi_f2lz563; CHECK-NEON-NEXT:    vmov.32 d12[0], r0564; CHECK-NEON-NEXT:    subs r0, r0, r9565; CHECK-NEON-NEXT:    sbcs r0, r1, #0566; CHECK-NEON-NEXT:    mov r0, #0567; CHECK-NEON-NEXT:    vdup.32 d17, r6568; CHECK-NEON-NEXT:    movwlt r0, #1569; CHECK-NEON-NEXT:    cmp r0, #0570; CHECK-NEON-NEXT:    mvnne r0, #0571; CHECK-NEON-NEXT:    vmov.32 d12[1], r1572; CHECK-NEON-NEXT:    rsbs r3, r11, #-2147483648573; CHECK-NEON-NEXT:    vdup.32 d16, r0574; CHECK-NEON-NEXT:    mvn r0, #0575; CHECK-NEON-NEXT:    vbsl q8, q6, q4576; CHECK-NEON-NEXT:    adr r1, .LCPI6_1577; CHECK-NEON-NEXT:    vld1.64 {d18, d19}, [r1:128]578; CHECK-NEON-NEXT:    sbcs r3, r0, r10579; CHECK-NEON-NEXT:    mov r3, #0580; CHECK-NEON-NEXT:    vmov r1, r2, d17581; CHECK-NEON-NEXT:    movwlt r3, #1582; CHECK-NEON-NEXT:    cmp r3, #0583; CHECK-NEON-NEXT:    mvnne r3, #0584; CHECK-NEON-NEXT:    rsbs r6, r5, #-2147483648585; CHECK-NEON-NEXT:    sbcs r6, r0, r4586; CHECK-NEON-NEXT:    vmov r5, r4, d16587; CHECK-NEON-NEXT:    mov r6, #0588; CHECK-NEON-NEXT:    movwlt r6, #1589; CHECK-NEON-NEXT:    cmp r6, #0590; CHECK-NEON-NEXT:    mvnne r6, #0591; CHECK-NEON-NEXT:    vdup.32 d23, r6592; CHECK-NEON-NEXT:    vdup.32 d22, r3593; CHECK-NEON-NEXT:    vbsl q11, q5, q9594; CHECK-NEON-NEXT:    vmovn.i64 d1, q11595; CHECK-NEON-NEXT:    rsbs r1, r1, #-2147483648596; CHECK-NEON-NEXT:    sbcs r1, r0, r2597; CHECK-NEON-NEXT:    mov r1, #0598; CHECK-NEON-NEXT:    movwlt r1, #1599; CHECK-NEON-NEXT:    cmp r1, #0600; CHECK-NEON-NEXT:    mvnne r1, #0601; CHECK-NEON-NEXT:    rsbs r2, r5, #-2147483648602; CHECK-NEON-NEXT:    sbcs r0, r0, r4603; CHECK-NEON-NEXT:    vdup.32 d21, r1604; CHECK-NEON-NEXT:    movwlt r7, #1605; CHECK-NEON-NEXT:    cmp r7, #0606; CHECK-NEON-NEXT:    mvnne r7, #0607; CHECK-NEON-NEXT:    vdup.32 d20, r7608; CHECK-NEON-NEXT:    vbif q8, q9, q10609; CHECK-NEON-NEXT:    vmovn.i64 d0, q8610; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}611; CHECK-NEON-NEXT:    add sp, sp, #4612; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}613; CHECK-NEON-NEXT:    .p2align 4614; CHECK-NEON-NEXT:  @ %bb.1:615; CHECK-NEON-NEXT:  .LCPI6_0:616; CHECK-NEON-NEXT:    .long 2147483647 @ 0x7fffffff617; CHECK-NEON-NEXT:    .long 0 @ 0x0618; CHECK-NEON-NEXT:    .long 2147483647 @ 0x7fffffff619; CHECK-NEON-NEXT:    .long 0 @ 0x0620; CHECK-NEON-NEXT:  .LCPI6_1:621; CHECK-NEON-NEXT:    .long 2147483648 @ 0x80000000622; CHECK-NEON-NEXT:    .long 4294967295 @ 0xffffffff623; CHECK-NEON-NEXT:    .long 2147483648 @ 0x80000000624; CHECK-NEON-NEXT:    .long 4294967295 @ 0xffffffff625;626; CHECK-FP16-LABEL: stest_f16i32:627; CHECK-FP16:       @ %bb.0: @ %entry628; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}629; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}630; CHECK-FP16-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}631; CHECK-FP16-NEXT:    vpush {d8, d9, d10, d11, d12, d13}632; CHECK-FP16-NEXT:    vmov.u16 r0, d0[3]633; CHECK-FP16-NEXT:    vorr d8, d0, d0634; CHECK-FP16-NEXT:    vmov.u16 r8, d0[0]635; CHECK-FP16-NEXT:    vmov.u16 r9, d0[1]636; CHECK-FP16-NEXT:    vmov s0, r0637; CHECK-FP16-NEXT:    bl __fixhfdi638; CHECK-FP16-NEXT:    mov r4, r0639; CHECK-FP16-NEXT:    vmov.u16 r0, d8[2]640; CHECK-FP16-NEXT:    mov r5, r1641; CHECK-FP16-NEXT:    vmov.32 d9[0], r4642; CHECK-FP16-NEXT:    vmov s0, r0643; CHECK-FP16-NEXT:    bl __fixhfdi644; CHECK-FP16-NEXT:    adr r2, .LCPI6_0645; CHECK-FP16-NEXT:    mvn r10, #-2147483648646; CHECK-FP16-NEXT:    vld1.64 {d10, d11}, [r2:128]647; CHECK-FP16-NEXT:    subs r2, r4, r10648; CHECK-FP16-NEXT:    sbcs r2, r5, #0649; CHECK-FP16-NEXT:    vmov s0, r9650; CHECK-FP16-NEXT:    mov r2, #0651; CHECK-FP16-NEXT:    vmov.32 d8[0], r0652; CHECK-FP16-NEXT:    movwlt r2, #1653; CHECK-FP16-NEXT:    cmp r2, #0654; CHECK-FP16-NEXT:    mvnne r2, #0655; CHECK-FP16-NEXT:    subs r0, r0, r10656; CHECK-FP16-NEXT:    sbcs r0, r1, #0657; CHECK-FP16-NEXT:    vmov.32 d9[1], r5658; CHECK-FP16-NEXT:    mov r0, #0659; CHECK-FP16-NEXT:    mov r6, #0660; CHECK-FP16-NEXT:    movwlt r0, #1661; CHECK-FP16-NEXT:    cmp r0, #0662; CHECK-FP16-NEXT:    vmov.32 d8[1], r1663; CHECK-FP16-NEXT:    mvnne r0, #0664; CHECK-FP16-NEXT:    vdup.32 d17, r2665; CHECK-FP16-NEXT:    vdup.32 d16, r0666; CHECK-FP16-NEXT:    vbif q4, q5, q8667; CHECK-FP16-NEXT:    bl __fixhfdi668; CHECK-FP16-NEXT:    vmov.32 d13[0], r0669; CHECK-FP16-NEXT:    subs r0, r0, r10670; CHECK-FP16-NEXT:    vmov s0, r8671; CHECK-FP16-NEXT:    sbcs r0, r1, #0672; CHECK-FP16-NEXT:    mov r7, #0673; CHECK-FP16-NEXT:    vmov r9, r8, d8674; CHECK-FP16-NEXT:    movwlt r7, #1675; CHECK-FP16-NEXT:    cmp r7, #0676; CHECK-FP16-NEXT:    vmov.32 d13[1], r1677; CHECK-FP16-NEXT:    vmov r5, r4, d9678; CHECK-FP16-NEXT:    mvnne r7, #0679; CHECK-FP16-NEXT:    bl __fixhfdi680; CHECK-FP16-NEXT:    vmov.32 d12[0], r0681; CHECK-FP16-NEXT:    subs r0, r0, r10682; CHECK-FP16-NEXT:    sbcs r0, r1, #0683; CHECK-FP16-NEXT:    mov r0, #0684; CHECK-FP16-NEXT:    vdup.32 d17, r7685; CHECK-FP16-NEXT:    movwlt r0, #1686; CHECK-FP16-NEXT:    cmp r0, #0687; CHECK-FP16-NEXT:    mvnne r0, #0688; CHECK-FP16-NEXT:    vmov.32 d12[1], r1689; CHECK-FP16-NEXT:    rsbs r3, r9, #-2147483648690; CHECK-FP16-NEXT:    vdup.32 d16, r0691; CHECK-FP16-NEXT:    mvn r0, #0692; CHECK-FP16-NEXT:    vbsl q8, q6, q5693; CHECK-FP16-NEXT:    adr r1, .LCPI6_1694; CHECK-FP16-NEXT:    vld1.64 {d18, d19}, [r1:128]695; CHECK-FP16-NEXT:    sbcs r3, r0, r8696; CHECK-FP16-NEXT:    mov r3, #0697; CHECK-FP16-NEXT:    vmov r1, r2, d17698; CHECK-FP16-NEXT:    movwlt r3, #1699; CHECK-FP16-NEXT:    cmp r3, #0700; CHECK-FP16-NEXT:    mvnne r3, #0701; CHECK-FP16-NEXT:    rsbs r7, r5, #-2147483648702; CHECK-FP16-NEXT:    sbcs r7, r0, r4703; CHECK-FP16-NEXT:    vmov r5, r4, d16704; CHECK-FP16-NEXT:    mov r7, #0705; CHECK-FP16-NEXT:    movwlt r7, #1706; CHECK-FP16-NEXT:    cmp r7, #0707; CHECK-FP16-NEXT:    mvnne r7, #0708; CHECK-FP16-NEXT:    vdup.32 d23, r7709; CHECK-FP16-NEXT:    vdup.32 d22, r3710; CHECK-FP16-NEXT:    vbsl q11, q4, q9711; CHECK-FP16-NEXT:    vmovn.i64 d1, q11712; CHECK-FP16-NEXT:    rsbs r1, r1, #-2147483648713; CHECK-FP16-NEXT:    sbcs r1, r0, r2714; CHECK-FP16-NEXT:    mov r1, #0715; CHECK-FP16-NEXT:    movwlt r1, #1716; CHECK-FP16-NEXT:    cmp r1, #0717; CHECK-FP16-NEXT:    mvnne r1, #0718; CHECK-FP16-NEXT:    rsbs r2, r5, #-2147483648719; CHECK-FP16-NEXT:    sbcs r0, r0, r4720; CHECK-FP16-NEXT:    vdup.32 d21, r1721; CHECK-FP16-NEXT:    movwlt r6, #1722; CHECK-FP16-NEXT:    cmp r6, #0723; CHECK-FP16-NEXT:    mvnne r6, #0724; CHECK-FP16-NEXT:    vdup.32 d20, r6725; CHECK-FP16-NEXT:    vbif q8, q9, q10726; CHECK-FP16-NEXT:    vmovn.i64 d0, q8727; CHECK-FP16-NEXT:    vpop {d8, d9, d10, d11, d12, d13}728; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}729; CHECK-FP16-NEXT:    .p2align 4730; CHECK-FP16-NEXT:  @ %bb.1:731; CHECK-FP16-NEXT:  .LCPI6_0:732; CHECK-FP16-NEXT:    .long 2147483647 @ 0x7fffffff733; CHECK-FP16-NEXT:    .long 0 @ 0x0734; CHECK-FP16-NEXT:    .long 2147483647 @ 0x7fffffff735; CHECK-FP16-NEXT:    .long 0 @ 0x0736; CHECK-FP16-NEXT:  .LCPI6_1:737; CHECK-FP16-NEXT:    .long 2147483648 @ 0x80000000738; CHECK-FP16-NEXT:    .long 4294967295 @ 0xffffffff739; CHECK-FP16-NEXT:    .long 2147483648 @ 0x80000000740; CHECK-FP16-NEXT:    .long 4294967295 @ 0xffffffff741entry:742  %conv = fptosi <4 x half> %x to <4 x i64>743  %0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>744  %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>745  %1 = icmp sgt <4 x i64> %spec.store.select, <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>746  %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>747  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>748  ret <4 x i32> %conv6749}750 751define <4 x i32> @utest_f16i32(<4 x half> %x) {752; CHECK-NEON-LABEL: utest_f16i32:753; CHECK-NEON:       @ %bb.0: @ %entry754; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, r9, r11, lr}755; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, r9, r11, lr}756; CHECK-NEON-NEXT:    .vsave {d12, d13}757; CHECK-NEON-NEXT:    vpush {d12, d13}758; CHECK-NEON-NEXT:    .vsave {d8, d9, d10}759; CHECK-NEON-NEXT:    vpush {d8, d9, d10}760; CHECK-NEON-NEXT:    vmov r0, s3761; CHECK-NEON-NEXT:    vmov.f32 s16, s2762; CHECK-NEON-NEXT:    vmov.f32 s18, s1763; CHECK-NEON-NEXT:    vmov.f32 s20, s0764; CHECK-NEON-NEXT:    bl __aeabi_h2f765; CHECK-NEON-NEXT:    bl __aeabi_f2ulz766; CHECK-NEON-NEXT:    mov r4, r0767; CHECK-NEON-NEXT:    vmov r0, s18768; CHECK-NEON-NEXT:    mov r8, r1769; CHECK-NEON-NEXT:    bl __aeabi_h2f770; CHECK-NEON-NEXT:    bl __aeabi_f2ulz771; CHECK-NEON-NEXT:    mov r6, r0772; CHECK-NEON-NEXT:    vmov.32 d13[0], r0773; CHECK-NEON-NEXT:    vmov r0, s20774; CHECK-NEON-NEXT:    mov r9, r1775; CHECK-NEON-NEXT:    bl __aeabi_h2f776; CHECK-NEON-NEXT:    bl __aeabi_f2ulz777; CHECK-NEON-NEXT:    mov r5, r0778; CHECK-NEON-NEXT:    vmov.32 d12[0], r0779; CHECK-NEON-NEXT:    vmov r0, s16780; CHECK-NEON-NEXT:    mov r7, r1781; CHECK-NEON-NEXT:    bl __aeabi_h2f782; CHECK-NEON-NEXT:    vmov.32 d9[0], r4783; CHECK-NEON-NEXT:    bl __aeabi_f2ulz784; CHECK-NEON-NEXT:    mvn r3, #0785; CHECK-NEON-NEXT:    vmov.32 d8[0], r0786; CHECK-NEON-NEXT:    subs r0, r0, r3787; CHECK-NEON-NEXT:    mov r2, #0788; CHECK-NEON-NEXT:    sbcs r0, r1, #0789; CHECK-NEON-NEXT:    mov r0, #0790; CHECK-NEON-NEXT:    movwlo r0, #1791; CHECK-NEON-NEXT:    cmp r0, #0792; CHECK-NEON-NEXT:    mvnne r0, #0793; CHECK-NEON-NEXT:    subs r1, r4, r3794; CHECK-NEON-NEXT:    sbcs r1, r8, #0795; CHECK-NEON-NEXT:    mov r1, #0796; CHECK-NEON-NEXT:    movwlo r1, #1797; CHECK-NEON-NEXT:    cmp r1, #0798; CHECK-NEON-NEXT:    mvnne r1, #0799; CHECK-NEON-NEXT:    subs r6, r6, r3800; CHECK-NEON-NEXT:    sbcs r6, r9, #0801; CHECK-NEON-NEXT:    vdup.32 d19, r1802; CHECK-NEON-NEXT:    mov r6, #0803; CHECK-NEON-NEXT:    vdup.32 d18, r0804; CHECK-NEON-NEXT:    movwlo r6, #1805; CHECK-NEON-NEXT:    cmp r6, #0806; CHECK-NEON-NEXT:    mvnne r6, #0807; CHECK-NEON-NEXT:    subs r3, r5, r3808; CHECK-NEON-NEXT:    sbcs r3, r7, #0809; CHECK-NEON-NEXT:    vdup.32 d17, r6810; CHECK-NEON-NEXT:    movwlo r2, #1811; CHECK-NEON-NEXT:    cmp r2, #0812; CHECK-NEON-NEXT:    mvnne r2, #0813; CHECK-NEON-NEXT:    vand q10, q4, q9814; CHECK-NEON-NEXT:    vdup.32 d16, r2815; CHECK-NEON-NEXT:    vand q11, q6, q8816; CHECK-NEON-NEXT:    vorn q9, q10, q9817; CHECK-NEON-NEXT:    vorn q8, q11, q8818; CHECK-NEON-NEXT:    vmovn.i64 d1, q9819; CHECK-NEON-NEXT:    vmovn.i64 d0, q8820; CHECK-NEON-NEXT:    vpop {d8, d9, d10}821; CHECK-NEON-NEXT:    vpop {d12, d13}822; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, r9, r11, pc}823;824; CHECK-FP16-LABEL: utest_f16i32:825; CHECK-FP16:       @ %bb.0: @ %entry826; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, r9, r11, lr}827; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, r9, r11, lr}828; CHECK-FP16-NEXT:    .vsave {d8, d9, d10, d11}829; CHECK-FP16-NEXT:    vpush {d8, d9, d10, d11}830; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]831; CHECK-FP16-NEXT:    vorr d8, d0, d0832; CHECK-FP16-NEXT:    vmov.u16 r5, d0[3]833; CHECK-FP16-NEXT:    vmov s0, r0834; CHECK-FP16-NEXT:    bl __fixunshfdi835; CHECK-FP16-NEXT:    mov r4, r0836; CHECK-FP16-NEXT:    vmov.u16 r0, d8[0]837; CHECK-FP16-NEXT:    mov r8, r1838; CHECK-FP16-NEXT:    vmov.32 d11[0], r4839; CHECK-FP16-NEXT:    vmov s0, r0840; CHECK-FP16-NEXT:    bl __fixunshfdi841; CHECK-FP16-NEXT:    vmov s0, r5842; CHECK-FP16-NEXT:    mov r6, r0843; CHECK-FP16-NEXT:    mov r9, r1844; CHECK-FP16-NEXT:    vmov.32 d10[0], r0845; CHECK-FP16-NEXT:    bl __fixunshfdi846; CHECK-FP16-NEXT:    mov r5, r0847; CHECK-FP16-NEXT:    vmov.u16 r0, d8[2]848; CHECK-FP16-NEXT:    mov r7, r1849; CHECK-FP16-NEXT:    vmov.32 d9[0], r5850; CHECK-FP16-NEXT:    vmov s0, r0851; CHECK-FP16-NEXT:    bl __fixunshfdi852; CHECK-FP16-NEXT:    mvn r3, #0853; CHECK-FP16-NEXT:    vmov.32 d8[0], r0854; CHECK-FP16-NEXT:    subs r0, r0, r3855; CHECK-FP16-NEXT:    mov r2, #0856; CHECK-FP16-NEXT:    sbcs r0, r1, #0857; CHECK-FP16-NEXT:    mov r0, #0858; CHECK-FP16-NEXT:    movwlo r0, #1859; CHECK-FP16-NEXT:    cmp r0, #0860; CHECK-FP16-NEXT:    mvnne r0, #0861; CHECK-FP16-NEXT:    subs r1, r5, r3862; CHECK-FP16-NEXT:    sbcs r1, r7, #0863; CHECK-FP16-NEXT:    mov r1, #0864; CHECK-FP16-NEXT:    movwlo r1, #1865; CHECK-FP16-NEXT:    cmp r1, #0866; CHECK-FP16-NEXT:    mvnne r1, #0867; CHECK-FP16-NEXT:    subs r7, r4, r3868; CHECK-FP16-NEXT:    sbcs r7, r8, #0869; CHECK-FP16-NEXT:    vdup.32 d19, r1870; CHECK-FP16-NEXT:    mov r7, #0871; CHECK-FP16-NEXT:    vdup.32 d18, r0872; CHECK-FP16-NEXT:    movwlo r7, #1873; CHECK-FP16-NEXT:    cmp r7, #0874; CHECK-FP16-NEXT:    mvnne r7, #0875; CHECK-FP16-NEXT:    subs r3, r6, r3876; CHECK-FP16-NEXT:    sbcs r3, r9, #0877; CHECK-FP16-NEXT:    vdup.32 d17, r7878; CHECK-FP16-NEXT:    movwlo r2, #1879; CHECK-FP16-NEXT:    cmp r2, #0880; CHECK-FP16-NEXT:    mvnne r2, #0881; CHECK-FP16-NEXT:    vand q10, q4, q9882; CHECK-FP16-NEXT:    vdup.32 d16, r2883; CHECK-FP16-NEXT:    vand q11, q5, q8884; CHECK-FP16-NEXT:    vorn q9, q10, q9885; CHECK-FP16-NEXT:    vorn q8, q11, q8886; CHECK-FP16-NEXT:    vmovn.i64 d1, q9887; CHECK-FP16-NEXT:    vmovn.i64 d0, q8888; CHECK-FP16-NEXT:    vpop {d8, d9, d10, d11}889; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, r9, r11, pc}890entry:891  %conv = fptoui <4 x half> %x to <4 x i64>892  %0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>893  %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>894  %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>895  ret <4 x i32> %conv6896}897 898define <4 x i32> @ustest_f16i32(<4 x half> %x) {899; CHECK-NEON-LABEL: ustest_f16i32:900; CHECK-NEON:       @ %bb.0: @ %entry901; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}902; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}903; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}904; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13}905; CHECK-NEON-NEXT:    vmov r0, s3906; CHECK-NEON-NEXT:    vmov.f32 s16, s2907; CHECK-NEON-NEXT:    vmov.f32 s18, s1908; CHECK-NEON-NEXT:    vmov.f32 s20, s0909; CHECK-NEON-NEXT:    bl __aeabi_h2f910; CHECK-NEON-NEXT:    bl __aeabi_f2lz911; CHECK-NEON-NEXT:    mov r5, r0912; CHECK-NEON-NEXT:    vmov r0, s16913; CHECK-NEON-NEXT:    mov r6, r1914; CHECK-NEON-NEXT:    bl __aeabi_h2f915; CHECK-NEON-NEXT:    vmov r8, s20916; CHECK-NEON-NEXT:    vmov.32 d13[0], r5917; CHECK-NEON-NEXT:    bl __aeabi_f2lz918; CHECK-NEON-NEXT:    vmov r2, s18919; CHECK-NEON-NEXT:    vmov.32 d12[0], r0920; CHECK-NEON-NEXT:    mvn r9, #0921; CHECK-NEON-NEXT:    subs r0, r0, r9922; CHECK-NEON-NEXT:    sbcs r0, r1, #0923; CHECK-NEON-NEXT:    vmov.32 d13[1], r6924; CHECK-NEON-NEXT:    mov r0, #0925; CHECK-NEON-NEXT:    mov r7, #0926; CHECK-NEON-NEXT:    movwlt r0, #1927; CHECK-NEON-NEXT:    cmp r0, #0928; CHECK-NEON-NEXT:    vmov.32 d12[1], r1929; CHECK-NEON-NEXT:    mvnne r0, #0930; CHECK-NEON-NEXT:    subs r1, r5, r9931; CHECK-NEON-NEXT:    sbcs r1, r6, #0932; CHECK-NEON-NEXT:    mov r1, #0933; CHECK-NEON-NEXT:    movwlt r1, #1934; CHECK-NEON-NEXT:    cmp r1, #0935; CHECK-NEON-NEXT:    mvnne r1, #0936; CHECK-NEON-NEXT:    vdup.32 d9, r1937; CHECK-NEON-NEXT:    vdup.32 d8, r0938; CHECK-NEON-NEXT:    mov r0, r2939; CHECK-NEON-NEXT:    bl __aeabi_h2f940; CHECK-NEON-NEXT:    vmov.i64 q5, #0xffffffff941; CHECK-NEON-NEXT:    vbsl q4, q6, q5942; CHECK-NEON-NEXT:    bl __aeabi_f2lz943; CHECK-NEON-NEXT:    mov r5, r0944; CHECK-NEON-NEXT:    vmov.32 d13[0], r0945; CHECK-NEON-NEXT:    mov r0, r8946; CHECK-NEON-NEXT:    mov r6, r1947; CHECK-NEON-NEXT:    vmov r4, r10, d8948; CHECK-NEON-NEXT:    bl __aeabi_h2f949; CHECK-NEON-NEXT:    bl __aeabi_f2lz950; CHECK-NEON-NEXT:    subs r2, r5, r9951; CHECK-NEON-NEXT:    vmov.32 d12[0], r0952; CHECK-NEON-NEXT:    sbcs r2, r6, #0953; CHECK-NEON-NEXT:    mov r2, #0954; CHECK-NEON-NEXT:    vmov.32 d13[1], r6955; CHECK-NEON-NEXT:    movwlt r2, #1956; CHECK-NEON-NEXT:    cmp r2, #0957; CHECK-NEON-NEXT:    mvnne r2, #0958; CHECK-NEON-NEXT:    subs r0, r0, r9959; CHECK-NEON-NEXT:    sbcs r0, r1, #0960; CHECK-NEON-NEXT:    vdup.32 d17, r2961; CHECK-NEON-NEXT:    mov r0, #0962; CHECK-NEON-NEXT:    vmov.32 d12[1], r1963; CHECK-NEON-NEXT:    movwlt r0, #1964; CHECK-NEON-NEXT:    cmp r0, #0965; CHECK-NEON-NEXT:    mvnne r0, #0966; CHECK-NEON-NEXT:    vmov r2, r3, d9967; CHECK-NEON-NEXT:    vdup.32 d16, r0968; CHECK-NEON-NEXT:    rsbs r6, r4, #0969; CHECK-NEON-NEXT:    vbsl q8, q6, q5970; CHECK-NEON-NEXT:    rscs r6, r10, #0971; CHECK-NEON-NEXT:    mov r6, #0972; CHECK-NEON-NEXT:    movwlt r6, #1973; CHECK-NEON-NEXT:    cmp r6, #0974; CHECK-NEON-NEXT:    vmov r0, r1, d17975; CHECK-NEON-NEXT:    mvnne r6, #0976; CHECK-NEON-NEXT:    vmov r5, r4, d16977; CHECK-NEON-NEXT:    rsbs r0, r0, #0978; CHECK-NEON-NEXT:    rscs r0, r1, #0979; CHECK-NEON-NEXT:    mov r0, #0980; CHECK-NEON-NEXT:    movwlt r0, #1981; CHECK-NEON-NEXT:    cmp r0, #0982; CHECK-NEON-NEXT:    mvnne r0, #0983; CHECK-NEON-NEXT:    rsbs r1, r2, #0984; CHECK-NEON-NEXT:    rscs r1, r3, #0985; CHECK-NEON-NEXT:    vmov.32 d19[0], r0986; CHECK-NEON-NEXT:    mov r1, #0987; CHECK-NEON-NEXT:    movwlt r1, #1988; CHECK-NEON-NEXT:    cmp r1, #0989; CHECK-NEON-NEXT:    mvnne r1, #0990; CHECK-NEON-NEXT:    rsbs r0, r5, #0991; CHECK-NEON-NEXT:    rscs r0, r4, #0992; CHECK-NEON-NEXT:    vmov.32 d21[0], r1993; CHECK-NEON-NEXT:    movwlt r7, #1994; CHECK-NEON-NEXT:    cmp r7, #0995; CHECK-NEON-NEXT:    vmov.32 d20[0], r6996; CHECK-NEON-NEXT:    mvnne r7, #0997; CHECK-NEON-NEXT:    vmov.32 d18[0], r7998; CHECK-NEON-NEXT:    vand q10, q10, q4999; CHECK-NEON-NEXT:    vand q8, q9, q81000; CHECK-NEON-NEXT:    vmovn.i64 d1, q101001; CHECK-NEON-NEXT:    vmovn.i64 d0, q81002; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13}1003; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}1004;1005; CHECK-FP16-LABEL: ustest_f16i32:1006; CHECK-FP16:       @ %bb.0: @ %entry1007; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}1008; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}1009; CHECK-FP16-NEXT:    .vsave {d8, d9, d10, d11, d12, d13}1010; CHECK-FP16-NEXT:    vpush {d8, d9, d10, d11, d12, d13}1011; CHECK-FP16-NEXT:    vmov.u16 r0, d0[3]1012; CHECK-FP16-NEXT:    vorr d8, d0, d01013; CHECK-FP16-NEXT:    vmov.u16 r8, d0[0]1014; CHECK-FP16-NEXT:    vmov.u16 r9, d0[1]1015; CHECK-FP16-NEXT:    vmov s0, r01016; CHECK-FP16-NEXT:    bl __fixhfdi1017; CHECK-FP16-NEXT:    mov r4, r01018; CHECK-FP16-NEXT:    vmov.u16 r0, d8[2]1019; CHECK-FP16-NEXT:    mov r5, r11020; CHECK-FP16-NEXT:    vmov.32 d9[0], r41021; CHECK-FP16-NEXT:    vmov s0, r01022; CHECK-FP16-NEXT:    bl __fixhfdi1023; CHECK-FP16-NEXT:    mvn r10, #01024; CHECK-FP16-NEXT:    subs r2, r4, r101025; CHECK-FP16-NEXT:    sbcs r2, r5, #01026; CHECK-FP16-NEXT:    vmov.32 d8[0], r01027; CHECK-FP16-NEXT:    mov r2, #01028; CHECK-FP16-NEXT:    vmov s0, r91029; CHECK-FP16-NEXT:    movwlt r2, #11030; CHECK-FP16-NEXT:    cmp r2, #01031; CHECK-FP16-NEXT:    mvnne r2, #01032; CHECK-FP16-NEXT:    subs r0, r0, r101033; CHECK-FP16-NEXT:    sbcs r0, r1, #01034; CHECK-FP16-NEXT:    vmov.32 d9[1], r51035; CHECK-FP16-NEXT:    mov r0, #01036; CHECK-FP16-NEXT:    vmov.i64 q5, #0xffffffff1037; CHECK-FP16-NEXT:    movwlt r0, #11038; CHECK-FP16-NEXT:    cmp r0, #01039; CHECK-FP16-NEXT:    vmov.32 d8[1], r11040; CHECK-FP16-NEXT:    mvnne r0, #01041; CHECK-FP16-NEXT:    mov r6, #01042; CHECK-FP16-NEXT:    vdup.32 d17, r21043; CHECK-FP16-NEXT:    vdup.32 d16, r01044; CHECK-FP16-NEXT:    vbif q4, q5, q81045; CHECK-FP16-NEXT:    bl __fixhfdi1046; CHECK-FP16-NEXT:    vmov s0, r81047; CHECK-FP16-NEXT:    mov r4, r01048; CHECK-FP16-NEXT:    mov r5, r11049; CHECK-FP16-NEXT:    vmov.32 d13[0], r01050; CHECK-FP16-NEXT:    vmov r7, r8, d81051; CHECK-FP16-NEXT:    bl __fixhfdi1052; CHECK-FP16-NEXT:    subs r2, r4, r101053; CHECK-FP16-NEXT:    vmov.32 d12[0], r01054; CHECK-FP16-NEXT:    sbcs r2, r5, #01055; CHECK-FP16-NEXT:    mov r2, #01056; CHECK-FP16-NEXT:    vmov.32 d13[1], r51057; CHECK-FP16-NEXT:    movwlt r2, #11058; CHECK-FP16-NEXT:    cmp r2, #01059; CHECK-FP16-NEXT:    mvnne r2, #01060; CHECK-FP16-NEXT:    subs r0, r0, r101061; CHECK-FP16-NEXT:    sbcs r0, r1, #01062; CHECK-FP16-NEXT:    vdup.32 d17, r21063; CHECK-FP16-NEXT:    mov r0, #01064; CHECK-FP16-NEXT:    vmov.32 d12[1], r11065; CHECK-FP16-NEXT:    movwlt r0, #11066; CHECK-FP16-NEXT:    cmp r0, #01067; CHECK-FP16-NEXT:    mvnne r0, #01068; CHECK-FP16-NEXT:    vmov r2, r3, d91069; CHECK-FP16-NEXT:    vdup.32 d16, r01070; CHECK-FP16-NEXT:    rsbs r7, r7, #01071; CHECK-FP16-NEXT:    vbsl q8, q6, q51072; CHECK-FP16-NEXT:    rscs r7, r8, #01073; CHECK-FP16-NEXT:    mov r7, #01074; CHECK-FP16-NEXT:    movwlt r7, #11075; CHECK-FP16-NEXT:    cmp r7, #01076; CHECK-FP16-NEXT:    vmov r0, r1, d171077; CHECK-FP16-NEXT:    mvnne r7, #01078; CHECK-FP16-NEXT:    vmov r5, r4, d161079; CHECK-FP16-NEXT:    rsbs r0, r0, #01080; CHECK-FP16-NEXT:    rscs r0, r1, #01081; CHECK-FP16-NEXT:    mov r0, #01082; CHECK-FP16-NEXT:    movwlt r0, #11083; CHECK-FP16-NEXT:    cmp r0, #01084; CHECK-FP16-NEXT:    mvnne r0, #01085; CHECK-FP16-NEXT:    rsbs r1, r2, #01086; CHECK-FP16-NEXT:    rscs r1, r3, #01087; CHECK-FP16-NEXT:    vmov.32 d19[0], r01088; CHECK-FP16-NEXT:    mov r1, #01089; CHECK-FP16-NEXT:    movwlt r1, #11090; CHECK-FP16-NEXT:    cmp r1, #01091; CHECK-FP16-NEXT:    mvnne r1, #01092; CHECK-FP16-NEXT:    rsbs r0, r5, #01093; CHECK-FP16-NEXT:    rscs r0, r4, #01094; CHECK-FP16-NEXT:    vmov.32 d21[0], r11095; CHECK-FP16-NEXT:    movwlt r6, #11096; CHECK-FP16-NEXT:    cmp r6, #01097; CHECK-FP16-NEXT:    vmov.32 d20[0], r71098; CHECK-FP16-NEXT:    mvnne r6, #01099; CHECK-FP16-NEXT:    vmov.32 d18[0], r61100; CHECK-FP16-NEXT:    vand q10, q10, q41101; CHECK-FP16-NEXT:    vand q8, q9, q81102; CHECK-FP16-NEXT:    vmovn.i64 d1, q101103; CHECK-FP16-NEXT:    vmovn.i64 d0, q81104; CHECK-FP16-NEXT:    vpop {d8, d9, d10, d11, d12, d13}1105; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}1106entry:1107  %conv = fptosi <4 x half> %x to <4 x i64>1108  %0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>1109  %spec.store.select = select <4 x i1> %0, <4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>1110  %1 = icmp sgt <4 x i64> %spec.store.select, zeroinitializer1111  %spec.store.select7 = select <4 x i1> %1, <4 x i64> %spec.store.select, <4 x i64> zeroinitializer1112  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>1113  ret <4 x i32> %conv61114}1115 1116; i16 saturate1117 1118define <2 x i16> @stest_f64i16(<2 x double> %x) {1119; CHECK-LABEL: stest_f64i16:1120; CHECK:       @ %bb.0: @ %entry1121; CHECK-NEXT:    vcvt.s32.f64 s4, d01122; CHECK-NEXT:    vmov r0, s41123; CHECK-NEXT:    vcvt.s32.f64 s0, d11124; CHECK-NEXT:    vmov.i32 d17, #0x7fff1125; CHECK-NEXT:    vmvn.i32 d18, #0x7fff1126; CHECK-NEXT:    vmov.32 d16[0], r01127; CHECK-NEXT:    vmov r0, s01128; CHECK-NEXT:    vmov.32 d16[1], r01129; CHECK-NEXT:    vmin.s32 d16, d16, d171130; CHECK-NEXT:    vmax.s32 d0, d16, d181131; CHECK-NEXT:    bx lr1132entry:1133  %conv = fptosi <2 x double> %x to <2 x i32>1134  %0 = icmp slt <2 x i32> %conv, <i32 32767, i32 32767>1135  %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>1136  %1 = icmp sgt <2 x i32> %spec.store.select, <i32 -32768, i32 -32768>1137  %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>1138  %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>1139  ret <2 x i16> %conv61140}1141 1142define <2 x i16> @utest_f64i16(<2 x double> %x) {1143; CHECK-LABEL: utest_f64i16:1144; CHECK:       @ %bb.0: @ %entry1145; CHECK-NEXT:    vcvt.u32.f64 s4, d01146; CHECK-NEXT:    vmov r0, s41147; CHECK-NEXT:    vcvt.u32.f64 s0, d11148; CHECK-NEXT:    vmov.i32 d17, #0xffff1149; CHECK-NEXT:    vmov.32 d16[0], r01150; CHECK-NEXT:    vmov r0, s01151; CHECK-NEXT:    vmov.32 d16[1], r01152; CHECK-NEXT:    vmin.u32 d0, d16, d171153; CHECK-NEXT:    bx lr1154entry:1155  %conv = fptoui <2 x double> %x to <2 x i32>1156  %0 = icmp ult <2 x i32> %conv, <i32 65535, i32 65535>1157  %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>1158  %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>1159  ret <2 x i16> %conv61160}1161 1162define <2 x i16> @ustest_f64i16(<2 x double> %x) {1163; CHECK-LABEL: ustest_f64i16:1164; CHECK:       @ %bb.0: @ %entry1165; CHECK-NEXT:    vcvt.s32.f64 s4, d01166; CHECK-NEXT:    vmov r0, s41167; CHECK-NEXT:    vcvt.s32.f64 s0, d11168; CHECK-NEXT:    vmov.i32 d17, #0xffff1169; CHECK-NEXT:    vmov.i32 d18, #0x01170; CHECK-NEXT:    vmov.32 d16[0], r01171; CHECK-NEXT:    vmov r0, s01172; CHECK-NEXT:    vmov.32 d16[1], r01173; CHECK-NEXT:    vmin.s32 d16, d16, d171174; CHECK-NEXT:    vmax.s32 d0, d16, d181175; CHECK-NEXT:    bx lr1176entry:1177  %conv = fptosi <2 x double> %x to <2 x i32>1178  %0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535>1179  %spec.store.select = select <2 x i1> %0, <2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>1180  %1 = icmp sgt <2 x i32> %spec.store.select, zeroinitializer1181  %spec.store.select7 = select <2 x i1> %1, <2 x i32> %spec.store.select, <2 x i32> zeroinitializer1182  %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>1183  ret <2 x i16> %conv61184}1185 1186define <4 x i16> @stest_f32i16(<4 x float> %x) {1187; CHECK-LABEL: stest_f32i16:1188; CHECK:       @ %bb.0: @ %entry1189; CHECK-NEXT:    vcvt.s32.f32 q8, q01190; CHECK-NEXT:    vmov.i32 q9, #0x7fff1191; CHECK-NEXT:    vmvn.i32 q10, #0x7fff1192; CHECK-NEXT:    vmin.s32 q8, q8, q91193; CHECK-NEXT:    vmax.s32 q8, q8, q101194; CHECK-NEXT:    vmovn.i32 d0, q81195; CHECK-NEXT:    bx lr1196entry:1197  %conv = fptosi <4 x float> %x to <4 x i32>1198  %0 = icmp slt <4 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767>1199  %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>1200  %1 = icmp sgt <4 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>1201  %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>1202  %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>1203  ret <4 x i16> %conv61204}1205 1206define <4 x i16> @utest_f32i16(<4 x float> %x) {1207; CHECK-LABEL: utest_f32i16:1208; CHECK:       @ %bb.0: @ %entry1209; CHECK-NEXT:    vcvt.u32.f32 q8, q01210; CHECK-NEXT:    vmov.i32 q9, #0xffff1211; CHECK-NEXT:    vmin.u32 q8, q8, q91212; CHECK-NEXT:    vmovn.i32 d0, q81213; CHECK-NEXT:    bx lr1214entry:1215  %conv = fptoui <4 x float> %x to <4 x i32>1216  %0 = icmp ult <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>1217  %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>1218  %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>1219  ret <4 x i16> %conv61220}1221 1222define <4 x i16> @ustest_f32i16(<4 x float> %x) {1223; CHECK-LABEL: ustest_f32i16:1224; CHECK:       @ %bb.0: @ %entry1225; CHECK-NEXT:    vcvt.s32.f32 q8, q01226; CHECK-NEXT:    vmov.i32 q9, #0xffff1227; CHECK-NEXT:    vmov.i32 q10, #0x01228; CHECK-NEXT:    vmin.s32 q8, q8, q91229; CHECK-NEXT:    vmax.s32 q8, q8, q101230; CHECK-NEXT:    vmovn.i32 d0, q81231; CHECK-NEXT:    bx lr1232entry:1233  %conv = fptosi <4 x float> %x to <4 x i32>1234  %0 = icmp slt <4 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535>1235  %spec.store.select = select <4 x i1> %0, <4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>1236  %1 = icmp sgt <4 x i32> %spec.store.select, zeroinitializer1237  %spec.store.select7 = select <4 x i1> %1, <4 x i32> %spec.store.select, <4 x i32> zeroinitializer1238  %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>1239  ret <4 x i16> %conv61240}1241 1242define <8 x i16> @stest_f16i16(<8 x half> %x) {1243; CHECK-NEON-LABEL: stest_f16i16:1244; CHECK-NEON:       @ %bb.0: @ %entry1245; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}1246; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}1247; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1248; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}1249; CHECK-NEON-NEXT:    vmov r0, s11250; CHECK-NEON-NEXT:    vmov.f32 s16, s71251; CHECK-NEON-NEXT:    vmov.f32 s18, s61252; CHECK-NEON-NEXT:    vmov.f32 s20, s51253; CHECK-NEON-NEXT:    vmov.f32 s22, s41254; CHECK-NEON-NEXT:    vmov.f32 s24, s31255; CHECK-NEON-NEXT:    vmov.f32 s26, s21256; CHECK-NEON-NEXT:    vmov.f32 s28, s01257; CHECK-NEON-NEXT:    bl __aeabi_h2f1258; CHECK-NEON-NEXT:    mov r4, r01259; CHECK-NEON-NEXT:    vmov r0, s261260; CHECK-NEON-NEXT:    bl __aeabi_h2f1261; CHECK-NEON-NEXT:    mov r5, r01262; CHECK-NEON-NEXT:    vmov r0, s221263; CHECK-NEON-NEXT:    bl __aeabi_h2f1264; CHECK-NEON-NEXT:    mov r6, r01265; CHECK-NEON-NEXT:    vmov r0, s241266; CHECK-NEON-NEXT:    bl __aeabi_h2f1267; CHECK-NEON-NEXT:    mov r7, r01268; CHECK-NEON-NEXT:    vmov r0, s181269; CHECK-NEON-NEXT:    bl __aeabi_h2f1270; CHECK-NEON-NEXT:    vmov s0, r01271; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01272; CHECK-NEON-NEXT:    vmov r0, s01273; CHECK-NEON-NEXT:    vmov.32 d13[0], r01274; CHECK-NEON-NEXT:    vmov r0, s161275; CHECK-NEON-NEXT:    bl __aeabi_h2f1276; CHECK-NEON-NEXT:    vmov s0, r01277; CHECK-NEON-NEXT:    vmov s22, r71278; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01279; CHECK-NEON-NEXT:    vmov s30, r61280; CHECK-NEON-NEXT:    vmov r0, s01281; CHECK-NEON-NEXT:    vmov.32 d13[1], r01282; CHECK-NEON-NEXT:    vmov r0, s281283; CHECK-NEON-NEXT:    bl __aeabi_h2f1284; CHECK-NEON-NEXT:    vmov s0, r01285; CHECK-NEON-NEXT:    vmov r1, s201286; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01287; CHECK-NEON-NEXT:    vmov s2, r51288; CHECK-NEON-NEXT:    vcvt.s32.f32 s20, s21289; CHECK-NEON-NEXT:    vmov r0, s01290; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s301291; CHECK-NEON-NEXT:    vmov.32 d8[0], r01292; CHECK-NEON-NEXT:    vmov r0, s01293; CHECK-NEON-NEXT:    vmov.32 d12[0], r01294; CHECK-NEON-NEXT:    mov r0, r11295; CHECK-NEON-NEXT:    bl __aeabi_h2f1296; CHECK-NEON-NEXT:    vmov s0, r01297; CHECK-NEON-NEXT:    vmov r0, s201298; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01299; CHECK-NEON-NEXT:    vmov s2, r41300; CHECK-NEON-NEXT:    vmov.i32 q8, #0x7fff1301; CHECK-NEON-NEXT:    vcvt.s32.f32 s2, s21302; CHECK-NEON-NEXT:    vmvn.i32 q9, #0x7fff1303; CHECK-NEON-NEXT:    vmov.32 d9[0], r01304; CHECK-NEON-NEXT:    vmov r0, s01305; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s221306; CHECK-NEON-NEXT:    vmov.32 d12[1], r01307; CHECK-NEON-NEXT:    vmov r0, s01308; CHECK-NEON-NEXT:    vmin.s32 q10, q6, q81309; CHECK-NEON-NEXT:    vmax.s32 q10, q10, q91310; CHECK-NEON-NEXT:    vmov.32 d9[1], r01311; CHECK-NEON-NEXT:    vmov r0, s21312; CHECK-NEON-NEXT:    vmovn.i32 d1, q101313; CHECK-NEON-NEXT:    vmov.32 d8[1], r01314; CHECK-NEON-NEXT:    vmin.s32 q8, q4, q81315; CHECK-NEON-NEXT:    vmax.s32 q8, q8, q91316; CHECK-NEON-NEXT:    vmovn.i32 d0, q81317; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}1318; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}1319;1320; CHECK-FP16-LABEL: stest_f16i16:1321; CHECK-FP16:       @ %bb.0: @ %entry1322; CHECK-FP16-NEXT:    vmovx.f16 s4, s01323; CHECK-FP16-NEXT:    vcvt.s32.f16 s12, s01324; CHECK-FP16-NEXT:    vcvt.s32.f16 s0, s31325; CHECK-FP16-NEXT:    vcvt.s32.f16 s5, s21326; CHECK-FP16-NEXT:    vmov r0, s01327; CHECK-FP16-NEXT:    vcvt.s32.f16 s14, s11328; CHECK-FP16-NEXT:    vmovx.f16 s10, s31329; CHECK-FP16-NEXT:    vmovx.f16 s8, s21330; CHECK-FP16-NEXT:    vcvt.s32.f16 s10, s101331; CHECK-FP16-NEXT:    vcvt.s32.f16 s8, s81332; CHECK-FP16-NEXT:    vmovx.f16 s6, s11333; CHECK-FP16-NEXT:    vcvt.s32.f16 s4, s41334; CHECK-FP16-NEXT:    vcvt.s32.f16 s6, s61335; CHECK-FP16-NEXT:    vmov.i32 q10, #0x7fff1336; CHECK-FP16-NEXT:    vmvn.i32 q11, #0x7fff1337; CHECK-FP16-NEXT:    vmov.32 d17[0], r01338; CHECK-FP16-NEXT:    vmov r0, s51339; CHECK-FP16-NEXT:    vmov.32 d16[0], r01340; CHECK-FP16-NEXT:    vmov r0, s141341; CHECK-FP16-NEXT:    vmov.32 d19[0], r01342; CHECK-FP16-NEXT:    vmov r0, s121343; CHECK-FP16-NEXT:    vmov.32 d18[0], r01344; CHECK-FP16-NEXT:    vmov r0, s101345; CHECK-FP16-NEXT:    vmov.32 d17[1], r01346; CHECK-FP16-NEXT:    vmov r0, s81347; CHECK-FP16-NEXT:    vmov.32 d16[1], r01348; CHECK-FP16-NEXT:    vmov r0, s61349; CHECK-FP16-NEXT:    vmin.s32 q8, q8, q101350; CHECK-FP16-NEXT:    vmax.s32 q8, q8, q111351; CHECK-FP16-NEXT:    vmovn.i32 d1, q81352; CHECK-FP16-NEXT:    vmov.32 d19[1], r01353; CHECK-FP16-NEXT:    vmov r0, s41354; CHECK-FP16-NEXT:    vmov.32 d18[1], r01355; CHECK-FP16-NEXT:    vmin.s32 q9, q9, q101356; CHECK-FP16-NEXT:    vmax.s32 q9, q9, q111357; CHECK-FP16-NEXT:    vmovn.i32 d0, q91358; CHECK-FP16-NEXT:    bx lr1359entry:1360  %conv = fptosi <8 x half> %x to <8 x i32>1361  %0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>1362  %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>1363  %1 = icmp sgt <8 x i32> %spec.store.select, <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>1364  %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>1365  %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>1366  ret <8 x i16> %conv61367}1368 1369define <8 x i16> @utest_f16i16(<8 x half> %x) {1370; CHECK-NEON-LABEL: utest_f16i16:1371; CHECK-NEON:       @ %bb.0: @ %entry1372; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}1373; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}1374; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14}1375; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14}1376; CHECK-NEON-NEXT:    vmov r0, s11377; CHECK-NEON-NEXT:    vmov.f32 s16, s71378; CHECK-NEON-NEXT:    vmov.f32 s18, s61379; CHECK-NEON-NEXT:    vmov.f32 s20, s51380; CHECK-NEON-NEXT:    vmov.f32 s22, s41381; CHECK-NEON-NEXT:    vmov.f32 s24, s31382; CHECK-NEON-NEXT:    vmov.f32 s26, s21383; CHECK-NEON-NEXT:    vmov.f32 s28, s01384; CHECK-NEON-NEXT:    bl __aeabi_h2f1385; CHECK-NEON-NEXT:    mov r4, r01386; CHECK-NEON-NEXT:    vmov r0, s261387; CHECK-NEON-NEXT:    bl __aeabi_h2f1388; CHECK-NEON-NEXT:    mov r5, r01389; CHECK-NEON-NEXT:    vmov r0, s221390; CHECK-NEON-NEXT:    bl __aeabi_h2f1391; CHECK-NEON-NEXT:    mov r6, r01392; CHECK-NEON-NEXT:    vmov r0, s241393; CHECK-NEON-NEXT:    bl __aeabi_h2f1394; CHECK-NEON-NEXT:    mov r7, r01395; CHECK-NEON-NEXT:    vmov r0, s181396; CHECK-NEON-NEXT:    bl __aeabi_h2f1397; CHECK-NEON-NEXT:    vmov s0, r01398; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s01399; CHECK-NEON-NEXT:    vmov r0, s01400; CHECK-NEON-NEXT:    vmov.32 d13[0], r01401; CHECK-NEON-NEXT:    vmov r0, s161402; CHECK-NEON-NEXT:    bl __aeabi_h2f1403; CHECK-NEON-NEXT:    vmov s0, r01404; CHECK-NEON-NEXT:    vmov s16, r71405; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s01406; CHECK-NEON-NEXT:    vmov s18, r61407; CHECK-NEON-NEXT:    vmov r0, s01408; CHECK-NEON-NEXT:    vmov.32 d13[1], r01409; CHECK-NEON-NEXT:    vmov r0, s281410; CHECK-NEON-NEXT:    bl __aeabi_h2f1411; CHECK-NEON-NEXT:    vmov s0, r01412; CHECK-NEON-NEXT:    vmov r1, s201413; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s01414; CHECK-NEON-NEXT:    vmov s2, r51415; CHECK-NEON-NEXT:    vmov r0, s01416; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s181417; CHECK-NEON-NEXT:    vcvt.u32.f32 s18, s21418; CHECK-NEON-NEXT:    vmov.32 d10[0], r01419; CHECK-NEON-NEXT:    vmov r0, s01420; CHECK-NEON-NEXT:    vmov.32 d12[0], r01421; CHECK-NEON-NEXT:    mov r0, r11422; CHECK-NEON-NEXT:    bl __aeabi_h2f1423; CHECK-NEON-NEXT:    vmov s0, r01424; CHECK-NEON-NEXT:    vmov r0, s181425; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s01426; CHECK-NEON-NEXT:    vmov s2, r41427; CHECK-NEON-NEXT:    vmov.i32 q8, #0xffff1428; CHECK-NEON-NEXT:    vcvt.u32.f32 s2, s21429; CHECK-NEON-NEXT:    vmov.32 d11[0], r01430; CHECK-NEON-NEXT:    vmov r0, s01431; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s161432; CHECK-NEON-NEXT:    vmov.32 d12[1], r01433; CHECK-NEON-NEXT:    vmov r0, s01434; CHECK-NEON-NEXT:    vmin.u32 q9, q6, q81435; CHECK-NEON-NEXT:    vmov.32 d11[1], r01436; CHECK-NEON-NEXT:    vmov r0, s21437; CHECK-NEON-NEXT:    vmovn.i32 d1, q91438; CHECK-NEON-NEXT:    vmov.32 d10[1], r01439; CHECK-NEON-NEXT:    vmin.u32 q8, q5, q81440; CHECK-NEON-NEXT:    vmovn.i32 d0, q81441; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14}1442; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}1443;1444; CHECK-FP16-LABEL: utest_f16i16:1445; CHECK-FP16:       @ %bb.0: @ %entry1446; CHECK-FP16-NEXT:    vmovx.f16 s4, s01447; CHECK-FP16-NEXT:    vcvt.u32.f16 s12, s01448; CHECK-FP16-NEXT:    vcvt.u32.f16 s0, s31449; CHECK-FP16-NEXT:    vcvt.u32.f16 s5, s21450; CHECK-FP16-NEXT:    vmov r0, s01451; CHECK-FP16-NEXT:    vcvt.u32.f16 s14, s11452; CHECK-FP16-NEXT:    vmovx.f16 s10, s31453; CHECK-FP16-NEXT:    vmovx.f16 s8, s21454; CHECK-FP16-NEXT:    vcvt.u32.f16 s10, s101455; CHECK-FP16-NEXT:    vcvt.u32.f16 s8, s81456; CHECK-FP16-NEXT:    vmovx.f16 s6, s11457; CHECK-FP16-NEXT:    vcvt.u32.f16 s4, s41458; CHECK-FP16-NEXT:    vcvt.u32.f16 s6, s61459; CHECK-FP16-NEXT:    vmov.i32 q10, #0xffff1460; CHECK-FP16-NEXT:    vmov.32 d17[0], r01461; CHECK-FP16-NEXT:    vmov r0, s51462; CHECK-FP16-NEXT:    vmov.32 d16[0], r01463; CHECK-FP16-NEXT:    vmov r0, s141464; CHECK-FP16-NEXT:    vmov.32 d19[0], r01465; CHECK-FP16-NEXT:    vmov r0, s121466; CHECK-FP16-NEXT:    vmov.32 d18[0], r01467; CHECK-FP16-NEXT:    vmov r0, s101468; CHECK-FP16-NEXT:    vmov.32 d17[1], r01469; CHECK-FP16-NEXT:    vmov r0, s81470; CHECK-FP16-NEXT:    vmov.32 d16[1], r01471; CHECK-FP16-NEXT:    vmov r0, s61472; CHECK-FP16-NEXT:    vmin.u32 q8, q8, q101473; CHECK-FP16-NEXT:    vmovn.i32 d1, q81474; CHECK-FP16-NEXT:    vmov.32 d19[1], r01475; CHECK-FP16-NEXT:    vmov r0, s41476; CHECK-FP16-NEXT:    vmov.32 d18[1], r01477; CHECK-FP16-NEXT:    vmin.u32 q9, q9, q101478; CHECK-FP16-NEXT:    vmovn.i32 d0, q91479; CHECK-FP16-NEXT:    bx lr1480entry:1481  %conv = fptoui <8 x half> %x to <8 x i32>1482  %0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>1483  %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>1484  %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>1485  ret <8 x i16> %conv61486}1487 1488define <8 x i16> @ustest_f16i16(<8 x half> %x) {1489; CHECK-NEON-LABEL: ustest_f16i16:1490; CHECK-NEON:       @ %bb.0: @ %entry1491; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}1492; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}1493; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}1494; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}1495; CHECK-NEON-NEXT:    vmov r0, s11496; CHECK-NEON-NEXT:    vmov.f32 s16, s71497; CHECK-NEON-NEXT:    vmov.f32 s18, s61498; CHECK-NEON-NEXT:    vmov.f32 s20, s51499; CHECK-NEON-NEXT:    vmov.f32 s22, s41500; CHECK-NEON-NEXT:    vmov.f32 s24, s31501; CHECK-NEON-NEXT:    vmov.f32 s26, s21502; CHECK-NEON-NEXT:    vmov.f32 s28, s01503; CHECK-NEON-NEXT:    bl __aeabi_h2f1504; CHECK-NEON-NEXT:    mov r4, r01505; CHECK-NEON-NEXT:    vmov r0, s261506; CHECK-NEON-NEXT:    bl __aeabi_h2f1507; CHECK-NEON-NEXT:    mov r5, r01508; CHECK-NEON-NEXT:    vmov r0, s221509; CHECK-NEON-NEXT:    bl __aeabi_h2f1510; CHECK-NEON-NEXT:    mov r6, r01511; CHECK-NEON-NEXT:    vmov r0, s241512; CHECK-NEON-NEXT:    bl __aeabi_h2f1513; CHECK-NEON-NEXT:    mov r7, r01514; CHECK-NEON-NEXT:    vmov r0, s181515; CHECK-NEON-NEXT:    bl __aeabi_h2f1516; CHECK-NEON-NEXT:    vmov s0, r01517; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01518; CHECK-NEON-NEXT:    vmov r0, s01519; CHECK-NEON-NEXT:    vmov.32 d13[0], r01520; CHECK-NEON-NEXT:    vmov r0, s161521; CHECK-NEON-NEXT:    bl __aeabi_h2f1522; CHECK-NEON-NEXT:    vmov s0, r01523; CHECK-NEON-NEXT:    vmov s22, r71524; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01525; CHECK-NEON-NEXT:    vmov s30, r61526; CHECK-NEON-NEXT:    vmov r0, s01527; CHECK-NEON-NEXT:    vmov.32 d13[1], r01528; CHECK-NEON-NEXT:    vmov r0, s281529; CHECK-NEON-NEXT:    bl __aeabi_h2f1530; CHECK-NEON-NEXT:    vmov s0, r01531; CHECK-NEON-NEXT:    vmov r1, s201532; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01533; CHECK-NEON-NEXT:    vmov s2, r51534; CHECK-NEON-NEXT:    vcvt.s32.f32 s20, s21535; CHECK-NEON-NEXT:    vmov r0, s01536; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s301537; CHECK-NEON-NEXT:    vmov.32 d8[0], r01538; CHECK-NEON-NEXT:    vmov r0, s01539; CHECK-NEON-NEXT:    vmov.32 d12[0], r01540; CHECK-NEON-NEXT:    mov r0, r11541; CHECK-NEON-NEXT:    bl __aeabi_h2f1542; CHECK-NEON-NEXT:    vmov s0, r01543; CHECK-NEON-NEXT:    vmov r0, s201544; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s01545; CHECK-NEON-NEXT:    vmov s2, r41546; CHECK-NEON-NEXT:    vmov.i32 q8, #0xffff1547; CHECK-NEON-NEXT:    vcvt.s32.f32 s2, s21548; CHECK-NEON-NEXT:    vmov.i32 q9, #0x01549; CHECK-NEON-NEXT:    vmov.32 d9[0], r01550; CHECK-NEON-NEXT:    vmov r0, s01551; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s221552; CHECK-NEON-NEXT:    vmov.32 d12[1], r01553; CHECK-NEON-NEXT:    vmov r0, s01554; CHECK-NEON-NEXT:    vmin.s32 q10, q6, q81555; CHECK-NEON-NEXT:    vmax.s32 q10, q10, q91556; CHECK-NEON-NEXT:    vmov.32 d9[1], r01557; CHECK-NEON-NEXT:    vmov r0, s21558; CHECK-NEON-NEXT:    vmovn.i32 d1, q101559; CHECK-NEON-NEXT:    vmov.32 d8[1], r01560; CHECK-NEON-NEXT:    vmin.s32 q8, q4, q81561; CHECK-NEON-NEXT:    vmax.s32 q8, q8, q91562; CHECK-NEON-NEXT:    vmovn.i32 d0, q81563; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}1564; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}1565;1566; CHECK-FP16-LABEL: ustest_f16i16:1567; CHECK-FP16:       @ %bb.0: @ %entry1568; CHECK-FP16-NEXT:    vmovx.f16 s4, s01569; CHECK-FP16-NEXT:    vcvt.s32.f16 s12, s01570; CHECK-FP16-NEXT:    vcvt.s32.f16 s0, s31571; CHECK-FP16-NEXT:    vcvt.s32.f16 s5, s21572; CHECK-FP16-NEXT:    vmov r0, s01573; CHECK-FP16-NEXT:    vcvt.s32.f16 s14, s11574; CHECK-FP16-NEXT:    vmovx.f16 s10, s31575; CHECK-FP16-NEXT:    vmovx.f16 s8, s21576; CHECK-FP16-NEXT:    vcvt.s32.f16 s10, s101577; CHECK-FP16-NEXT:    vcvt.s32.f16 s8, s81578; CHECK-FP16-NEXT:    vmovx.f16 s6, s11579; CHECK-FP16-NEXT:    vcvt.s32.f16 s4, s41580; CHECK-FP16-NEXT:    vcvt.s32.f16 s6, s61581; CHECK-FP16-NEXT:    vmov.i32 q10, #0xffff1582; CHECK-FP16-NEXT:    vmov.i32 q11, #0x01583; CHECK-FP16-NEXT:    vmov.32 d17[0], r01584; CHECK-FP16-NEXT:    vmov r0, s51585; CHECK-FP16-NEXT:    vmov.32 d16[0], r01586; CHECK-FP16-NEXT:    vmov r0, s141587; CHECK-FP16-NEXT:    vmov.32 d19[0], r01588; CHECK-FP16-NEXT:    vmov r0, s121589; CHECK-FP16-NEXT:    vmov.32 d18[0], r01590; CHECK-FP16-NEXT:    vmov r0, s101591; CHECK-FP16-NEXT:    vmov.32 d17[1], r01592; CHECK-FP16-NEXT:    vmov r0, s81593; CHECK-FP16-NEXT:    vmov.32 d16[1], r01594; CHECK-FP16-NEXT:    vmov r0, s61595; CHECK-FP16-NEXT:    vmin.s32 q8, q8, q101596; CHECK-FP16-NEXT:    vmax.s32 q8, q8, q111597; CHECK-FP16-NEXT:    vmovn.i32 d1, q81598; CHECK-FP16-NEXT:    vmov.32 d19[1], r01599; CHECK-FP16-NEXT:    vmov r0, s41600; CHECK-FP16-NEXT:    vmov.32 d18[1], r01601; CHECK-FP16-NEXT:    vmin.s32 q9, q9, q101602; CHECK-FP16-NEXT:    vmax.s32 q9, q9, q111603; CHECK-FP16-NEXT:    vmovn.i32 d0, q91604; CHECK-FP16-NEXT:    bx lr1605entry:1606  %conv = fptosi <8 x half> %x to <8 x i32>1607  %0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>1608  %spec.store.select = select <8 x i1> %0, <8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>1609  %1 = icmp sgt <8 x i32> %spec.store.select, zeroinitializer1610  %spec.store.select7 = select <8 x i1> %1, <8 x i32> %spec.store.select, <8 x i32> zeroinitializer1611  %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>1612  ret <8 x i16> %conv61613}1614 1615; i64 saturate1616 1617define <2 x i64> @stest_f64i64(<2 x double> %x) {1618; CHECK-LABEL: stest_f64i64:1619; CHECK:       @ %bb.0: @ %entry1620; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}1621; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}1622; CHECK-NEXT:    .vsave {d8, d9}1623; CHECK-NEXT:    vpush {d8, d9}1624; CHECK-NEXT:    vorr q4, q0, q01625; CHECK-NEXT:    vorr d0, d9, d91626; CHECK-NEXT:    bl __fixdfti1627; CHECK-NEXT:    mov r4, r11628; CHECK-NEXT:    mvn r9, #01629; CHECK-NEXT:    subs r1, r0, r91630; CHECK-NEXT:    mvn r5, #-21474836481631; CHECK-NEXT:    sbcs r1, r4, r51632; CHECK-NEXT:    vorr d0, d8, d81633; CHECK-NEXT:    sbcs r1, r2, #01634; CHECK-NEXT:    mov r7, #01635; CHECK-NEXT:    sbcs r1, r3, #01636; CHECK-NEXT:    mov r8, #-21474836481637; CHECK-NEXT:    mov r1, #01638; CHECK-NEXT:    mov r10, #01639; CHECK-NEXT:    movwlt r1, #11640; CHECK-NEXT:    cmp r1, #01641; CHECK-NEXT:    moveq r3, r11642; CHECK-NEXT:    movne r1, r21643; CHECK-NEXT:    moveq r4, r51644; CHECK-NEXT:    moveq r0, r91645; CHECK-NEXT:    rsbs r2, r0, #01646; CHECK-NEXT:    rscs r2, r4, #-21474836481647; CHECK-NEXT:    sbcs r1, r9, r11648; CHECK-NEXT:    sbcs r1, r9, r31649; CHECK-NEXT:    movwlt r7, #11650; CHECK-NEXT:    cmp r7, #01651; CHECK-NEXT:    movne r7, r01652; CHECK-NEXT:    moveq r4, r81653; CHECK-NEXT:    bl __fixdfti1654; CHECK-NEXT:    subs r6, r0, r91655; CHECK-NEXT:    vmov.32 d1[0], r71656; CHECK-NEXT:    sbcs r6, r1, r51657; CHECK-NEXT:    sbcs r6, r2, #01658; CHECK-NEXT:    sbcs r6, r3, #01659; CHECK-NEXT:    mov r6, #01660; CHECK-NEXT:    movwlt r6, #11661; CHECK-NEXT:    cmp r6, #01662; CHECK-NEXT:    moveq r3, r61663; CHECK-NEXT:    movne r6, r21664; CHECK-NEXT:    movne r5, r11665; CHECK-NEXT:    moveq r0, r91666; CHECK-NEXT:    rsbs r1, r0, #01667; CHECK-NEXT:    rscs r1, r5, #-21474836481668; CHECK-NEXT:    sbcs r1, r9, r61669; CHECK-NEXT:    sbcs r1, r9, r31670; CHECK-NEXT:    movwlt r10, #11671; CHECK-NEXT:    cmp r10, #01672; CHECK-NEXT:    movne r10, r01673; CHECK-NEXT:    moveq r5, r81674; CHECK-NEXT:    vmov.32 d0[0], r101675; CHECK-NEXT:    vmov.32 d1[1], r41676; CHECK-NEXT:    vmov.32 d0[1], r51677; CHECK-NEXT:    vpop {d8, d9}1678; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}1679entry:1680  %conv = fptosi <2 x double> %x to <2 x i128>1681  %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>1682  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>1683  %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>1684  %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>1685  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1686  ret <2 x i64> %conv61687}1688 1689define <2 x i64> @utest_f64i64(<2 x double> %x) {1690; CHECK-LABEL: utest_f64i64:1691; CHECK:       @ %bb.0: @ %entry1692; CHECK-NEXT:    .save {r4, r5, r6, lr}1693; CHECK-NEXT:    push {r4, r5, r6, lr}1694; CHECK-NEXT:    .vsave {d8, d9}1695; CHECK-NEXT:    vpush {d8, d9}1696; CHECK-NEXT:    vorr q4, q0, q01697; CHECK-NEXT:    vorr d0, d9, d91698; CHECK-NEXT:    bl __fixunsdfti1699; CHECK-NEXT:    mov r4, r11700; CHECK-NEXT:    subs r1, r2, #11701; CHECK-NEXT:    vorr d0, d8, d81702; CHECK-NEXT:    sbcs r1, r3, #01703; CHECK-NEXT:    mov r6, #01704; CHECK-NEXT:    mov r5, #01705; CHECK-NEXT:    movwlo r6, #11706; CHECK-NEXT:    cmp r6, #01707; CHECK-NEXT:    moveq r4, r61708; CHECK-NEXT:    movne r6, r01709; CHECK-NEXT:    bl __fixunsdfti1710; CHECK-NEXT:    subs r2, r2, #11711; CHECK-NEXT:    vmov.32 d1[0], r61712; CHECK-NEXT:    sbcs r2, r3, #01713; CHECK-NEXT:    movwlo r5, #11714; CHECK-NEXT:    cmp r5, #01715; CHECK-NEXT:    moveq r0, r51716; CHECK-NEXT:    movne r5, r11717; CHECK-NEXT:    vmov.32 d0[0], r01718; CHECK-NEXT:    vmov.32 d1[1], r41719; CHECK-NEXT:    vmov.32 d0[1], r51720; CHECK-NEXT:    vpop {d8, d9}1721; CHECK-NEXT:    pop {r4, r5, r6, pc}1722entry:1723  %conv = fptoui <2 x double> %x to <2 x i128>1724  %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>1725  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>1726  %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>1727  ret <2 x i64> %conv61728}1729 1730define <2 x i64> @ustest_f64i64(<2 x double> %x) {1731; CHECK-LABEL: ustest_f64i64:1732; CHECK:       @ %bb.0: @ %entry1733; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}1734; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}1735; CHECK-NEXT:    .vsave {d8, d9}1736; CHECK-NEXT:    vpush {d8, d9}1737; CHECK-NEXT:    vorr q4, q0, q01738; CHECK-NEXT:    vorr d0, d9, d91739; CHECK-NEXT:    bl __fixdfti1740; CHECK-NEXT:    mov r4, r11741; CHECK-NEXT:    subs r1, r2, #11742; CHECK-NEXT:    sbcs r1, r3, #01743; CHECK-NEXT:    mov r8, #11744; CHECK-NEXT:    mov r1, #01745; CHECK-NEXT:    movge r2, r81746; CHECK-NEXT:    movwlt r1, #11747; CHECK-NEXT:    cmp r1, #01748; CHECK-NEXT:    moveq r3, r11749; CHECK-NEXT:    moveq r4, r11750; CHECK-NEXT:    movne r1, r01751; CHECK-NEXT:    rsbs r0, r1, #01752; CHECK-NEXT:    rscs r0, r4, #01753; CHECK-NEXT:    vorr d0, d8, d81754; CHECK-NEXT:    rscs r0, r2, #01755; CHECK-NEXT:    mov r7, #01756; CHECK-NEXT:    rscs r0, r3, #01757; CHECK-NEXT:    mov r5, #01758; CHECK-NEXT:    movwlt r7, #11759; CHECK-NEXT:    cmp r7, #01760; CHECK-NEXT:    moveq r4, r71761; CHECK-NEXT:    movne r7, r11762; CHECK-NEXT:    bl __fixdfti1763; CHECK-NEXT:    subs r6, r2, #11764; CHECK-NEXT:    vmov.32 d1[0], r71765; CHECK-NEXT:    sbcs r6, r3, #01766; CHECK-NEXT:    movlt r8, r21767; CHECK-NEXT:    mov r2, #01768; CHECK-NEXT:    movwlt r2, #11769; CHECK-NEXT:    cmp r2, #01770; CHECK-NEXT:    moveq r3, r21771; CHECK-NEXT:    moveq r1, r21772; CHECK-NEXT:    movne r2, r01773; CHECK-NEXT:    rsbs r0, r2, #01774; CHECK-NEXT:    rscs r0, r1, #01775; CHECK-NEXT:    rscs r0, r8, #01776; CHECK-NEXT:    rscs r0, r3, #01777; CHECK-NEXT:    movwlt r5, #11778; CHECK-NEXT:    cmp r5, #01779; CHECK-NEXT:    moveq r2, r51780; CHECK-NEXT:    movne r5, r11781; CHECK-NEXT:    vmov.32 d0[0], r21782; CHECK-NEXT:    vmov.32 d1[1], r41783; CHECK-NEXT:    vmov.32 d0[1], r51784; CHECK-NEXT:    vpop {d8, d9}1785; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, pc}1786entry:1787  %conv = fptosi <2 x double> %x to <2 x i128>1788  %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>1789  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>1790  %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer1791  %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer1792  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1793  ret <2 x i64> %conv61794}1795 1796define <2 x i64> @stest_f32i64(<2 x float> %x) {1797; CHECK-LABEL: stest_f32i64:1798; CHECK:       @ %bb.0: @ %entry1799; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}1800; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}1801; CHECK-NEXT:    .vsave {d8}1802; CHECK-NEXT:    vpush {d8}1803; CHECK-NEXT:    vmov.f64 d8, d01804; CHECK-NEXT:    vmov.f32 s0, s171805; CHECK-NEXT:    bl __fixsfti1806; CHECK-NEXT:    mov r4, r11807; CHECK-NEXT:    mvn r9, #01808; CHECK-NEXT:    subs r1, r0, r91809; CHECK-NEXT:    mvn r5, #-21474836481810; CHECK-NEXT:    sbcs r1, r4, r51811; CHECK-NEXT:    vmov.f32 s0, s161812; CHECK-NEXT:    sbcs r1, r2, #01813; CHECK-NEXT:    mov r7, #01814; CHECK-NEXT:    sbcs r1, r3, #01815; CHECK-NEXT:    mov r8, #-21474836481816; CHECK-NEXT:    mov r1, #01817; CHECK-NEXT:    mov r10, #01818; CHECK-NEXT:    movwlt r1, #11819; CHECK-NEXT:    cmp r1, #01820; CHECK-NEXT:    moveq r3, r11821; CHECK-NEXT:    movne r1, r21822; CHECK-NEXT:    moveq r4, r51823; CHECK-NEXT:    moveq r0, r91824; CHECK-NEXT:    rsbs r2, r0, #01825; CHECK-NEXT:    rscs r2, r4, #-21474836481826; CHECK-NEXT:    sbcs r1, r9, r11827; CHECK-NEXT:    sbcs r1, r9, r31828; CHECK-NEXT:    movwlt r7, #11829; CHECK-NEXT:    cmp r7, #01830; CHECK-NEXT:    movne r7, r01831; CHECK-NEXT:    moveq r4, r81832; CHECK-NEXT:    bl __fixsfti1833; CHECK-NEXT:    subs r6, r0, r91834; CHECK-NEXT:    vmov.32 d1[0], r71835; CHECK-NEXT:    sbcs r6, r1, r51836; CHECK-NEXT:    sbcs r6, r2, #01837; CHECK-NEXT:    sbcs r6, r3, #01838; CHECK-NEXT:    mov r6, #01839; CHECK-NEXT:    movwlt r6, #11840; CHECK-NEXT:    cmp r6, #01841; CHECK-NEXT:    moveq r3, r61842; CHECK-NEXT:    movne r6, r21843; CHECK-NEXT:    movne r5, r11844; CHECK-NEXT:    moveq r0, r91845; CHECK-NEXT:    rsbs r1, r0, #01846; CHECK-NEXT:    rscs r1, r5, #-21474836481847; CHECK-NEXT:    sbcs r1, r9, r61848; CHECK-NEXT:    sbcs r1, r9, r31849; CHECK-NEXT:    movwlt r10, #11850; CHECK-NEXT:    cmp r10, #01851; CHECK-NEXT:    movne r10, r01852; CHECK-NEXT:    moveq r5, r81853; CHECK-NEXT:    vmov.32 d0[0], r101854; CHECK-NEXT:    vmov.32 d1[1], r41855; CHECK-NEXT:    vmov.32 d0[1], r51856; CHECK-NEXT:    vpop {d8}1857; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}1858entry:1859  %conv = fptosi <2 x float> %x to <2 x i128>1860  %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>1861  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>1862  %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>1863  %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>1864  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1865  ret <2 x i64> %conv61866}1867 1868define <2 x i64> @utest_f32i64(<2 x float> %x) {1869; CHECK-LABEL: utest_f32i64:1870; CHECK:       @ %bb.0: @ %entry1871; CHECK-NEXT:    .save {r4, r5, r6, lr}1872; CHECK-NEXT:    push {r4, r5, r6, lr}1873; CHECK-NEXT:    .vsave {d8}1874; CHECK-NEXT:    vpush {d8}1875; CHECK-NEXT:    vmov.f64 d8, d01876; CHECK-NEXT:    vmov.f32 s0, s171877; CHECK-NEXT:    bl __fixunssfti1878; CHECK-NEXT:    vmov.f32 s0, s161879; CHECK-NEXT:    mov r4, r11880; CHECK-NEXT:    subs r1, r2, #11881; CHECK-NEXT:    mov r6, #01882; CHECK-NEXT:    sbcs r1, r3, #01883; CHECK-NEXT:    mov r5, #01884; CHECK-NEXT:    movwlo r6, #11885; CHECK-NEXT:    cmp r6, #01886; CHECK-NEXT:    moveq r4, r61887; CHECK-NEXT:    movne r6, r01888; CHECK-NEXT:    bl __fixunssfti1889; CHECK-NEXT:    subs r2, r2, #11890; CHECK-NEXT:    vmov.32 d1[0], r61891; CHECK-NEXT:    sbcs r2, r3, #01892; CHECK-NEXT:    movwlo r5, #11893; CHECK-NEXT:    cmp r5, #01894; CHECK-NEXT:    moveq r0, r51895; CHECK-NEXT:    movne r5, r11896; CHECK-NEXT:    vmov.32 d0[0], r01897; CHECK-NEXT:    vmov.32 d1[1], r41898; CHECK-NEXT:    vmov.32 d0[1], r51899; CHECK-NEXT:    vpop {d8}1900; CHECK-NEXT:    pop {r4, r5, r6, pc}1901entry:1902  %conv = fptoui <2 x float> %x to <2 x i128>1903  %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>1904  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>1905  %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>1906  ret <2 x i64> %conv61907}1908 1909define <2 x i64> @ustest_f32i64(<2 x float> %x) {1910; CHECK-LABEL: ustest_f32i64:1911; CHECK:       @ %bb.0: @ %entry1912; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}1913; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}1914; CHECK-NEXT:    .vsave {d8}1915; CHECK-NEXT:    vpush {d8}1916; CHECK-NEXT:    vmov.f64 d8, d01917; CHECK-NEXT:    vmov.f32 s0, s171918; CHECK-NEXT:    bl __fixsfti1919; CHECK-NEXT:    mov r4, r11920; CHECK-NEXT:    subs r1, r2, #11921; CHECK-NEXT:    sbcs r1, r3, #01922; CHECK-NEXT:    mov r8, #11923; CHECK-NEXT:    mov r1, #01924; CHECK-NEXT:    vmov.f32 s0, s161925; CHECK-NEXT:    movge r2, r81926; CHECK-NEXT:    movwlt r1, #11927; CHECK-NEXT:    cmp r1, #01928; CHECK-NEXT:    mov r7, #01929; CHECK-NEXT:    moveq r3, r11930; CHECK-NEXT:    moveq r4, r11931; CHECK-NEXT:    movne r1, r01932; CHECK-NEXT:    rsbs r0, r1, #01933; CHECK-NEXT:    rscs r0, r4, #01934; CHECK-NEXT:    mov r5, #01935; CHECK-NEXT:    rscs r0, r2, #01936; CHECK-NEXT:    rscs r0, r3, #01937; CHECK-NEXT:    movwlt r7, #11938; CHECK-NEXT:    cmp r7, #01939; CHECK-NEXT:    moveq r4, r71940; CHECK-NEXT:    movne r7, r11941; CHECK-NEXT:    bl __fixsfti1942; CHECK-NEXT:    subs r6, r2, #11943; CHECK-NEXT:    vmov.32 d1[0], r71944; CHECK-NEXT:    sbcs r6, r3, #01945; CHECK-NEXT:    movlt r8, r21946; CHECK-NEXT:    mov r2, #01947; CHECK-NEXT:    movwlt r2, #11948; CHECK-NEXT:    cmp r2, #01949; CHECK-NEXT:    moveq r3, r21950; CHECK-NEXT:    moveq r1, r21951; CHECK-NEXT:    movne r2, r01952; CHECK-NEXT:    rsbs r0, r2, #01953; CHECK-NEXT:    rscs r0, r1, #01954; CHECK-NEXT:    rscs r0, r8, #01955; CHECK-NEXT:    rscs r0, r3, #01956; CHECK-NEXT:    movwlt r5, #11957; CHECK-NEXT:    cmp r5, #01958; CHECK-NEXT:    moveq r2, r51959; CHECK-NEXT:    movne r5, r11960; CHECK-NEXT:    vmov.32 d0[0], r21961; CHECK-NEXT:    vmov.32 d1[1], r41962; CHECK-NEXT:    vmov.32 d0[1], r51963; CHECK-NEXT:    vpop {d8}1964; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, pc}1965entry:1966  %conv = fptosi <2 x float> %x to <2 x i128>1967  %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>1968  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>1969  %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer1970  %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer1971  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>1972  ret <2 x i64> %conv61973}1974 1975define <2 x i64> @stest_f16i64(<2 x half> %x) {1976; CHECK-NEON-LABEL: stest_f16i64:1977; CHECK-NEON:       @ %bb.0: @ %entry1978; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}1979; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}1980; CHECK-NEON-NEXT:    .vsave {d8}1981; CHECK-NEON-NEXT:    vpush {d8}1982; CHECK-NEON-NEXT:    vmov r0, s01983; CHECK-NEON-NEXT:    vmov.f32 s16, s11984; CHECK-NEON-NEXT:    bl __aeabi_h2f1985; CHECK-NEON-NEXT:    mov r8, r01986; CHECK-NEON-NEXT:    vmov r0, s161987; CHECK-NEON-NEXT:    bl __aeabi_h2f1988; CHECK-NEON-NEXT:    vmov s0, r01989; CHECK-NEON-NEXT:    bl __fixsfti1990; CHECK-NEON-NEXT:    mov r4, r11991; CHECK-NEON-NEXT:    mvn r9, #01992; CHECK-NEON-NEXT:    subs r1, r0, r91993; CHECK-NEON-NEXT:    mvn r6, #-21474836481994; CHECK-NEON-NEXT:    sbcs r1, r4, r61995; CHECK-NEON-NEXT:    vmov s0, r81996; CHECK-NEON-NEXT:    sbcs r1, r2, #01997; CHECK-NEON-NEXT:    mov r5, #01998; CHECK-NEON-NEXT:    sbcs r1, r3, #01999; CHECK-NEON-NEXT:    mov r8, #-21474836482000; CHECK-NEON-NEXT:    mov r1, #02001; CHECK-NEON-NEXT:    mov r10, #02002; CHECK-NEON-NEXT:    movwlt r1, #12003; CHECK-NEON-NEXT:    cmp r1, #02004; CHECK-NEON-NEXT:    moveq r3, r12005; CHECK-NEON-NEXT:    movne r1, r22006; CHECK-NEON-NEXT:    moveq r4, r62007; CHECK-NEON-NEXT:    moveq r0, r92008; CHECK-NEON-NEXT:    rsbs r2, r0, #02009; CHECK-NEON-NEXT:    rscs r2, r4, #-21474836482010; CHECK-NEON-NEXT:    sbcs r1, r9, r12011; CHECK-NEON-NEXT:    sbcs r1, r9, r32012; CHECK-NEON-NEXT:    movwlt r5, #12013; CHECK-NEON-NEXT:    cmp r5, #02014; CHECK-NEON-NEXT:    movne r5, r02015; CHECK-NEON-NEXT:    moveq r4, r82016; CHECK-NEON-NEXT:    bl __fixsfti2017; CHECK-NEON-NEXT:    subs r7, r0, r92018; CHECK-NEON-NEXT:    vmov.32 d1[0], r52019; CHECK-NEON-NEXT:    sbcs r7, r1, r62020; CHECK-NEON-NEXT:    sbcs r7, r2, #02021; CHECK-NEON-NEXT:    sbcs r7, r3, #02022; CHECK-NEON-NEXT:    mov r7, #02023; CHECK-NEON-NEXT:    movwlt r7, #12024; CHECK-NEON-NEXT:    cmp r7, #02025; CHECK-NEON-NEXT:    moveq r3, r72026; CHECK-NEON-NEXT:    movne r7, r22027; CHECK-NEON-NEXT:    movne r6, r12028; CHECK-NEON-NEXT:    moveq r0, r92029; CHECK-NEON-NEXT:    rsbs r1, r0, #02030; CHECK-NEON-NEXT:    rscs r1, r6, #-21474836482031; CHECK-NEON-NEXT:    sbcs r1, r9, r72032; CHECK-NEON-NEXT:    sbcs r1, r9, r32033; CHECK-NEON-NEXT:    movwlt r10, #12034; CHECK-NEON-NEXT:    cmp r10, #02035; CHECK-NEON-NEXT:    movne r10, r02036; CHECK-NEON-NEXT:    moveq r6, r82037; CHECK-NEON-NEXT:    vmov.32 d0[0], r102038; CHECK-NEON-NEXT:    vmov.32 d1[1], r42039; CHECK-NEON-NEXT:    vmov.32 d0[1], r62040; CHECK-NEON-NEXT:    vpop {d8}2041; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}2042;2043; CHECK-FP16-LABEL: stest_f16i64:2044; CHECK-FP16:       @ %bb.0: @ %entry2045; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}2046; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}2047; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]2048; CHECK-FP16-NEXT:    vmov.u16 r7, d0[0]2049; CHECK-FP16-NEXT:    vmov s0, r02050; CHECK-FP16-NEXT:    bl __fixhfti2051; CHECK-FP16-NEXT:    mov r4, r12052; CHECK-FP16-NEXT:    mvn r9, #02053; CHECK-FP16-NEXT:    subs r1, r0, r92054; CHECK-FP16-NEXT:    mvn r5, #-21474836482055; CHECK-FP16-NEXT:    sbcs r1, r4, r52056; CHECK-FP16-NEXT:    vmov s0, r72057; CHECK-FP16-NEXT:    sbcs r1, r2, #02058; CHECK-FP16-NEXT:    mov r7, #02059; CHECK-FP16-NEXT:    sbcs r1, r3, #02060; CHECK-FP16-NEXT:    mov r8, #-21474836482061; CHECK-FP16-NEXT:    mov r1, #02062; CHECK-FP16-NEXT:    mov r10, #02063; CHECK-FP16-NEXT:    movwlt r1, #12064; CHECK-FP16-NEXT:    cmp r1, #02065; CHECK-FP16-NEXT:    moveq r3, r12066; CHECK-FP16-NEXT:    movne r1, r22067; CHECK-FP16-NEXT:    moveq r4, r52068; CHECK-FP16-NEXT:    moveq r0, r92069; CHECK-FP16-NEXT:    rsbs r2, r0, #02070; CHECK-FP16-NEXT:    rscs r2, r4, #-21474836482071; CHECK-FP16-NEXT:    sbcs r1, r9, r12072; CHECK-FP16-NEXT:    sbcs r1, r9, r32073; CHECK-FP16-NEXT:    movwlt r7, #12074; CHECK-FP16-NEXT:    cmp r7, #02075; CHECK-FP16-NEXT:    movne r7, r02076; CHECK-FP16-NEXT:    moveq r4, r82077; CHECK-FP16-NEXT:    bl __fixhfti2078; CHECK-FP16-NEXT:    subs r6, r0, r92079; CHECK-FP16-NEXT:    vmov.32 d1[0], r72080; CHECK-FP16-NEXT:    sbcs r6, r1, r52081; CHECK-FP16-NEXT:    sbcs r6, r2, #02082; CHECK-FP16-NEXT:    sbcs r6, r3, #02083; CHECK-FP16-NEXT:    mov r6, #02084; CHECK-FP16-NEXT:    movwlt r6, #12085; CHECK-FP16-NEXT:    cmp r6, #02086; CHECK-FP16-NEXT:    moveq r3, r62087; CHECK-FP16-NEXT:    movne r6, r22088; CHECK-FP16-NEXT:    movne r5, r12089; CHECK-FP16-NEXT:    moveq r0, r92090; CHECK-FP16-NEXT:    rsbs r1, r0, #02091; CHECK-FP16-NEXT:    rscs r1, r5, #-21474836482092; CHECK-FP16-NEXT:    sbcs r1, r9, r62093; CHECK-FP16-NEXT:    sbcs r1, r9, r32094; CHECK-FP16-NEXT:    movwlt r10, #12095; CHECK-FP16-NEXT:    cmp r10, #02096; CHECK-FP16-NEXT:    movne r10, r02097; CHECK-FP16-NEXT:    moveq r5, r82098; CHECK-FP16-NEXT:    vmov.32 d0[0], r102099; CHECK-FP16-NEXT:    vmov.32 d1[1], r42100; CHECK-FP16-NEXT:    vmov.32 d0[1], r52101; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}2102entry:2103  %conv = fptosi <2 x half> %x to <2 x i128>2104  %0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>2105  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>2106  %1 = icmp sgt <2 x i128> %spec.store.select, <i128 -9223372036854775808, i128 -9223372036854775808>2107  %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>2108  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>2109  ret <2 x i64> %conv62110}2111 2112define <2 x i64> @utest_f16i64(<2 x half> %x) {2113; CHECK-NEON-LABEL: utest_f16i64:2114; CHECK-NEON:       @ %bb.0: @ %entry2115; CHECK-NEON-NEXT:    .save {r4, r5, r6, lr}2116; CHECK-NEON-NEXT:    push {r4, r5, r6, lr}2117; CHECK-NEON-NEXT:    .vsave {d8}2118; CHECK-NEON-NEXT:    vpush {d8}2119; CHECK-NEON-NEXT:    vmov r0, s02120; CHECK-NEON-NEXT:    vmov.f32 s16, s12121; CHECK-NEON-NEXT:    bl __aeabi_h2f2122; CHECK-NEON-NEXT:    mov r5, r02123; CHECK-NEON-NEXT:    vmov r0, s162124; CHECK-NEON-NEXT:    bl __aeabi_h2f2125; CHECK-NEON-NEXT:    vmov s0, r02126; CHECK-NEON-NEXT:    bl __fixunssfti2127; CHECK-NEON-NEXT:    mov r4, r12128; CHECK-NEON-NEXT:    subs r1, r2, #12129; CHECK-NEON-NEXT:    vmov s0, r52130; CHECK-NEON-NEXT:    sbcs r1, r3, #02131; CHECK-NEON-NEXT:    mov r5, #02132; CHECK-NEON-NEXT:    mov r6, #02133; CHECK-NEON-NEXT:    movwlo r5, #12134; CHECK-NEON-NEXT:    cmp r5, #02135; CHECK-NEON-NEXT:    moveq r4, r52136; CHECK-NEON-NEXT:    movne r5, r02137; CHECK-NEON-NEXT:    bl __fixunssfti2138; CHECK-NEON-NEXT:    subs r2, r2, #12139; CHECK-NEON-NEXT:    vmov.32 d1[0], r52140; CHECK-NEON-NEXT:    sbcs r2, r3, #02141; CHECK-NEON-NEXT:    movwlo r6, #12142; CHECK-NEON-NEXT:    cmp r6, #02143; CHECK-NEON-NEXT:    moveq r0, r62144; CHECK-NEON-NEXT:    movne r6, r12145; CHECK-NEON-NEXT:    vmov.32 d0[0], r02146; CHECK-NEON-NEXT:    vmov.32 d1[1], r42147; CHECK-NEON-NEXT:    vmov.32 d0[1], r62148; CHECK-NEON-NEXT:    vpop {d8}2149; CHECK-NEON-NEXT:    pop {r4, r5, r6, pc}2150;2151; CHECK-FP16-LABEL: utest_f16i64:2152; CHECK-FP16:       @ %bb.0: @ %entry2153; CHECK-FP16-NEXT:    .save {r4, r5, r6, lr}2154; CHECK-FP16-NEXT:    push {r4, r5, r6, lr}2155; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]2156; CHECK-FP16-NEXT:    vmov.u16 r6, d0[0]2157; CHECK-FP16-NEXT:    vmov s0, r02158; CHECK-FP16-NEXT:    bl __fixunshfti2159; CHECK-FP16-NEXT:    mov r4, r12160; CHECK-FP16-NEXT:    subs r1, r2, #12161; CHECK-FP16-NEXT:    vmov s0, r62162; CHECK-FP16-NEXT:    sbcs r1, r3, #02163; CHECK-FP16-NEXT:    mov r6, #02164; CHECK-FP16-NEXT:    mov r5, #02165; CHECK-FP16-NEXT:    movwlo r6, #12166; CHECK-FP16-NEXT:    cmp r6, #02167; CHECK-FP16-NEXT:    moveq r4, r62168; CHECK-FP16-NEXT:    movne r6, r02169; CHECK-FP16-NEXT:    bl __fixunshfti2170; CHECK-FP16-NEXT:    subs r2, r2, #12171; CHECK-FP16-NEXT:    vmov.32 d1[0], r62172; CHECK-FP16-NEXT:    sbcs r2, r3, #02173; CHECK-FP16-NEXT:    movwlo r5, #12174; CHECK-FP16-NEXT:    cmp r5, #02175; CHECK-FP16-NEXT:    moveq r0, r52176; CHECK-FP16-NEXT:    movne r5, r12177; CHECK-FP16-NEXT:    vmov.32 d0[0], r02178; CHECK-FP16-NEXT:    vmov.32 d1[1], r42179; CHECK-FP16-NEXT:    vmov.32 d0[1], r52180; CHECK-FP16-NEXT:    pop {r4, r5, r6, pc}2181entry:2182  %conv = fptoui <2 x half> %x to <2 x i128>2183  %0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>2184  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>2185  %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>2186  ret <2 x i64> %conv62187}2188 2189define <2 x i64> @ustest_f16i64(<2 x half> %x) {2190; CHECK-NEON-LABEL: ustest_f16i64:2191; CHECK-NEON:       @ %bb.0: @ %entry2192; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, lr}2193; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, lr}2194; CHECK-NEON-NEXT:    .vsave {d8}2195; CHECK-NEON-NEXT:    vpush {d8}2196; CHECK-NEON-NEXT:    vmov r0, s02197; CHECK-NEON-NEXT:    vmov.f32 s16, s12198; CHECK-NEON-NEXT:    bl __aeabi_h2f2199; CHECK-NEON-NEXT:    mov r5, r02200; CHECK-NEON-NEXT:    vmov r0, s162201; CHECK-NEON-NEXT:    bl __aeabi_h2f2202; CHECK-NEON-NEXT:    vmov s0, r02203; CHECK-NEON-NEXT:    bl __fixsfti2204; CHECK-NEON-NEXT:    mov r4, r12205; CHECK-NEON-NEXT:    subs r1, r2, #12206; CHECK-NEON-NEXT:    sbcs r1, r3, #02207; CHECK-NEON-NEXT:    mov r8, #12208; CHECK-NEON-NEXT:    mov r1, #02209; CHECK-NEON-NEXT:    movge r2, r82210; CHECK-NEON-NEXT:    movwlt r1, #12211; CHECK-NEON-NEXT:    cmp r1, #02212; CHECK-NEON-NEXT:    moveq r3, r12213; CHECK-NEON-NEXT:    moveq r4, r12214; CHECK-NEON-NEXT:    movne r1, r02215; CHECK-NEON-NEXT:    rsbs r0, r1, #02216; CHECK-NEON-NEXT:    rscs r0, r4, #02217; CHECK-NEON-NEXT:    vmov s0, r52218; CHECK-NEON-NEXT:    rscs r0, r2, #02219; CHECK-NEON-NEXT:    mov r7, #02220; CHECK-NEON-NEXT:    rscs r0, r3, #02221; CHECK-NEON-NEXT:    mov r5, #02222; CHECK-NEON-NEXT:    movwlt r7, #12223; CHECK-NEON-NEXT:    cmp r7, #02224; CHECK-NEON-NEXT:    moveq r4, r72225; CHECK-NEON-NEXT:    movne r7, r12226; CHECK-NEON-NEXT:    bl __fixsfti2227; CHECK-NEON-NEXT:    subs r6, r2, #12228; CHECK-NEON-NEXT:    vmov.32 d1[0], r72229; CHECK-NEON-NEXT:    sbcs r6, r3, #02230; CHECK-NEON-NEXT:    movlt r8, r22231; CHECK-NEON-NEXT:    mov r2, #02232; CHECK-NEON-NEXT:    movwlt r2, #12233; CHECK-NEON-NEXT:    cmp r2, #02234; CHECK-NEON-NEXT:    moveq r3, r22235; CHECK-NEON-NEXT:    moveq r1, r22236; CHECK-NEON-NEXT:    movne r2, r02237; CHECK-NEON-NEXT:    rsbs r0, r2, #02238; CHECK-NEON-NEXT:    rscs r0, r1, #02239; CHECK-NEON-NEXT:    rscs r0, r8, #02240; CHECK-NEON-NEXT:    rscs r0, r3, #02241; CHECK-NEON-NEXT:    movwlt r5, #12242; CHECK-NEON-NEXT:    cmp r5, #02243; CHECK-NEON-NEXT:    moveq r2, r52244; CHECK-NEON-NEXT:    movne r5, r12245; CHECK-NEON-NEXT:    vmov.32 d0[0], r22246; CHECK-NEON-NEXT:    vmov.32 d1[1], r42247; CHECK-NEON-NEXT:    vmov.32 d0[1], r52248; CHECK-NEON-NEXT:    vpop {d8}2249; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, pc}2250;2251; CHECK-FP16-LABEL: ustest_f16i64:2252; CHECK-FP16:       @ %bb.0: @ %entry2253; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, lr}2254; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, lr}2255; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]2256; CHECK-FP16-NEXT:    vmov.u16 r5, d0[0]2257; CHECK-FP16-NEXT:    vmov s0, r02258; CHECK-FP16-NEXT:    bl __fixhfti2259; CHECK-FP16-NEXT:    mov r4, r12260; CHECK-FP16-NEXT:    subs r1, r2, #12261; CHECK-FP16-NEXT:    sbcs r1, r3, #02262; CHECK-FP16-NEXT:    mov r8, #12263; CHECK-FP16-NEXT:    mov r1, #02264; CHECK-FP16-NEXT:    movge r2, r82265; CHECK-FP16-NEXT:    movwlt r1, #12266; CHECK-FP16-NEXT:    cmp r1, #02267; CHECK-FP16-NEXT:    moveq r3, r12268; CHECK-FP16-NEXT:    moveq r4, r12269; CHECK-FP16-NEXT:    movne r1, r02270; CHECK-FP16-NEXT:    rsbs r0, r1, #02271; CHECK-FP16-NEXT:    rscs r0, r4, #02272; CHECK-FP16-NEXT:    vmov s0, r52273; CHECK-FP16-NEXT:    rscs r0, r2, #02274; CHECK-FP16-NEXT:    mov r7, #02275; CHECK-FP16-NEXT:    rscs r0, r3, #02276; CHECK-FP16-NEXT:    mov r5, #02277; CHECK-FP16-NEXT:    movwlt r7, #12278; CHECK-FP16-NEXT:    cmp r7, #02279; CHECK-FP16-NEXT:    moveq r4, r72280; CHECK-FP16-NEXT:    movne r7, r12281; CHECK-FP16-NEXT:    bl __fixhfti2282; CHECK-FP16-NEXT:    subs r6, r2, #12283; CHECK-FP16-NEXT:    vmov.32 d1[0], r72284; CHECK-FP16-NEXT:    sbcs r6, r3, #02285; CHECK-FP16-NEXT:    movlt r8, r22286; CHECK-FP16-NEXT:    mov r2, #02287; CHECK-FP16-NEXT:    movwlt r2, #12288; CHECK-FP16-NEXT:    cmp r2, #02289; CHECK-FP16-NEXT:    moveq r3, r22290; CHECK-FP16-NEXT:    moveq r1, r22291; CHECK-FP16-NEXT:    movne r2, r02292; CHECK-FP16-NEXT:    rsbs r0, r2, #02293; CHECK-FP16-NEXT:    rscs r0, r1, #02294; CHECK-FP16-NEXT:    rscs r0, r8, #02295; CHECK-FP16-NEXT:    rscs r0, r3, #02296; CHECK-FP16-NEXT:    movwlt r5, #12297; CHECK-FP16-NEXT:    cmp r5, #02298; CHECK-FP16-NEXT:    moveq r2, r52299; CHECK-FP16-NEXT:    movne r5, r12300; CHECK-FP16-NEXT:    vmov.32 d0[0], r22301; CHECK-FP16-NEXT:    vmov.32 d1[1], r42302; CHECK-FP16-NEXT:    vmov.32 d0[1], r52303; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, pc}2304entry:2305  %conv = fptosi <2 x half> %x to <2 x i128>2306  %0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>2307  %spec.store.select = select <2 x i1> %0, <2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>2308  %1 = icmp sgt <2 x i128> %spec.store.select, zeroinitializer2309  %spec.store.select7 = select <2 x i1> %1, <2 x i128> %spec.store.select, <2 x i128> zeroinitializer2310  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>2311  ret <2 x i64> %conv62312}2313 2314 2315 2316; i32 saturate2317 2318define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {2319; CHECK-LABEL: stest_f64i32_mm:2320; CHECK:       @ %bb.0: @ %entry2321; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}2322; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}2323; CHECK-NEXT:    .vsave {d8, d9}2324; CHECK-NEXT:    vpush {d8, d9}2325; CHECK-NEXT:    vorr q4, q0, q02326; CHECK-NEXT:    vmov r0, r1, d82327; CHECK-NEXT:    bl __aeabi_d2lz2328; CHECK-NEXT:    mov r4, r02329; CHECK-NEXT:    mov r8, r12330; CHECK-NEXT:    vmov r0, r1, d92331; CHECK-NEXT:    mvn r6, #-21474836482332; CHECK-NEXT:    subs r2, r4, r62333; CHECK-NEXT:    mov r5, #02334; CHECK-NEXT:    sbcs r2, r8, #02335; CHECK-NEXT:    mov r7, #02336; CHECK-NEXT:    movge r4, r62337; CHECK-NEXT:    movwlt r5, #12338; CHECK-NEXT:    bl __aeabi_d2lz2339; CHECK-NEXT:    subs r2, r0, r62340; CHECK-NEXT:    sbcs r2, r1, #02341; CHECK-NEXT:    movlt r6, r02342; CHECK-NEXT:    movwlt r7, #12343; CHECK-NEXT:    cmp r7, #02344; CHECK-NEXT:    mov r0, #-21474836482345; CHECK-NEXT:    movne r7, r12346; CHECK-NEXT:    cmp r5, #02347; CHECK-NEXT:    movne r5, r82348; CHECK-NEXT:    rsbs r2, r4, #-21474836482349; CHECK-NEXT:    mvn r1, #02350; CHECK-NEXT:    sbcs r2, r1, r52351; CHECK-NEXT:    movge r4, r02352; CHECK-NEXT:    rsbs r2, r6, #-21474836482353; CHECK-NEXT:    vmov.32 d0[0], r42354; CHECK-NEXT:    sbcs r1, r1, r72355; CHECK-NEXT:    movge r6, r02356; CHECK-NEXT:    vmov.32 d0[1], r62357; CHECK-NEXT:    vpop {d8, d9}2358; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, pc}2359entry:2360  %conv = fptosi <2 x double> %x to <2 x i64>2361  %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)2362  %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> <i64 -2147483648, i64 -2147483648>)2363  %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>2364  ret <2 x i32> %conv62365}2366 2367define <2 x i32> @utest_f64i32_mm(<2 x double> %x) {2368; CHECK-LABEL: utest_f64i32_mm:2369; CHECK:       @ %bb.0: @ %entry2370; CHECK-NEXT:    .save {r4, lr}2371; CHECK-NEXT:    push {r4, lr}2372; CHECK-NEXT:    .vsave {d8, d9}2373; CHECK-NEXT:    vpush {d8, d9}2374; CHECK-NEXT:    vorr q4, q0, q02375; CHECK-NEXT:    vmov r0, r1, d92376; CHECK-NEXT:    bl __aeabi_d2ulz2377; CHECK-NEXT:    mov r4, r12378; CHECK-NEXT:    vmov r2, r1, d82379; CHECK-NEXT:    vmov.32 d9[0], r02380; CHECK-NEXT:    mov r0, r22381; CHECK-NEXT:    bl __aeabi_d2ulz2382; CHECK-NEXT:    vmov.32 d8[0], r02383; CHECK-NEXT:    vmov.i64 q8, #0xffffffff2384; CHECK-NEXT:    vmov.32 d9[1], r42385; CHECK-NEXT:    vmov.32 d8[1], r12386; CHECK-NEXT:    vqsub.u64 q8, q4, q82387; CHECK-NEXT:    vsub.i64 q8, q4, q82388; CHECK-NEXT:    vmovn.i64 d0, q82389; CHECK-NEXT:    vpop {d8, d9}2390; CHECK-NEXT:    pop {r4, pc}2391entry:2392  %conv = fptoui <2 x double> %x to <2 x i64>2393  %spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)2394  %conv6 = trunc <2 x i64> %spec.store.select to <2 x i32>2395  ret <2 x i32> %conv62396}2397 2398define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {2399; CHECK-LABEL: ustest_f64i32_mm:2400; CHECK:       @ %bb.0: @ %entry2401; CHECK-NEXT:    .save {r4, r5, r6, lr}2402; CHECK-NEXT:    push {r4, r5, r6, lr}2403; CHECK-NEXT:    .vsave {d8, d9}2404; CHECK-NEXT:    vpush {d8, d9}2405; CHECK-NEXT:    vorr q4, q0, q02406; CHECK-NEXT:    vmov r0, r1, d82407; CHECK-NEXT:    bl __aeabi_d2lz2408; CHECK-NEXT:    vmov r2, r12, d92409; CHECK-NEXT:    mvn r4, #02410; CHECK-NEXT:    subs r5, r0, r42411; CHECK-NEXT:    mov r3, #02412; CHECK-NEXT:    sbcs r5, r1, #02413; CHECK-NEXT:    mov r6, #02414; CHECK-NEXT:    movge r0, r42415; CHECK-NEXT:    movwlt r3, #12416; CHECK-NEXT:    cmp r3, #02417; CHECK-NEXT:    mov r5, #02418; CHECK-NEXT:    movne r3, r12419; CHECK-NEXT:    rsbs r1, r0, #02420; CHECK-NEXT:    rscs r1, r3, #02421; CHECK-NEXT:    movwlt r6, #12422; CHECK-NEXT:    cmp r6, #02423; CHECK-NEXT:    movne r6, r02424; CHECK-NEXT:    mov r0, r22425; CHECK-NEXT:    mov r1, r122426; CHECK-NEXT:    bl __aeabi_d2lz2427; CHECK-NEXT:    subs r2, r0, r42428; CHECK-NEXT:    vmov.32 d0[0], r62429; CHECK-NEXT:    sbcs r2, r1, #02430; CHECK-NEXT:    movlt r4, r02431; CHECK-NEXT:    mov r0, #02432; CHECK-NEXT:    movwlt r0, #12433; CHECK-NEXT:    cmp r0, #02434; CHECK-NEXT:    movne r0, r12435; CHECK-NEXT:    rsbs r1, r4, #02436; CHECK-NEXT:    rscs r0, r0, #02437; CHECK-NEXT:    movwlt r5, #12438; CHECK-NEXT:    cmp r5, #02439; CHECK-NEXT:    movne r5, r42440; CHECK-NEXT:    vmov.32 d0[1], r52441; CHECK-NEXT:    vpop {d8, d9}2442; CHECK-NEXT:    pop {r4, r5, r6, pc}2443entry:2444  %conv = fptosi <2 x double> %x to <2 x i64>2445  %spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)2446  %spec.store.select7 = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %spec.store.select, <2 x i64> zeroinitializer)2447  %conv6 = trunc <2 x i64> %spec.store.select7 to <2 x i32>2448  ret <2 x i32> %conv62449}2450 2451define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {2452; CHECK-LABEL: stest_f32i32_mm:2453; CHECK:       @ %bb.0: @ %entry2454; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}2455; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}2456; CHECK-NEXT:    .pad #42457; CHECK-NEXT:    sub sp, sp, #42458; CHECK-NEXT:    .vsave {d8, d9}2459; CHECK-NEXT:    vpush {d8, d9}2460; CHECK-NEXT:    .pad #82461; CHECK-NEXT:    sub sp, sp, #82462; CHECK-NEXT:    vorr q4, q0, q02463; CHECK-NEXT:    vmov r0, s192464; CHECK-NEXT:    bl __aeabi_f2lz2465; CHECK-NEXT:    vmov r2, s182466; CHECK-NEXT:    mov r11, r02467; CHECK-NEXT:    vmov r0, s172468; CHECK-NEXT:    mvn r6, #-21474836482469; CHECK-NEXT:    mov r3, #-21474836482470; CHECK-NEXT:    mvn r10, #02471; CHECK-NEXT:    vmov r7, s162472; CHECK-NEXT:    mov r4, #02473; CHECK-NEXT:    str r2, [sp, #4] @ 4-byte Spill2474; CHECK-NEXT:    subs r2, r11, r62475; CHECK-NEXT:    sbcs r2, r1, #02476; CHECK-NEXT:    mov r2, #02477; CHECK-NEXT:    movge r11, r62478; CHECK-NEXT:    movwlt r2, #12479; CHECK-NEXT:    cmp r2, #02480; CHECK-NEXT:    movne r2, r12481; CHECK-NEXT:    rsbs r1, r11, #-21474836482482; CHECK-NEXT:    sbcs r1, r10, r22483; CHECK-NEXT:    movge r11, r32484; CHECK-NEXT:    bl __aeabi_f2lz2485; CHECK-NEXT:    mov r5, r02486; CHECK-NEXT:    subs r0, r0, r62487; CHECK-NEXT:    sbcs r0, r1, #02488; CHECK-NEXT:    mov r9, #02489; CHECK-NEXT:    mov r0, r72490; CHECK-NEXT:    movge r5, r62491; CHECK-NEXT:    movwlt r9, #12492; CHECK-NEXT:    cmp r9, #02493; CHECK-NEXT:    movne r9, r12494; CHECK-NEXT:    bl __aeabi_f2lz2495; CHECK-NEXT:    mov r7, r02496; CHECK-NEXT:    subs r0, r0, r62497; CHECK-NEXT:    sbcs r0, r1, #02498; CHECK-NEXT:    mov r8, #02499; CHECK-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload2500; CHECK-NEXT:    movge r7, r62501; CHECK-NEXT:    movwlt r8, #12502; CHECK-NEXT:    cmp r8, #02503; CHECK-NEXT:    movne r8, r12504; CHECK-NEXT:    bl __aeabi_f2lz2505; CHECK-NEXT:    subs r2, r0, r62506; CHECK-NEXT:    sbcs r2, r1, #02507; CHECK-NEXT:    movlt r6, r02508; CHECK-NEXT:    movwlt r4, #12509; CHECK-NEXT:    cmp r4, #02510; CHECK-NEXT:    movne r4, r12511; CHECK-NEXT:    rsbs r0, r6, #-21474836482512; CHECK-NEXT:    sbcs r0, r10, r42513; CHECK-NEXT:    mov r1, #-21474836482514; CHECK-NEXT:    movge r6, r12515; CHECK-NEXT:    rsbs r0, r7, #-21474836482516; CHECK-NEXT:    sbcs r0, r10, r82517; CHECK-NEXT:    vmov.32 d1[0], r62518; CHECK-NEXT:    movge r7, r12519; CHECK-NEXT:    rsbs r0, r5, #-21474836482520; CHECK-NEXT:    vmov.32 d0[0], r72521; CHECK-NEXT:    sbcs r0, r10, r92522; CHECK-NEXT:    movge r5, r12523; CHECK-NEXT:    vmov.32 d1[1], r112524; CHECK-NEXT:    vmov.32 d0[1], r52525; CHECK-NEXT:    add sp, sp, #82526; CHECK-NEXT:    vpop {d8, d9}2527; CHECK-NEXT:    add sp, sp, #42528; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}2529entry:2530  %conv = fptosi <4 x float> %x to <4 x i64>2531  %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)2532  %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)2533  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>2534  ret <4 x i32> %conv62535}2536 2537define <4 x i32> @utest_f32i32_mm(<4 x float> %x) {2538; CHECK-LABEL: utest_f32i32_mm:2539; CHECK:       @ %bb.0: @ %entry2540; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}2541; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}2542; CHECK-NEXT:    .vsave {d8, d9, d10, d11}2543; CHECK-NEXT:    vpush {d8, d9, d10, d11}2544; CHECK-NEXT:    vorr q4, q0, q02545; CHECK-NEXT:    vmov r0, s172546; CHECK-NEXT:    bl __aeabi_f2ulz2547; CHECK-NEXT:    mov r4, r12548; CHECK-NEXT:    vmov r1, s182549; CHECK-NEXT:    vmov r5, s192550; CHECK-NEXT:    vmov r6, s162551; CHECK-NEXT:    vmov.32 d9[0], r02552; CHECK-NEXT:    mov r0, r12553; CHECK-NEXT:    bl __aeabi_f2ulz2554; CHECK-NEXT:    vmov.32 d10[0], r02555; CHECK-NEXT:    mov r0, r52556; CHECK-NEXT:    mov r7, r12557; CHECK-NEXT:    bl __aeabi_f2ulz2558; CHECK-NEXT:    vmov.32 d11[0], r02559; CHECK-NEXT:    mov r0, r62560; CHECK-NEXT:    mov r5, r12561; CHECK-NEXT:    bl __aeabi_f2ulz2562; CHECK-NEXT:    vmov.32 d8[0], r02563; CHECK-NEXT:    vmov.i64 q8, #0xffffffff2564; CHECK-NEXT:    vmov.32 d11[1], r52565; CHECK-NEXT:    vmov.32 d9[1], r42566; CHECK-NEXT:    vmov.32 d10[1], r72567; CHECK-NEXT:    vmov.32 d8[1], r12568; CHECK-NEXT:    vqsub.u64 q9, q5, q82569; CHECK-NEXT:    vqsub.u64 q8, q4, q82570; CHECK-NEXT:    vsub.i64 q9, q5, q92571; CHECK-NEXT:    vsub.i64 q8, q4, q82572; CHECK-NEXT:    vmovn.i64 d1, q92573; CHECK-NEXT:    vmovn.i64 d0, q82574; CHECK-NEXT:    vpop {d8, d9, d10, d11}2575; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}2576entry:2577  %conv = fptoui <4 x float> %x to <4 x i64>2578  %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)2579  %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>2580  ret <4 x i32> %conv62581}2582 2583define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {2584; CHECK-LABEL: ustest_f32i32_mm:2585; CHECK:       @ %bb.0: @ %entry2586; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}2587; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}2588; CHECK-NEXT:    .vsave {d8, d9}2589; CHECK-NEXT:    vpush {d8, d9}2590; CHECK-NEXT:    vorr q4, q0, q02591; CHECK-NEXT:    vmov r0, s192592; CHECK-NEXT:    bl __aeabi_f2lz2593; CHECK-NEXT:    vmov r2, s162594; CHECK-NEXT:    mvn r6, #02595; CHECK-NEXT:    subs r3, r0, r62596; CHECK-NEXT:    mov r4, #02597; CHECK-NEXT:    sbcs r3, r1, #02598; CHECK-NEXT:    vmov r8, s172599; CHECK-NEXT:    mov r3, #02600; CHECK-NEXT:    movge r0, r62601; CHECK-NEXT:    movwlt r3, #12602; CHECK-NEXT:    cmp r3, #02603; CHECK-NEXT:    movne r3, r12604; CHECK-NEXT:    rsbs r1, r0, #02605; CHECK-NEXT:    rscs r1, r3, #02606; CHECK-NEXT:    vmov r9, s182607; CHECK-NEXT:    movwlt r4, #12608; CHECK-NEXT:    cmp r4, #02609; CHECK-NEXT:    movne r4, r02610; CHECK-NEXT:    mov r10, #02611; CHECK-NEXT:    mov r0, r22612; CHECK-NEXT:    bl __aeabi_f2lz2613; CHECK-NEXT:    subs r2, r0, r62614; CHECK-NEXT:    mov r5, #02615; CHECK-NEXT:    sbcs r2, r1, #02616; CHECK-NEXT:    mov r2, #02617; CHECK-NEXT:    movge r0, r62618; CHECK-NEXT:    movwlt r2, #12619; CHECK-NEXT:    cmp r2, #02620; CHECK-NEXT:    movne r2, r12621; CHECK-NEXT:    rsbs r1, r0, #02622; CHECK-NEXT:    rscs r1, r2, #02623; CHECK-NEXT:    movwlt r5, #12624; CHECK-NEXT:    cmp r5, #02625; CHECK-NEXT:    movne r5, r02626; CHECK-NEXT:    mov r0, r92627; CHECK-NEXT:    bl __aeabi_f2lz2628; CHECK-NEXT:    subs r2, r0, r62629; CHECK-NEXT:    mov r7, #02630; CHECK-NEXT:    sbcs r2, r1, #02631; CHECK-NEXT:    mov r2, #02632; CHECK-NEXT:    movge r0, r62633; CHECK-NEXT:    movwlt r2, #12634; CHECK-NEXT:    cmp r2, #02635; CHECK-NEXT:    movne r2, r12636; CHECK-NEXT:    rsbs r1, r0, #02637; CHECK-NEXT:    rscs r1, r2, #02638; CHECK-NEXT:    movwlt r7, #12639; CHECK-NEXT:    cmp r7, #02640; CHECK-NEXT:    movne r7, r02641; CHECK-NEXT:    mov r0, r82642; CHECK-NEXT:    bl __aeabi_f2lz2643; CHECK-NEXT:    subs r2, r0, r62644; CHECK-NEXT:    vmov.32 d1[0], r72645; CHECK-NEXT:    sbcs r2, r1, #02646; CHECK-NEXT:    movlt r6, r02647; CHECK-NEXT:    mov r0, #02648; CHECK-NEXT:    movwlt r0, #12649; CHECK-NEXT:    cmp r0, #02650; CHECK-NEXT:    movne r0, r12651; CHECK-NEXT:    rsbs r1, r6, #02652; CHECK-NEXT:    rscs r0, r0, #02653; CHECK-NEXT:    vmov.32 d0[0], r52654; CHECK-NEXT:    movwlt r10, #12655; CHECK-NEXT:    cmp r10, #02656; CHECK-NEXT:    vmov.32 d1[1], r42657; CHECK-NEXT:    movne r10, r62658; CHECK-NEXT:    vmov.32 d0[1], r102659; CHECK-NEXT:    vpop {d8, d9}2660; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}2661entry:2662  %conv = fptosi <4 x float> %x to <4 x i64>2663  %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)2664  %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)2665  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>2666  ret <4 x i32> %conv62667}2668 2669define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {2670; CHECK-NEON-LABEL: stest_f16i32_mm:2671; CHECK-NEON:       @ %bb.0: @ %entry2672; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}2673; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}2674; CHECK-NEON-NEXT:    .pad #42675; CHECK-NEON-NEXT:    sub sp, sp, #42676; CHECK-NEON-NEXT:    .vsave {d8, d9, d10}2677; CHECK-NEON-NEXT:    vpush {d8, d9, d10}2678; CHECK-NEON-NEXT:    .pad #82679; CHECK-NEON-NEXT:    sub sp, sp, #82680; CHECK-NEON-NEXT:    vmov r0, s32681; CHECK-NEON-NEXT:    vmov.f32 s16, s22682; CHECK-NEON-NEXT:    vmov.f32 s18, s12683; CHECK-NEON-NEXT:    vmov.f32 s20, s02684; CHECK-NEON-NEXT:    bl __aeabi_h2f2685; CHECK-NEON-NEXT:    bl __aeabi_f2lz2686; CHECK-NEON-NEXT:    vmov r2, s162687; CHECK-NEON-NEXT:    mov r11, r02688; CHECK-NEON-NEXT:    vmov r0, s182689; CHECK-NEON-NEXT:    mvn r6, #-21474836482690; CHECK-NEON-NEXT:    mov r3, #-21474836482691; CHECK-NEON-NEXT:    mvn r10, #02692; CHECK-NEON-NEXT:    vmov r7, s202693; CHECK-NEON-NEXT:    mov r4, #02694; CHECK-NEON-NEXT:    str r2, [sp, #4] @ 4-byte Spill2695; CHECK-NEON-NEXT:    subs r2, r11, r62696; CHECK-NEON-NEXT:    sbcs r2, r1, #02697; CHECK-NEON-NEXT:    mov r2, #02698; CHECK-NEON-NEXT:    movge r11, r62699; CHECK-NEON-NEXT:    movwlt r2, #12700; CHECK-NEON-NEXT:    cmp r2, #02701; CHECK-NEON-NEXT:    movne r2, r12702; CHECK-NEON-NEXT:    rsbs r1, r11, #-21474836482703; CHECK-NEON-NEXT:    sbcs r1, r10, r22704; CHECK-NEON-NEXT:    movge r11, r32705; CHECK-NEON-NEXT:    bl __aeabi_h2f2706; CHECK-NEON-NEXT:    bl __aeabi_f2lz2707; CHECK-NEON-NEXT:    mov r5, r02708; CHECK-NEON-NEXT:    subs r0, r0, r62709; CHECK-NEON-NEXT:    sbcs r0, r1, #02710; CHECK-NEON-NEXT:    mov r8, #02711; CHECK-NEON-NEXT:    mov r0, r72712; CHECK-NEON-NEXT:    movge r5, r62713; CHECK-NEON-NEXT:    movwlt r8, #12714; CHECK-NEON-NEXT:    cmp r8, #02715; CHECK-NEON-NEXT:    movne r8, r12716; CHECK-NEON-NEXT:    bl __aeabi_h2f2717; CHECK-NEON-NEXT:    bl __aeabi_f2lz2718; CHECK-NEON-NEXT:    mov r7, r02719; CHECK-NEON-NEXT:    subs r0, r0, r62720; CHECK-NEON-NEXT:    sbcs r0, r1, #02721; CHECK-NEON-NEXT:    mov r9, #02722; CHECK-NEON-NEXT:    ldr r0, [sp, #4] @ 4-byte Reload2723; CHECK-NEON-NEXT:    movge r7, r62724; CHECK-NEON-NEXT:    movwlt r9, #12725; CHECK-NEON-NEXT:    cmp r9, #02726; CHECK-NEON-NEXT:    movne r9, r12727; CHECK-NEON-NEXT:    bl __aeabi_h2f2728; CHECK-NEON-NEXT:    bl __aeabi_f2lz2729; CHECK-NEON-NEXT:    subs r2, r0, r62730; CHECK-NEON-NEXT:    sbcs r2, r1, #02731; CHECK-NEON-NEXT:    movlt r6, r02732; CHECK-NEON-NEXT:    movwlt r4, #12733; CHECK-NEON-NEXT:    cmp r4, #02734; CHECK-NEON-NEXT:    movne r4, r12735; CHECK-NEON-NEXT:    rsbs r0, r6, #-21474836482736; CHECK-NEON-NEXT:    sbcs r0, r10, r42737; CHECK-NEON-NEXT:    mov r1, #-21474836482738; CHECK-NEON-NEXT:    movge r6, r12739; CHECK-NEON-NEXT:    rsbs r0, r7, #-21474836482740; CHECK-NEON-NEXT:    sbcs r0, r10, r92741; CHECK-NEON-NEXT:    vmov.32 d1[0], r62742; CHECK-NEON-NEXT:    movge r7, r12743; CHECK-NEON-NEXT:    rsbs r0, r5, #-21474836482744; CHECK-NEON-NEXT:    vmov.32 d0[0], r72745; CHECK-NEON-NEXT:    sbcs r0, r10, r82746; CHECK-NEON-NEXT:    movge r5, r12747; CHECK-NEON-NEXT:    vmov.32 d1[1], r112748; CHECK-NEON-NEXT:    vmov.32 d0[1], r52749; CHECK-NEON-NEXT:    add sp, sp, #82750; CHECK-NEON-NEXT:    vpop {d8, d9, d10}2751; CHECK-NEON-NEXT:    add sp, sp, #42752; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}2753;2754; CHECK-FP16-LABEL: stest_f16i32_mm:2755; CHECK-FP16:       @ %bb.0: @ %entry2756; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}2757; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, r11, lr}2758; CHECK-FP16-NEXT:    .pad #42759; CHECK-FP16-NEXT:    sub sp, sp, #42760; CHECK-FP16-NEXT:    .vsave {d8, d9}2761; CHECK-FP16-NEXT:    vpush {d8, d9}2762; CHECK-FP16-NEXT:    vmov.u16 r0, d0[3]2763; CHECK-FP16-NEXT:    vmov.u16 r4, d0[2]2764; CHECK-FP16-NEXT:    vmov.u16 r5, d0[0]2765; CHECK-FP16-NEXT:    vmov.u16 r6, d0[1]2766; CHECK-FP16-NEXT:    vmov s0, r02767; CHECK-FP16-NEXT:    bl __fixhfdi2768; CHECK-FP16-NEXT:    mov r10, r02769; CHECK-FP16-NEXT:    mvn r7, #-21474836482770; CHECK-FP16-NEXT:    subs r0, r0, r72771; CHECK-FP16-NEXT:    vmov s0, r62772; CHECK-FP16-NEXT:    sbcs r0, r1, #02773; CHECK-FP16-NEXT:    mov r2, #-21474836482774; CHECK-FP16-NEXT:    mov r0, #02775; CHECK-FP16-NEXT:    movge r10, r72776; CHECK-FP16-NEXT:    movwlt r0, #12777; CHECK-FP16-NEXT:    cmp r0, #02778; CHECK-FP16-NEXT:    movne r0, r12779; CHECK-FP16-NEXT:    rsbs r1, r10, #-21474836482780; CHECK-FP16-NEXT:    mvn r9, #02781; CHECK-FP16-NEXT:    sbcs r0, r9, r02782; CHECK-FP16-NEXT:    vmov s16, r42783; CHECK-FP16-NEXT:    mov r11, #02784; CHECK-FP16-NEXT:    vmov s18, r52785; CHECK-FP16-NEXT:    movge r10, r22786; CHECK-FP16-NEXT:    bl __fixhfdi2787; CHECK-FP16-NEXT:    vmov.f32 s0, s182788; CHECK-FP16-NEXT:    mov r5, r02789; CHECK-FP16-NEXT:    subs r0, r0, r72790; CHECK-FP16-NEXT:    mov r4, #02791; CHECK-FP16-NEXT:    sbcs r0, r1, #02792; CHECK-FP16-NEXT:    movge r5, r72793; CHECK-FP16-NEXT:    movwlt r4, #12794; CHECK-FP16-NEXT:    cmp r4, #02795; CHECK-FP16-NEXT:    movne r4, r12796; CHECK-FP16-NEXT:    bl __fixhfdi2797; CHECK-FP16-NEXT:    vmov.f32 s0, s162798; CHECK-FP16-NEXT:    mov r6, r02799; CHECK-FP16-NEXT:    subs r0, r0, r72800; CHECK-FP16-NEXT:    mov r8, #02801; CHECK-FP16-NEXT:    sbcs r0, r1, #02802; CHECK-FP16-NEXT:    movge r6, r72803; CHECK-FP16-NEXT:    movwlt r8, #12804; CHECK-FP16-NEXT:    cmp r8, #02805; CHECK-FP16-NEXT:    movne r8, r12806; CHECK-FP16-NEXT:    bl __fixhfdi2807; CHECK-FP16-NEXT:    subs r2, r0, r72808; CHECK-FP16-NEXT:    sbcs r2, r1, #02809; CHECK-FP16-NEXT:    movlt r7, r02810; CHECK-FP16-NEXT:    movwlt r11, #12811; CHECK-FP16-NEXT:    cmp r11, #02812; CHECK-FP16-NEXT:    movne r11, r12813; CHECK-FP16-NEXT:    rsbs r0, r7, #-21474836482814; CHECK-FP16-NEXT:    sbcs r0, r9, r112815; CHECK-FP16-NEXT:    mov r1, #-21474836482816; CHECK-FP16-NEXT:    movge r7, r12817; CHECK-FP16-NEXT:    rsbs r0, r6, #-21474836482818; CHECK-FP16-NEXT:    sbcs r0, r9, r82819; CHECK-FP16-NEXT:    vmov.32 d1[0], r72820; CHECK-FP16-NEXT:    movge r6, r12821; CHECK-FP16-NEXT:    rsbs r0, r5, #-21474836482822; CHECK-FP16-NEXT:    vmov.32 d0[0], r62823; CHECK-FP16-NEXT:    sbcs r0, r9, r42824; CHECK-FP16-NEXT:    movge r5, r12825; CHECK-FP16-NEXT:    vmov.32 d1[1], r102826; CHECK-FP16-NEXT:    vmov.32 d0[1], r52827; CHECK-FP16-NEXT:    vpop {d8, d9}2828; CHECK-FP16-NEXT:    add sp, sp, #42829; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}2830entry:2831  %conv = fptosi <4 x half> %x to <4 x i64>2832  %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)2833  %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)2834  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>2835  ret <4 x i32> %conv62836}2837 2838define <4 x i32> @utest_f16i32_mm(<4 x half> %x) {2839; CHECK-NEON-LABEL: utest_f16i32_mm:2840; CHECK-NEON:       @ %bb.0: @ %entry2841; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}2842; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}2843; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11}2844; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11}2845; CHECK-NEON-NEXT:    vmov r0, s12846; CHECK-NEON-NEXT:    vmov.f32 s16, s32847; CHECK-NEON-NEXT:    vmov.f32 s18, s22848; CHECK-NEON-NEXT:    vmov.f32 s20, s02849; CHECK-NEON-NEXT:    bl __aeabi_h2f2850; CHECK-NEON-NEXT:    bl __aeabi_f2ulz2851; CHECK-NEON-NEXT:    mov r4, r12852; CHECK-NEON-NEXT:    vmov r1, s182853; CHECK-NEON-NEXT:    vmov r6, s162854; CHECK-NEON-NEXT:    vmov.32 d9[0], r02855; CHECK-NEON-NEXT:    vmov r7, s202856; CHECK-NEON-NEXT:    mov r0, r12857; CHECK-NEON-NEXT:    bl __aeabi_h2f2858; CHECK-NEON-NEXT:    bl __aeabi_f2ulz2859; CHECK-NEON-NEXT:    vmov.32 d10[0], r02860; CHECK-NEON-NEXT:    mov r0, r62861; CHECK-NEON-NEXT:    mov r5, r12862; CHECK-NEON-NEXT:    bl __aeabi_h2f2863; CHECK-NEON-NEXT:    bl __aeabi_f2ulz2864; CHECK-NEON-NEXT:    vmov.32 d11[0], r02865; CHECK-NEON-NEXT:    mov r0, r72866; CHECK-NEON-NEXT:    mov r6, r12867; CHECK-NEON-NEXT:    bl __aeabi_h2f2868; CHECK-NEON-NEXT:    bl __aeabi_f2ulz2869; CHECK-NEON-NEXT:    vmov.32 d8[0], r02870; CHECK-NEON-NEXT:    vmov.i64 q8, #0xffffffff2871; CHECK-NEON-NEXT:    vmov.32 d11[1], r62872; CHECK-NEON-NEXT:    vmov.32 d9[1], r42873; CHECK-NEON-NEXT:    vmov.32 d10[1], r52874; CHECK-NEON-NEXT:    vmov.32 d8[1], r12875; CHECK-NEON-NEXT:    vqsub.u64 q9, q5, q82876; CHECK-NEON-NEXT:    vqsub.u64 q8, q4, q82877; CHECK-NEON-NEXT:    vsub.i64 q9, q5, q92878; CHECK-NEON-NEXT:    vsub.i64 q8, q4, q82879; CHECK-NEON-NEXT:    vmovn.i64 d1, q92880; CHECK-NEON-NEXT:    vmovn.i64 d0, q82881; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11}2882; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}2883;2884; CHECK-FP16-LABEL: utest_f16i32_mm:2885; CHECK-FP16:       @ %bb.0: @ %entry2886; CHECK-FP16-NEXT:    .save {r4, r5, r6, lr}2887; CHECK-FP16-NEXT:    push {r4, r5, r6, lr}2888; CHECK-FP16-NEXT:    .vsave {d10, d11, d12, d13}2889; CHECK-FP16-NEXT:    vpush {d10, d11, d12, d13}2890; CHECK-FP16-NEXT:    .vsave {d8}2891; CHECK-FP16-NEXT:    vpush {d8}2892; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]2893; CHECK-FP16-NEXT:    vorr d8, d0, d02894; CHECK-FP16-NEXT:    vmov.u16 r6, d0[3]2895; CHECK-FP16-NEXT:    vmov s0, r02896; CHECK-FP16-NEXT:    bl __fixunshfdi2897; CHECK-FP16-NEXT:    mov r4, r12898; CHECK-FP16-NEXT:    vmov.u16 r1, d8[2]2899; CHECK-FP16-NEXT:    vmov.32 d11[0], r02900; CHECK-FP16-NEXT:    vmov s0, r12901; CHECK-FP16-NEXT:    bl __fixunshfdi2902; CHECK-FP16-NEXT:    vmov s0, r62903; CHECK-FP16-NEXT:    mov r5, r12904; CHECK-FP16-NEXT:    vmov.32 d12[0], r02905; CHECK-FP16-NEXT:    bl __fixunshfdi2906; CHECK-FP16-NEXT:    mov r6, r12907; CHECK-FP16-NEXT:    vmov.u16 r1, d8[0]2908; CHECK-FP16-NEXT:    vmov.32 d13[0], r02909; CHECK-FP16-NEXT:    vmov s0, r12910; CHECK-FP16-NEXT:    bl __fixunshfdi2911; CHECK-FP16-NEXT:    vmov.32 d10[0], r02912; CHECK-FP16-NEXT:    vmov.i64 q8, #0xffffffff2913; CHECK-FP16-NEXT:    vmov.32 d13[1], r62914; CHECK-FP16-NEXT:    vmov.32 d11[1], r42915; CHECK-FP16-NEXT:    vmov.32 d12[1], r52916; CHECK-FP16-NEXT:    vmov.32 d10[1], r12917; CHECK-FP16-NEXT:    vqsub.u64 q9, q6, q82918; CHECK-FP16-NEXT:    vqsub.u64 q8, q5, q82919; CHECK-FP16-NEXT:    vsub.i64 q9, q6, q92920; CHECK-FP16-NEXT:    vsub.i64 q8, q5, q82921; CHECK-FP16-NEXT:    vmovn.i64 d1, q92922; CHECK-FP16-NEXT:    vmovn.i64 d0, q82923; CHECK-FP16-NEXT:    vpop {d8}2924; CHECK-FP16-NEXT:    vpop {d10, d11, d12, d13}2925; CHECK-FP16-NEXT:    pop {r4, r5, r6, pc}2926entry:2927  %conv = fptoui <4 x half> %x to <4 x i64>2928  %spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)2929  %conv6 = trunc <4 x i64> %spec.store.select to <4 x i32>2930  ret <4 x i32> %conv62931}2932 2933define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {2934; CHECK-NEON-LABEL: ustest_f16i32_mm:2935; CHECK-NEON:       @ %bb.0: @ %entry2936; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}2937; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}2938; CHECK-NEON-NEXT:    .vsave {d8, d9, d10}2939; CHECK-NEON-NEXT:    vpush {d8, d9, d10}2940; CHECK-NEON-NEXT:    vmov r0, s32941; CHECK-NEON-NEXT:    vmov.f32 s16, s22942; CHECK-NEON-NEXT:    vmov.f32 s18, s12943; CHECK-NEON-NEXT:    vmov.f32 s20, s02944; CHECK-NEON-NEXT:    bl __aeabi_h2f2945; CHECK-NEON-NEXT:    bl __aeabi_f2lz2946; CHECK-NEON-NEXT:    vmov r2, s202947; CHECK-NEON-NEXT:    mvn r6, #02948; CHECK-NEON-NEXT:    subs r3, r0, r62949; CHECK-NEON-NEXT:    mov r4, #02950; CHECK-NEON-NEXT:    sbcs r3, r1, #02951; CHECK-NEON-NEXT:    vmov r8, s182952; CHECK-NEON-NEXT:    mov r3, #02953; CHECK-NEON-NEXT:    movge r0, r62954; CHECK-NEON-NEXT:    movwlt r3, #12955; CHECK-NEON-NEXT:    cmp r3, #02956; CHECK-NEON-NEXT:    movne r3, r12957; CHECK-NEON-NEXT:    rsbs r1, r0, #02958; CHECK-NEON-NEXT:    rscs r1, r3, #02959; CHECK-NEON-NEXT:    vmov r9, s162960; CHECK-NEON-NEXT:    movwlt r4, #12961; CHECK-NEON-NEXT:    cmp r4, #02962; CHECK-NEON-NEXT:    movne r4, r02963; CHECK-NEON-NEXT:    mov r10, #02964; CHECK-NEON-NEXT:    mov r0, r22965; CHECK-NEON-NEXT:    bl __aeabi_h2f2966; CHECK-NEON-NEXT:    bl __aeabi_f2lz2967; CHECK-NEON-NEXT:    subs r2, r0, r62968; CHECK-NEON-NEXT:    mov r5, #02969; CHECK-NEON-NEXT:    sbcs r2, r1, #02970; CHECK-NEON-NEXT:    mov r2, #02971; CHECK-NEON-NEXT:    movge r0, r62972; CHECK-NEON-NEXT:    movwlt r2, #12973; CHECK-NEON-NEXT:    cmp r2, #02974; CHECK-NEON-NEXT:    movne r2, r12975; CHECK-NEON-NEXT:    rsbs r1, r0, #02976; CHECK-NEON-NEXT:    rscs r1, r2, #02977; CHECK-NEON-NEXT:    movwlt r5, #12978; CHECK-NEON-NEXT:    cmp r5, #02979; CHECK-NEON-NEXT:    movne r5, r02980; CHECK-NEON-NEXT:    mov r0, r92981; CHECK-NEON-NEXT:    bl __aeabi_h2f2982; CHECK-NEON-NEXT:    bl __aeabi_f2lz2983; CHECK-NEON-NEXT:    subs r2, r0, r62984; CHECK-NEON-NEXT:    mov r7, #02985; CHECK-NEON-NEXT:    sbcs r2, r1, #02986; CHECK-NEON-NEXT:    mov r2, #02987; CHECK-NEON-NEXT:    movge r0, r62988; CHECK-NEON-NEXT:    movwlt r2, #12989; CHECK-NEON-NEXT:    cmp r2, #02990; CHECK-NEON-NEXT:    movne r2, r12991; CHECK-NEON-NEXT:    rsbs r1, r0, #02992; CHECK-NEON-NEXT:    rscs r1, r2, #02993; CHECK-NEON-NEXT:    movwlt r7, #12994; CHECK-NEON-NEXT:    cmp r7, #02995; CHECK-NEON-NEXT:    movne r7, r02996; CHECK-NEON-NEXT:    mov r0, r82997; CHECK-NEON-NEXT:    bl __aeabi_h2f2998; CHECK-NEON-NEXT:    bl __aeabi_f2lz2999; CHECK-NEON-NEXT:    subs r2, r0, r63000; CHECK-NEON-NEXT:    vmov.32 d1[0], r73001; CHECK-NEON-NEXT:    sbcs r2, r1, #03002; CHECK-NEON-NEXT:    movlt r6, r03003; CHECK-NEON-NEXT:    mov r0, #03004; CHECK-NEON-NEXT:    movwlt r0, #13005; CHECK-NEON-NEXT:    cmp r0, #03006; CHECK-NEON-NEXT:    movne r0, r13007; CHECK-NEON-NEXT:    rsbs r1, r6, #03008; CHECK-NEON-NEXT:    rscs r0, r0, #03009; CHECK-NEON-NEXT:    vmov.32 d0[0], r53010; CHECK-NEON-NEXT:    movwlt r10, #13011; CHECK-NEON-NEXT:    cmp r10, #03012; CHECK-NEON-NEXT:    vmov.32 d1[1], r43013; CHECK-NEON-NEXT:    movne r10, r63014; CHECK-NEON-NEXT:    vmov.32 d0[1], r103015; CHECK-NEON-NEXT:    vpop {d8, d9, d10}3016; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}3017;3018; CHECK-FP16-LABEL: ustest_f16i32_mm:3019; CHECK-FP16:       @ %bb.0: @ %entry3020; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, lr}3021; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, lr}3022; CHECK-FP16-NEXT:    .vsave {d8, d9}3023; CHECK-FP16-NEXT:    vpush {d8, d9}3024; CHECK-FP16-NEXT:    vmov.u16 r0, d0[3]3025; CHECK-FP16-NEXT:    vorr d8, d0, d03026; CHECK-FP16-NEXT:    vmov.u16 r5, d0[0]3027; CHECK-FP16-NEXT:    vmov s0, r03028; CHECK-FP16-NEXT:    bl __fixhfdi3029; CHECK-FP16-NEXT:    vmov.u16 r2, d8[1]3030; CHECK-FP16-NEXT:    mvn r4, #03031; CHECK-FP16-NEXT:    vmov.u16 r3, d8[2]3032; CHECK-FP16-NEXT:    vmov s0, r53033; CHECK-FP16-NEXT:    mov r6, #03034; CHECK-FP16-NEXT:    mov r8, #03035; CHECK-FP16-NEXT:    vmov s16, r23036; CHECK-FP16-NEXT:    subs r2, r0, r43037; CHECK-FP16-NEXT:    sbcs r2, r1, #03038; CHECK-FP16-NEXT:    vmov s18, r33039; CHECK-FP16-NEXT:    mov r2, #03040; CHECK-FP16-NEXT:    movge r0, r43041; CHECK-FP16-NEXT:    movwlt r2, #13042; CHECK-FP16-NEXT:    cmp r2, #03043; CHECK-FP16-NEXT:    movne r2, r13044; CHECK-FP16-NEXT:    rsbs r1, r0, #03045; CHECK-FP16-NEXT:    rscs r1, r2, #03046; CHECK-FP16-NEXT:    movwlt r6, #13047; CHECK-FP16-NEXT:    cmp r6, #03048; CHECK-FP16-NEXT:    movne r6, r03049; CHECK-FP16-NEXT:    bl __fixhfdi3050; CHECK-FP16-NEXT:    subs r2, r0, r43051; CHECK-FP16-NEXT:    vmov.f32 s0, s183052; CHECK-FP16-NEXT:    sbcs r2, r1, #03053; CHECK-FP16-NEXT:    mov r7, #03054; CHECK-FP16-NEXT:    mov r2, #03055; CHECK-FP16-NEXT:    movge r0, r43056; CHECK-FP16-NEXT:    movwlt r2, #13057; CHECK-FP16-NEXT:    cmp r2, #03058; CHECK-FP16-NEXT:    movne r2, r13059; CHECK-FP16-NEXT:    rsbs r1, r0, #03060; CHECK-FP16-NEXT:    rscs r1, r2, #03061; CHECK-FP16-NEXT:    movwlt r7, #13062; CHECK-FP16-NEXT:    cmp r7, #03063; CHECK-FP16-NEXT:    movne r7, r03064; CHECK-FP16-NEXT:    bl __fixhfdi3065; CHECK-FP16-NEXT:    subs r2, r0, r43066; CHECK-FP16-NEXT:    vmov.f32 s0, s163067; CHECK-FP16-NEXT:    sbcs r2, r1, #03068; CHECK-FP16-NEXT:    mov r5, #03069; CHECK-FP16-NEXT:    mov r2, #03070; CHECK-FP16-NEXT:    movge r0, r43071; CHECK-FP16-NEXT:    movwlt r2, #13072; CHECK-FP16-NEXT:    cmp r2, #03073; CHECK-FP16-NEXT:    movne r2, r13074; CHECK-FP16-NEXT:    rsbs r1, r0, #03075; CHECK-FP16-NEXT:    rscs r1, r2, #03076; CHECK-FP16-NEXT:    movwlt r5, #13077; CHECK-FP16-NEXT:    cmp r5, #03078; CHECK-FP16-NEXT:    movne r5, r03079; CHECK-FP16-NEXT:    bl __fixhfdi3080; CHECK-FP16-NEXT:    subs r2, r0, r43081; CHECK-FP16-NEXT:    vmov.32 d1[0], r53082; CHECK-FP16-NEXT:    sbcs r2, r1, #03083; CHECK-FP16-NEXT:    movlt r4, r03084; CHECK-FP16-NEXT:    mov r0, #03085; CHECK-FP16-NEXT:    movwlt r0, #13086; CHECK-FP16-NEXT:    cmp r0, #03087; CHECK-FP16-NEXT:    movne r0, r13088; CHECK-FP16-NEXT:    rsbs r1, r4, #03089; CHECK-FP16-NEXT:    rscs r0, r0, #03090; CHECK-FP16-NEXT:    vmov.32 d0[0], r73091; CHECK-FP16-NEXT:    movwlt r8, #13092; CHECK-FP16-NEXT:    cmp r8, #03093; CHECK-FP16-NEXT:    vmov.32 d1[1], r63094; CHECK-FP16-NEXT:    movne r8, r43095; CHECK-FP16-NEXT:    vmov.32 d0[1], r83096; CHECK-FP16-NEXT:    vpop {d8, d9}3097; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, pc}3098entry:3099  %conv = fptosi <4 x half> %x to <4 x i64>3100  %spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)3101  %spec.store.select7 = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %spec.store.select, <4 x i64> zeroinitializer)3102  %conv6 = trunc <4 x i64> %spec.store.select7 to <4 x i32>3103  ret <4 x i32> %conv63104}3105 3106; i16 saturate3107 3108define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {3109; CHECK-LABEL: stest_f64i16_mm:3110; CHECK:       @ %bb.0: @ %entry3111; CHECK-NEXT:    vcvt.s32.f64 s4, d03112; CHECK-NEXT:    vmov r0, s43113; CHECK-NEXT:    vcvt.s32.f64 s0, d13114; CHECK-NEXT:    vmov.i32 d17, #0x7fff3115; CHECK-NEXT:    vmvn.i32 d18, #0x7fff3116; CHECK-NEXT:    vmov.32 d16[0], r03117; CHECK-NEXT:    vmov r0, s03118; CHECK-NEXT:    vmov.32 d16[1], r03119; CHECK-NEXT:    vmin.s32 d16, d16, d173120; CHECK-NEXT:    vmax.s32 d0, d16, d183121; CHECK-NEXT:    bx lr3122entry:3123  %conv = fptosi <2 x double> %x to <2 x i32>3124  %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>)3125  %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> <i32 -32768, i32 -32768>)3126  %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>3127  ret <2 x i16> %conv63128}3129 3130define <2 x i16> @utest_f64i16_mm(<2 x double> %x) {3131; CHECK-LABEL: utest_f64i16_mm:3132; CHECK:       @ %bb.0: @ %entry3133; CHECK-NEXT:    vcvt.u32.f64 s4, d03134; CHECK-NEXT:    vmov r0, s43135; CHECK-NEXT:    vcvt.u32.f64 s0, d13136; CHECK-NEXT:    vmov.i32 d17, #0xffff3137; CHECK-NEXT:    vmov.32 d16[0], r03138; CHECK-NEXT:    vmov r0, s03139; CHECK-NEXT:    vmov.32 d16[1], r03140; CHECK-NEXT:    vmin.u32 d0, d16, d173141; CHECK-NEXT:    bx lr3142entry:3143  %conv = fptoui <2 x double> %x to <2 x i32>3144  %spec.store.select = call <2 x i32> @llvm.umin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)3145  %conv6 = trunc <2 x i32> %spec.store.select to <2 x i16>3146  ret <2 x i16> %conv63147}3148 3149define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {3150; CHECK-LABEL: ustest_f64i16_mm:3151; CHECK:       @ %bb.0: @ %entry3152; CHECK-NEXT:    vcvt.s32.f64 s4, d03153; CHECK-NEXT:    vmov r0, s43154; CHECK-NEXT:    vcvt.s32.f64 s0, d13155; CHECK-NEXT:    vmov.i32 d17, #0xffff3156; CHECK-NEXT:    vmov.i32 d18, #0x03157; CHECK-NEXT:    vmov.32 d16[0], r03158; CHECK-NEXT:    vmov r0, s03159; CHECK-NEXT:    vmov.32 d16[1], r03160; CHECK-NEXT:    vmin.s32 d16, d16, d173161; CHECK-NEXT:    vmax.s32 d0, d16, d183162; CHECK-NEXT:    bx lr3163entry:3164  %conv = fptosi <2 x double> %x to <2 x i32>3165  %spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)3166  %spec.store.select7 = call <2 x i32> @llvm.smax.v2i32(<2 x i32> %spec.store.select, <2 x i32> zeroinitializer)3167  %conv6 = trunc <2 x i32> %spec.store.select7 to <2 x i16>3168  ret <2 x i16> %conv63169}3170 3171define <4 x i16> @stest_f32i16_mm(<4 x float> %x) {3172; CHECK-LABEL: stest_f32i16_mm:3173; CHECK:       @ %bb.0: @ %entry3174; CHECK-NEXT:    vcvt.s32.f32 q8, q03175; CHECK-NEXT:    vmov.i32 q9, #0x7fff3176; CHECK-NEXT:    vmvn.i32 q10, #0x7fff3177; CHECK-NEXT:    vmin.s32 q8, q8, q93178; CHECK-NEXT:    vmax.s32 q8, q8, q103179; CHECK-NEXT:    vmovn.i32 d0, q83180; CHECK-NEXT:    bx lr3181entry:3182  %conv = fptosi <4 x float> %x to <4 x i32>3183  %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)3184  %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)3185  %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>3186  ret <4 x i16> %conv63187}3188 3189define <4 x i16> @utest_f32i16_mm(<4 x float> %x) {3190; CHECK-LABEL: utest_f32i16_mm:3191; CHECK:       @ %bb.0: @ %entry3192; CHECK-NEXT:    vcvt.u32.f32 q8, q03193; CHECK-NEXT:    vmov.i32 q9, #0xffff3194; CHECK-NEXT:    vmin.u32 q8, q8, q93195; CHECK-NEXT:    vmovn.i32 d0, q83196; CHECK-NEXT:    bx lr3197entry:3198  %conv = fptoui <4 x float> %x to <4 x i32>3199  %spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)3200  %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>3201  ret <4 x i16> %conv63202}3203 3204define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {3205; CHECK-LABEL: ustest_f32i16_mm:3206; CHECK:       @ %bb.0: @ %entry3207; CHECK-NEXT:    vcvt.s32.f32 q8, q03208; CHECK-NEXT:    vmov.i32 q9, #0xffff3209; CHECK-NEXT:    vmov.i32 q10, #0x03210; CHECK-NEXT:    vmin.s32 q8, q8, q93211; CHECK-NEXT:    vmax.s32 q8, q8, q103212; CHECK-NEXT:    vmovn.i32 d0, q83213; CHECK-NEXT:    bx lr3214entry:3215  %conv = fptosi <4 x float> %x to <4 x i32>3216  %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)3217  %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)3218  %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>3219  ret <4 x i16> %conv63220}3221 3222define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {3223; CHECK-NEON-LABEL: stest_f16i16_mm:3224; CHECK-NEON:       @ %bb.0: @ %entry3225; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}3226; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}3227; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}3228; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}3229; CHECK-NEON-NEXT:    vmov r0, s13230; CHECK-NEON-NEXT:    vmov.f32 s16, s73231; CHECK-NEON-NEXT:    vmov.f32 s18, s63232; CHECK-NEON-NEXT:    vmov.f32 s20, s53233; CHECK-NEON-NEXT:    vmov.f32 s22, s43234; CHECK-NEON-NEXT:    vmov.f32 s24, s33235; CHECK-NEON-NEXT:    vmov.f32 s26, s23236; CHECK-NEON-NEXT:    vmov.f32 s28, s03237; CHECK-NEON-NEXT:    bl __aeabi_h2f3238; CHECK-NEON-NEXT:    mov r4, r03239; CHECK-NEON-NEXT:    vmov r0, s263240; CHECK-NEON-NEXT:    bl __aeabi_h2f3241; CHECK-NEON-NEXT:    mov r5, r03242; CHECK-NEON-NEXT:    vmov r0, s223243; CHECK-NEON-NEXT:    bl __aeabi_h2f3244; CHECK-NEON-NEXT:    mov r6, r03245; CHECK-NEON-NEXT:    vmov r0, s243246; CHECK-NEON-NEXT:    bl __aeabi_h2f3247; CHECK-NEON-NEXT:    mov r7, r03248; CHECK-NEON-NEXT:    vmov r0, s183249; CHECK-NEON-NEXT:    bl __aeabi_h2f3250; CHECK-NEON-NEXT:    vmov s0, r03251; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03252; CHECK-NEON-NEXT:    vmov r0, s03253; CHECK-NEON-NEXT:    vmov.32 d13[0], r03254; CHECK-NEON-NEXT:    vmov r0, s163255; CHECK-NEON-NEXT:    bl __aeabi_h2f3256; CHECK-NEON-NEXT:    vmov s0, r03257; CHECK-NEON-NEXT:    vmov s22, r73258; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03259; CHECK-NEON-NEXT:    vmov s30, r63260; CHECK-NEON-NEXT:    vmov r0, s03261; CHECK-NEON-NEXT:    vmov.32 d13[1], r03262; CHECK-NEON-NEXT:    vmov r0, s283263; CHECK-NEON-NEXT:    bl __aeabi_h2f3264; CHECK-NEON-NEXT:    vmov s0, r03265; CHECK-NEON-NEXT:    vmov r1, s203266; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03267; CHECK-NEON-NEXT:    vmov s2, r53268; CHECK-NEON-NEXT:    vcvt.s32.f32 s20, s23269; CHECK-NEON-NEXT:    vmov r0, s03270; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s303271; CHECK-NEON-NEXT:    vmov.32 d8[0], r03272; CHECK-NEON-NEXT:    vmov r0, s03273; CHECK-NEON-NEXT:    vmov.32 d12[0], r03274; CHECK-NEON-NEXT:    mov r0, r13275; CHECK-NEON-NEXT:    bl __aeabi_h2f3276; CHECK-NEON-NEXT:    vmov s0, r03277; CHECK-NEON-NEXT:    vmov r0, s203278; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03279; CHECK-NEON-NEXT:    vmov s2, r43280; CHECK-NEON-NEXT:    vmov.i32 q8, #0x7fff3281; CHECK-NEON-NEXT:    vcvt.s32.f32 s2, s23282; CHECK-NEON-NEXT:    vmvn.i32 q9, #0x7fff3283; CHECK-NEON-NEXT:    vmov.32 d9[0], r03284; CHECK-NEON-NEXT:    vmov r0, s03285; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s223286; CHECK-NEON-NEXT:    vmov.32 d12[1], r03287; CHECK-NEON-NEXT:    vmov r0, s03288; CHECK-NEON-NEXT:    vmin.s32 q10, q6, q83289; CHECK-NEON-NEXT:    vmax.s32 q10, q10, q93290; CHECK-NEON-NEXT:    vmov.32 d9[1], r03291; CHECK-NEON-NEXT:    vmov r0, s23292; CHECK-NEON-NEXT:    vmovn.i32 d1, q103293; CHECK-NEON-NEXT:    vmov.32 d8[1], r03294; CHECK-NEON-NEXT:    vmin.s32 q8, q4, q83295; CHECK-NEON-NEXT:    vmax.s32 q8, q8, q93296; CHECK-NEON-NEXT:    vmovn.i32 d0, q83297; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}3298; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}3299;3300; CHECK-FP16-LABEL: stest_f16i16_mm:3301; CHECK-FP16:       @ %bb.0: @ %entry3302; CHECK-FP16-NEXT:    vmovx.f16 s4, s03303; CHECK-FP16-NEXT:    vcvt.s32.f16 s12, s03304; CHECK-FP16-NEXT:    vcvt.s32.f16 s0, s33305; CHECK-FP16-NEXT:    vcvt.s32.f16 s5, s23306; CHECK-FP16-NEXT:    vmov r0, s03307; CHECK-FP16-NEXT:    vcvt.s32.f16 s14, s13308; CHECK-FP16-NEXT:    vmovx.f16 s10, s33309; CHECK-FP16-NEXT:    vmovx.f16 s8, s23310; CHECK-FP16-NEXT:    vcvt.s32.f16 s10, s103311; CHECK-FP16-NEXT:    vcvt.s32.f16 s8, s83312; CHECK-FP16-NEXT:    vmovx.f16 s6, s13313; CHECK-FP16-NEXT:    vcvt.s32.f16 s4, s43314; CHECK-FP16-NEXT:    vcvt.s32.f16 s6, s63315; CHECK-FP16-NEXT:    vmov.i32 q10, #0x7fff3316; CHECK-FP16-NEXT:    vmvn.i32 q11, #0x7fff3317; CHECK-FP16-NEXT:    vmov.32 d17[0], r03318; CHECK-FP16-NEXT:    vmov r0, s53319; CHECK-FP16-NEXT:    vmov.32 d16[0], r03320; CHECK-FP16-NEXT:    vmov r0, s143321; CHECK-FP16-NEXT:    vmov.32 d19[0], r03322; CHECK-FP16-NEXT:    vmov r0, s123323; CHECK-FP16-NEXT:    vmov.32 d18[0], r03324; CHECK-FP16-NEXT:    vmov r0, s103325; CHECK-FP16-NEXT:    vmov.32 d17[1], r03326; CHECK-FP16-NEXT:    vmov r0, s83327; CHECK-FP16-NEXT:    vmov.32 d16[1], r03328; CHECK-FP16-NEXT:    vmov r0, s63329; CHECK-FP16-NEXT:    vmin.s32 q8, q8, q103330; CHECK-FP16-NEXT:    vmax.s32 q8, q8, q113331; CHECK-FP16-NEXT:    vmovn.i32 d1, q83332; CHECK-FP16-NEXT:    vmov.32 d19[1], r03333; CHECK-FP16-NEXT:    vmov r0, s43334; CHECK-FP16-NEXT:    vmov.32 d18[1], r03335; CHECK-FP16-NEXT:    vmin.s32 q9, q9, q103336; CHECK-FP16-NEXT:    vmax.s32 q9, q9, q113337; CHECK-FP16-NEXT:    vmovn.i32 d0, q93338; CHECK-FP16-NEXT:    bx lr3339entry:3340  %conv = fptosi <8 x half> %x to <8 x i32>3341  %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)3342  %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)3343  %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>3344  ret <8 x i16> %conv63345}3346 3347define <8 x i16> @utest_f16i16_mm(<8 x half> %x) {3348; CHECK-NEON-LABEL: utest_f16i16_mm:3349; CHECK-NEON:       @ %bb.0: @ %entry3350; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}3351; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}3352; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14}3353; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14}3354; CHECK-NEON-NEXT:    vmov r0, s13355; CHECK-NEON-NEXT:    vmov.f32 s16, s73356; CHECK-NEON-NEXT:    vmov.f32 s18, s63357; CHECK-NEON-NEXT:    vmov.f32 s20, s53358; CHECK-NEON-NEXT:    vmov.f32 s22, s43359; CHECK-NEON-NEXT:    vmov.f32 s24, s33360; CHECK-NEON-NEXT:    vmov.f32 s26, s23361; CHECK-NEON-NEXT:    vmov.f32 s28, s03362; CHECK-NEON-NEXT:    bl __aeabi_h2f3363; CHECK-NEON-NEXT:    mov r4, r03364; CHECK-NEON-NEXT:    vmov r0, s263365; CHECK-NEON-NEXT:    bl __aeabi_h2f3366; CHECK-NEON-NEXT:    mov r5, r03367; CHECK-NEON-NEXT:    vmov r0, s223368; CHECK-NEON-NEXT:    bl __aeabi_h2f3369; CHECK-NEON-NEXT:    mov r6, r03370; CHECK-NEON-NEXT:    vmov r0, s243371; CHECK-NEON-NEXT:    bl __aeabi_h2f3372; CHECK-NEON-NEXT:    mov r7, r03373; CHECK-NEON-NEXT:    vmov r0, s183374; CHECK-NEON-NEXT:    bl __aeabi_h2f3375; CHECK-NEON-NEXT:    vmov s0, r03376; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s03377; CHECK-NEON-NEXT:    vmov r0, s03378; CHECK-NEON-NEXT:    vmov.32 d13[0], r03379; CHECK-NEON-NEXT:    vmov r0, s163380; CHECK-NEON-NEXT:    bl __aeabi_h2f3381; CHECK-NEON-NEXT:    vmov s0, r03382; CHECK-NEON-NEXT:    vmov s16, r73383; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s03384; CHECK-NEON-NEXT:    vmov s18, r63385; CHECK-NEON-NEXT:    vmov r0, s03386; CHECK-NEON-NEXT:    vmov.32 d13[1], r03387; CHECK-NEON-NEXT:    vmov r0, s283388; CHECK-NEON-NEXT:    bl __aeabi_h2f3389; CHECK-NEON-NEXT:    vmov s0, r03390; CHECK-NEON-NEXT:    vmov r1, s203391; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s03392; CHECK-NEON-NEXT:    vmov s2, r53393; CHECK-NEON-NEXT:    vmov r0, s03394; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s183395; CHECK-NEON-NEXT:    vcvt.u32.f32 s18, s23396; CHECK-NEON-NEXT:    vmov.32 d10[0], r03397; CHECK-NEON-NEXT:    vmov r0, s03398; CHECK-NEON-NEXT:    vmov.32 d12[0], r03399; CHECK-NEON-NEXT:    mov r0, r13400; CHECK-NEON-NEXT:    bl __aeabi_h2f3401; CHECK-NEON-NEXT:    vmov s0, r03402; CHECK-NEON-NEXT:    vmov r0, s183403; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s03404; CHECK-NEON-NEXT:    vmov s2, r43405; CHECK-NEON-NEXT:    vmov.i32 q8, #0xffff3406; CHECK-NEON-NEXT:    vcvt.u32.f32 s2, s23407; CHECK-NEON-NEXT:    vmov.32 d11[0], r03408; CHECK-NEON-NEXT:    vmov r0, s03409; CHECK-NEON-NEXT:    vcvt.u32.f32 s0, s163410; CHECK-NEON-NEXT:    vmov.32 d12[1], r03411; CHECK-NEON-NEXT:    vmov r0, s03412; CHECK-NEON-NEXT:    vmin.u32 q9, q6, q83413; CHECK-NEON-NEXT:    vmov.32 d11[1], r03414; CHECK-NEON-NEXT:    vmov r0, s23415; CHECK-NEON-NEXT:    vmovn.i32 d1, q93416; CHECK-NEON-NEXT:    vmov.32 d10[1], r03417; CHECK-NEON-NEXT:    vmin.u32 q8, q5, q83418; CHECK-NEON-NEXT:    vmovn.i32 d0, q83419; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14}3420; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}3421;3422; CHECK-FP16-LABEL: utest_f16i16_mm:3423; CHECK-FP16:       @ %bb.0: @ %entry3424; CHECK-FP16-NEXT:    vmovx.f16 s4, s03425; CHECK-FP16-NEXT:    vcvt.u32.f16 s12, s03426; CHECK-FP16-NEXT:    vcvt.u32.f16 s0, s33427; CHECK-FP16-NEXT:    vcvt.u32.f16 s5, s23428; CHECK-FP16-NEXT:    vmov r0, s03429; CHECK-FP16-NEXT:    vcvt.u32.f16 s14, s13430; CHECK-FP16-NEXT:    vmovx.f16 s10, s33431; CHECK-FP16-NEXT:    vmovx.f16 s8, s23432; CHECK-FP16-NEXT:    vcvt.u32.f16 s10, s103433; CHECK-FP16-NEXT:    vcvt.u32.f16 s8, s83434; CHECK-FP16-NEXT:    vmovx.f16 s6, s13435; CHECK-FP16-NEXT:    vcvt.u32.f16 s4, s43436; CHECK-FP16-NEXT:    vcvt.u32.f16 s6, s63437; CHECK-FP16-NEXT:    vmov.i32 q10, #0xffff3438; CHECK-FP16-NEXT:    vmov.32 d17[0], r03439; CHECK-FP16-NEXT:    vmov r0, s53440; CHECK-FP16-NEXT:    vmov.32 d16[0], r03441; CHECK-FP16-NEXT:    vmov r0, s143442; CHECK-FP16-NEXT:    vmov.32 d19[0], r03443; CHECK-FP16-NEXT:    vmov r0, s123444; CHECK-FP16-NEXT:    vmov.32 d18[0], r03445; CHECK-FP16-NEXT:    vmov r0, s103446; CHECK-FP16-NEXT:    vmov.32 d17[1], r03447; CHECK-FP16-NEXT:    vmov r0, s83448; CHECK-FP16-NEXT:    vmov.32 d16[1], r03449; CHECK-FP16-NEXT:    vmov r0, s63450; CHECK-FP16-NEXT:    vmin.u32 q8, q8, q103451; CHECK-FP16-NEXT:    vmovn.i32 d1, q83452; CHECK-FP16-NEXT:    vmov.32 d19[1], r03453; CHECK-FP16-NEXT:    vmov r0, s43454; CHECK-FP16-NEXT:    vmov.32 d18[1], r03455; CHECK-FP16-NEXT:    vmin.u32 q9, q9, q103456; CHECK-FP16-NEXT:    vmovn.i32 d0, q93457; CHECK-FP16-NEXT:    bx lr3458entry:3459  %conv = fptoui <8 x half> %x to <8 x i32>3460  %spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)3461  %conv6 = trunc <8 x i32> %spec.store.select to <8 x i16>3462  ret <8 x i16> %conv63463}3464 3465define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {3466; CHECK-NEON-LABEL: ustest_f16i16_mm:3467; CHECK-NEON:       @ %bb.0: @ %entry3468; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}3469; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}3470; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11, d12, d13, d14, d15}3471; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11, d12, d13, d14, d15}3472; CHECK-NEON-NEXT:    vmov r0, s13473; CHECK-NEON-NEXT:    vmov.f32 s16, s73474; CHECK-NEON-NEXT:    vmov.f32 s18, s63475; CHECK-NEON-NEXT:    vmov.f32 s20, s53476; CHECK-NEON-NEXT:    vmov.f32 s22, s43477; CHECK-NEON-NEXT:    vmov.f32 s24, s33478; CHECK-NEON-NEXT:    vmov.f32 s26, s23479; CHECK-NEON-NEXT:    vmov.f32 s28, s03480; CHECK-NEON-NEXT:    bl __aeabi_h2f3481; CHECK-NEON-NEXT:    mov r4, r03482; CHECK-NEON-NEXT:    vmov r0, s263483; CHECK-NEON-NEXT:    bl __aeabi_h2f3484; CHECK-NEON-NEXT:    mov r5, r03485; CHECK-NEON-NEXT:    vmov r0, s223486; CHECK-NEON-NEXT:    bl __aeabi_h2f3487; CHECK-NEON-NEXT:    mov r6, r03488; CHECK-NEON-NEXT:    vmov r0, s243489; CHECK-NEON-NEXT:    bl __aeabi_h2f3490; CHECK-NEON-NEXT:    mov r7, r03491; CHECK-NEON-NEXT:    vmov r0, s183492; CHECK-NEON-NEXT:    bl __aeabi_h2f3493; CHECK-NEON-NEXT:    vmov s0, r03494; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03495; CHECK-NEON-NEXT:    vmov r0, s03496; CHECK-NEON-NEXT:    vmov.32 d13[0], r03497; CHECK-NEON-NEXT:    vmov r0, s163498; CHECK-NEON-NEXT:    bl __aeabi_h2f3499; CHECK-NEON-NEXT:    vmov s0, r03500; CHECK-NEON-NEXT:    vmov s22, r73501; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03502; CHECK-NEON-NEXT:    vmov s30, r63503; CHECK-NEON-NEXT:    vmov r0, s03504; CHECK-NEON-NEXT:    vmov.32 d13[1], r03505; CHECK-NEON-NEXT:    vmov r0, s283506; CHECK-NEON-NEXT:    bl __aeabi_h2f3507; CHECK-NEON-NEXT:    vmov s0, r03508; CHECK-NEON-NEXT:    vmov r1, s203509; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03510; CHECK-NEON-NEXT:    vmov s2, r53511; CHECK-NEON-NEXT:    vcvt.s32.f32 s20, s23512; CHECK-NEON-NEXT:    vmov r0, s03513; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s303514; CHECK-NEON-NEXT:    vmov.32 d8[0], r03515; CHECK-NEON-NEXT:    vmov r0, s03516; CHECK-NEON-NEXT:    vmov.32 d12[0], r03517; CHECK-NEON-NEXT:    mov r0, r13518; CHECK-NEON-NEXT:    bl __aeabi_h2f3519; CHECK-NEON-NEXT:    vmov s0, r03520; CHECK-NEON-NEXT:    vmov r0, s203521; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s03522; CHECK-NEON-NEXT:    vmov s2, r43523; CHECK-NEON-NEXT:    vmov.i32 q8, #0xffff3524; CHECK-NEON-NEXT:    vcvt.s32.f32 s2, s23525; CHECK-NEON-NEXT:    vmov.i32 q9, #0x03526; CHECK-NEON-NEXT:    vmov.32 d9[0], r03527; CHECK-NEON-NEXT:    vmov r0, s03528; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s223529; CHECK-NEON-NEXT:    vmov.32 d12[1], r03530; CHECK-NEON-NEXT:    vmov r0, s03531; CHECK-NEON-NEXT:    vmin.s32 q10, q6, q83532; CHECK-NEON-NEXT:    vmax.s32 q10, q10, q93533; CHECK-NEON-NEXT:    vmov.32 d9[1], r03534; CHECK-NEON-NEXT:    vmov r0, s23535; CHECK-NEON-NEXT:    vmovn.i32 d1, q103536; CHECK-NEON-NEXT:    vmov.32 d8[1], r03537; CHECK-NEON-NEXT:    vmin.s32 q8, q4, q83538; CHECK-NEON-NEXT:    vmax.s32 q8, q8, q93539; CHECK-NEON-NEXT:    vmovn.i32 d0, q83540; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}3541; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}3542;3543; CHECK-FP16-LABEL: ustest_f16i16_mm:3544; CHECK-FP16:       @ %bb.0: @ %entry3545; CHECK-FP16-NEXT:    vmovx.f16 s4, s03546; CHECK-FP16-NEXT:    vcvt.s32.f16 s12, s03547; CHECK-FP16-NEXT:    vcvt.s32.f16 s0, s33548; CHECK-FP16-NEXT:    vcvt.s32.f16 s5, s23549; CHECK-FP16-NEXT:    vmov r0, s03550; CHECK-FP16-NEXT:    vcvt.s32.f16 s14, s13551; CHECK-FP16-NEXT:    vmovx.f16 s10, s33552; CHECK-FP16-NEXT:    vmovx.f16 s8, s23553; CHECK-FP16-NEXT:    vcvt.s32.f16 s10, s103554; CHECK-FP16-NEXT:    vcvt.s32.f16 s8, s83555; CHECK-FP16-NEXT:    vmovx.f16 s6, s13556; CHECK-FP16-NEXT:    vcvt.s32.f16 s4, s43557; CHECK-FP16-NEXT:    vcvt.s32.f16 s6, s63558; CHECK-FP16-NEXT:    vmov.i32 q10, #0xffff3559; CHECK-FP16-NEXT:    vmov.i32 q11, #0x03560; CHECK-FP16-NEXT:    vmov.32 d17[0], r03561; CHECK-FP16-NEXT:    vmov r0, s53562; CHECK-FP16-NEXT:    vmov.32 d16[0], r03563; CHECK-FP16-NEXT:    vmov r0, s143564; CHECK-FP16-NEXT:    vmov.32 d19[0], r03565; CHECK-FP16-NEXT:    vmov r0, s123566; CHECK-FP16-NEXT:    vmov.32 d18[0], r03567; CHECK-FP16-NEXT:    vmov r0, s103568; CHECK-FP16-NEXT:    vmov.32 d17[1], r03569; CHECK-FP16-NEXT:    vmov r0, s83570; CHECK-FP16-NEXT:    vmov.32 d16[1], r03571; CHECK-FP16-NEXT:    vmov r0, s63572; CHECK-FP16-NEXT:    vmin.s32 q8, q8, q103573; CHECK-FP16-NEXT:    vmax.s32 q8, q8, q113574; CHECK-FP16-NEXT:    vmovn.i32 d1, q83575; CHECK-FP16-NEXT:    vmov.32 d19[1], r03576; CHECK-FP16-NEXT:    vmov r0, s43577; CHECK-FP16-NEXT:    vmov.32 d18[1], r03578; CHECK-FP16-NEXT:    vmin.s32 q9, q9, q103579; CHECK-FP16-NEXT:    vmax.s32 q9, q9, q113580; CHECK-FP16-NEXT:    vmovn.i32 d0, q93581; CHECK-FP16-NEXT:    bx lr3582entry:3583  %conv = fptosi <8 x half> %x to <8 x i32>3584  %spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)3585  %spec.store.select7 = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %spec.store.select, <8 x i32> zeroinitializer)3586  %conv6 = trunc <8 x i32> %spec.store.select7 to <8 x i16>3587  ret <8 x i16> %conv63588}3589 3590; i64 saturate3591 3592define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {3593; CHECK-LABEL: stest_f64i64_mm:3594; CHECK:       @ %bb.0: @ %entry3595; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}3596; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}3597; CHECK-NEXT:    .vsave {d8, d9}3598; CHECK-NEXT:    vpush {d8, d9}3599; CHECK-NEXT:    vorr q4, q0, q03600; CHECK-NEXT:    vorr d0, d9, d93601; CHECK-NEXT:    bl __fixdfti3602; CHECK-NEXT:    mov r4, r13603; CHECK-NEXT:    mvn r9, #03604; CHECK-NEXT:    subs r1, r0, r93605; CHECK-NEXT:    mvn r5, #-21474836483606; CHECK-NEXT:    sbcs r1, r4, r53607; CHECK-NEXT:    vorr d0, d8, d83608; CHECK-NEXT:    sbcs r1, r2, #03609; CHECK-NEXT:    mov r7, #03610; CHECK-NEXT:    sbcs r1, r3, #03611; CHECK-NEXT:    mov r8, #-21474836483612; CHECK-NEXT:    mov r1, #03613; CHECK-NEXT:    mov r10, #03614; CHECK-NEXT:    movwlt r1, #13615; CHECK-NEXT:    cmp r1, #03616; CHECK-NEXT:    moveq r3, r13617; CHECK-NEXT:    movne r1, r23618; CHECK-NEXT:    moveq r4, r53619; CHECK-NEXT:    moveq r0, r93620; CHECK-NEXT:    rsbs r2, r0, #03621; CHECK-NEXT:    rscs r2, r4, #-21474836483622; CHECK-NEXT:    sbcs r1, r9, r13623; CHECK-NEXT:    sbcs r1, r9, r33624; CHECK-NEXT:    movwlt r7, #13625; CHECK-NEXT:    cmp r7, #03626; CHECK-NEXT:    movne r7, r03627; CHECK-NEXT:    moveq r4, r83628; CHECK-NEXT:    bl __fixdfti3629; CHECK-NEXT:    subs r6, r0, r93630; CHECK-NEXT:    vmov.32 d1[0], r73631; CHECK-NEXT:    sbcs r6, r1, r53632; CHECK-NEXT:    sbcs r6, r2, #03633; CHECK-NEXT:    sbcs r6, r3, #03634; CHECK-NEXT:    mov r6, #03635; CHECK-NEXT:    movwlt r6, #13636; CHECK-NEXT:    cmp r6, #03637; CHECK-NEXT:    moveq r3, r63638; CHECK-NEXT:    movne r6, r23639; CHECK-NEXT:    movne r5, r13640; CHECK-NEXT:    moveq r0, r93641; CHECK-NEXT:    rsbs r1, r0, #03642; CHECK-NEXT:    rscs r1, r5, #-21474836483643; CHECK-NEXT:    sbcs r1, r9, r63644; CHECK-NEXT:    sbcs r1, r9, r33645; CHECK-NEXT:    movwlt r10, #13646; CHECK-NEXT:    cmp r10, #03647; CHECK-NEXT:    movne r10, r03648; CHECK-NEXT:    moveq r5, r83649; CHECK-NEXT:    vmov.32 d0[0], r103650; CHECK-NEXT:    vmov.32 d1[1], r43651; CHECK-NEXT:    vmov.32 d0[1], r53652; CHECK-NEXT:    vpop {d8, d9}3653; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}3654entry:3655  %conv = fptosi <2 x double> %x to <2 x i128>3656  %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)3657  %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)3658  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>3659  ret <2 x i64> %conv63660}3661 3662define <2 x i64> @utest_f64i64_mm(<2 x double> %x) {3663; CHECK-LABEL: utest_f64i64_mm:3664; CHECK:       @ %bb.0: @ %entry3665; CHECK-NEXT:    .save {r4, r5, r6, lr}3666; CHECK-NEXT:    push {r4, r5, r6, lr}3667; CHECK-NEXT:    .vsave {d8, d9}3668; CHECK-NEXT:    vpush {d8, d9}3669; CHECK-NEXT:    vorr q4, q0, q03670; CHECK-NEXT:    vorr d0, d9, d93671; CHECK-NEXT:    bl __fixunsdfti3672; CHECK-NEXT:    mov r4, r13673; CHECK-NEXT:    subs r1, r2, #13674; CHECK-NEXT:    vorr d0, d8, d83675; CHECK-NEXT:    sbcs r1, r3, #03676; CHECK-NEXT:    mov r6, #03677; CHECK-NEXT:    mov r5, #03678; CHECK-NEXT:    movwlo r6, #13679; CHECK-NEXT:    cmp r6, #03680; CHECK-NEXT:    moveq r4, r63681; CHECK-NEXT:    movne r6, r03682; CHECK-NEXT:    bl __fixunsdfti3683; CHECK-NEXT:    subs r2, r2, #13684; CHECK-NEXT:    vmov.32 d1[0], r63685; CHECK-NEXT:    sbcs r2, r3, #03686; CHECK-NEXT:    movwlo r5, #13687; CHECK-NEXT:    cmp r5, #03688; CHECK-NEXT:    moveq r0, r53689; CHECK-NEXT:    movne r5, r13690; CHECK-NEXT:    vmov.32 d0[0], r03691; CHECK-NEXT:    vmov.32 d1[1], r43692; CHECK-NEXT:    vmov.32 d0[1], r53693; CHECK-NEXT:    vpop {d8, d9}3694; CHECK-NEXT:    pop {r4, r5, r6, pc}3695entry:3696  %conv = fptoui <2 x double> %x to <2 x i128>3697  %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)3698  %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>3699  ret <2 x i64> %conv63700}3701 3702define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {3703; CHECK-LABEL: ustest_f64i64_mm:3704; CHECK:       @ %bb.0: @ %entry3705; CHECK-NEXT:    .save {r4, r5, r6, lr}3706; CHECK-NEXT:    push {r4, r5, r6, lr}3707; CHECK-NEXT:    .vsave {d8, d9}3708; CHECK-NEXT:    vpush {d8, d9}3709; CHECK-NEXT:    vorr q4, q0, q03710; CHECK-NEXT:    vorr d0, d9, d93711; CHECK-NEXT:    bl __fixdfti3712; CHECK-NEXT:    mov r5, r03713; CHECK-NEXT:    subs r0, r2, #13714; CHECK-NEXT:    sbcs r0, r3, #03715; CHECK-NEXT:    vorr d0, d8, d83716; CHECK-NEXT:    mov r0, #03717; CHECK-NEXT:    mov r4, r13718; CHECK-NEXT:    movwlt r0, #13719; CHECK-NEXT:    cmp r0, #03720; CHECK-NEXT:    moveq r5, r03721; CHECK-NEXT:    moveq r4, r03722; CHECK-NEXT:    movne r0, r33723; CHECK-NEXT:    cmp r0, #03724; CHECK-NEXT:    mov r6, #03725; CHECK-NEXT:    movwmi r4, #03726; CHECK-NEXT:    movwmi r5, #03727; CHECK-NEXT:    bl __fixdfti3728; CHECK-NEXT:    subs r2, r2, #13729; CHECK-NEXT:    vmov.32 d1[0], r53730; CHECK-NEXT:    sbcs r2, r3, #03731; CHECK-NEXT:    movwlt r6, #13732; CHECK-NEXT:    cmp r6, #03733; CHECK-NEXT:    moveq r1, r63734; CHECK-NEXT:    moveq r0, r63735; CHECK-NEXT:    movne r6, r33736; CHECK-NEXT:    cmp r6, #03737; CHECK-NEXT:    movwmi r0, #03738; CHECK-NEXT:    movwmi r1, #03739; CHECK-NEXT:    vmov.32 d0[0], r03740; CHECK-NEXT:    vmov.32 d1[1], r43741; CHECK-NEXT:    vmov.32 d0[1], r13742; CHECK-NEXT:    vpop {d8, d9}3743; CHECK-NEXT:    pop {r4, r5, r6, pc}3744entry:3745  %conv = fptosi <2 x double> %x to <2 x i128>3746  %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)3747  %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)3748  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>3749  ret <2 x i64> %conv63750}3751 3752define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {3753; CHECK-LABEL: stest_f32i64_mm:3754; CHECK:       @ %bb.0: @ %entry3755; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}3756; CHECK-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}3757; CHECK-NEXT:    .vsave {d8}3758; CHECK-NEXT:    vpush {d8}3759; CHECK-NEXT:    vmov.f64 d8, d03760; CHECK-NEXT:    vmov.f32 s0, s173761; CHECK-NEXT:    bl __fixsfti3762; CHECK-NEXT:    mov r4, r13763; CHECK-NEXT:    mvn r9, #03764; CHECK-NEXT:    subs r1, r0, r93765; CHECK-NEXT:    mvn r5, #-21474836483766; CHECK-NEXT:    sbcs r1, r4, r53767; CHECK-NEXT:    vmov.f32 s0, s163768; CHECK-NEXT:    sbcs r1, r2, #03769; CHECK-NEXT:    mov r7, #03770; CHECK-NEXT:    sbcs r1, r3, #03771; CHECK-NEXT:    mov r8, #-21474836483772; CHECK-NEXT:    mov r1, #03773; CHECK-NEXT:    mov r10, #03774; CHECK-NEXT:    movwlt r1, #13775; CHECK-NEXT:    cmp r1, #03776; CHECK-NEXT:    moveq r3, r13777; CHECK-NEXT:    movne r1, r23778; CHECK-NEXT:    moveq r4, r53779; CHECK-NEXT:    moveq r0, r93780; CHECK-NEXT:    rsbs r2, r0, #03781; CHECK-NEXT:    rscs r2, r4, #-21474836483782; CHECK-NEXT:    sbcs r1, r9, r13783; CHECK-NEXT:    sbcs r1, r9, r33784; CHECK-NEXT:    movwlt r7, #13785; CHECK-NEXT:    cmp r7, #03786; CHECK-NEXT:    movne r7, r03787; CHECK-NEXT:    moveq r4, r83788; CHECK-NEXT:    bl __fixsfti3789; CHECK-NEXT:    subs r6, r0, r93790; CHECK-NEXT:    vmov.32 d1[0], r73791; CHECK-NEXT:    sbcs r6, r1, r53792; CHECK-NEXT:    sbcs r6, r2, #03793; CHECK-NEXT:    sbcs r6, r3, #03794; CHECK-NEXT:    mov r6, #03795; CHECK-NEXT:    movwlt r6, #13796; CHECK-NEXT:    cmp r6, #03797; CHECK-NEXT:    moveq r3, r63798; CHECK-NEXT:    movne r6, r23799; CHECK-NEXT:    movne r5, r13800; CHECK-NEXT:    moveq r0, r93801; CHECK-NEXT:    rsbs r1, r0, #03802; CHECK-NEXT:    rscs r1, r5, #-21474836483803; CHECK-NEXT:    sbcs r1, r9, r63804; CHECK-NEXT:    sbcs r1, r9, r33805; CHECK-NEXT:    movwlt r10, #13806; CHECK-NEXT:    cmp r10, #03807; CHECK-NEXT:    movne r10, r03808; CHECK-NEXT:    moveq r5, r83809; CHECK-NEXT:    vmov.32 d0[0], r103810; CHECK-NEXT:    vmov.32 d1[1], r43811; CHECK-NEXT:    vmov.32 d0[1], r53812; CHECK-NEXT:    vpop {d8}3813; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}3814entry:3815  %conv = fptosi <2 x float> %x to <2 x i128>3816  %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)3817  %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)3818  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>3819  ret <2 x i64> %conv63820}3821 3822define <2 x i64> @utest_f32i64_mm(<2 x float> %x) {3823; CHECK-LABEL: utest_f32i64_mm:3824; CHECK:       @ %bb.0: @ %entry3825; CHECK-NEXT:    .save {r4, r5, r6, lr}3826; CHECK-NEXT:    push {r4, r5, r6, lr}3827; CHECK-NEXT:    .vsave {d8}3828; CHECK-NEXT:    vpush {d8}3829; CHECK-NEXT:    vmov.f64 d8, d03830; CHECK-NEXT:    vmov.f32 s0, s173831; CHECK-NEXT:    bl __fixunssfti3832; CHECK-NEXT:    vmov.f32 s0, s163833; CHECK-NEXT:    mov r4, r13834; CHECK-NEXT:    subs r1, r2, #13835; CHECK-NEXT:    mov r6, #03836; CHECK-NEXT:    sbcs r1, r3, #03837; CHECK-NEXT:    mov r5, #03838; CHECK-NEXT:    movwlo r6, #13839; CHECK-NEXT:    cmp r6, #03840; CHECK-NEXT:    moveq r4, r63841; CHECK-NEXT:    movne r6, r03842; CHECK-NEXT:    bl __fixunssfti3843; CHECK-NEXT:    subs r2, r2, #13844; CHECK-NEXT:    vmov.32 d1[0], r63845; CHECK-NEXT:    sbcs r2, r3, #03846; CHECK-NEXT:    movwlo r5, #13847; CHECK-NEXT:    cmp r5, #03848; CHECK-NEXT:    moveq r0, r53849; CHECK-NEXT:    movne r5, r13850; CHECK-NEXT:    vmov.32 d0[0], r03851; CHECK-NEXT:    vmov.32 d1[1], r43852; CHECK-NEXT:    vmov.32 d0[1], r53853; CHECK-NEXT:    vpop {d8}3854; CHECK-NEXT:    pop {r4, r5, r6, pc}3855entry:3856  %conv = fptoui <2 x float> %x to <2 x i128>3857  %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)3858  %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>3859  ret <2 x i64> %conv63860}3861 3862define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {3863; CHECK-LABEL: ustest_f32i64_mm:3864; CHECK:       @ %bb.0: @ %entry3865; CHECK-NEXT:    .save {r4, r5, r6, lr}3866; CHECK-NEXT:    push {r4, r5, r6, lr}3867; CHECK-NEXT:    .vsave {d8}3868; CHECK-NEXT:    vpush {d8}3869; CHECK-NEXT:    vmov.f64 d8, d03870; CHECK-NEXT:    vmov.f32 s0, s173871; CHECK-NEXT:    bl __fixsfti3872; CHECK-NEXT:    vmov.f32 s0, s163873; CHECK-NEXT:    mov r5, r03874; CHECK-NEXT:    subs r0, r2, #13875; CHECK-NEXT:    mov r4, r13876; CHECK-NEXT:    sbcs r0, r3, #03877; CHECK-NEXT:    mov r6, #03878; CHECK-NEXT:    mov r0, #03879; CHECK-NEXT:    movwlt r0, #13880; CHECK-NEXT:    cmp r0, #03881; CHECK-NEXT:    moveq r5, r03882; CHECK-NEXT:    moveq r4, r03883; CHECK-NEXT:    movne r0, r33884; CHECK-NEXT:    cmp r0, #03885; CHECK-NEXT:    movwmi r4, #03886; CHECK-NEXT:    movwmi r5, #03887; CHECK-NEXT:    bl __fixsfti3888; CHECK-NEXT:    subs r2, r2, #13889; CHECK-NEXT:    vmov.32 d1[0], r53890; CHECK-NEXT:    sbcs r2, r3, #03891; CHECK-NEXT:    movwlt r6, #13892; CHECK-NEXT:    cmp r6, #03893; CHECK-NEXT:    moveq r1, r63894; CHECK-NEXT:    moveq r0, r63895; CHECK-NEXT:    movne r6, r33896; CHECK-NEXT:    cmp r6, #03897; CHECK-NEXT:    movwmi r0, #03898; CHECK-NEXT:    movwmi r1, #03899; CHECK-NEXT:    vmov.32 d0[0], r03900; CHECK-NEXT:    vmov.32 d1[1], r43901; CHECK-NEXT:    vmov.32 d0[1], r13902; CHECK-NEXT:    vpop {d8}3903; CHECK-NEXT:    pop {r4, r5, r6, pc}3904entry:3905  %conv = fptosi <2 x float> %x to <2 x i128>3906  %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)3907  %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)3908  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>3909  ret <2 x i64> %conv63910}3911 3912define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {3913; CHECK-NEON-LABEL: stest_f16i64_mm:3914; CHECK-NEON:       @ %bb.0: @ %entry3915; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}3916; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}3917; CHECK-NEON-NEXT:    .vsave {d8}3918; CHECK-NEON-NEXT:    vpush {d8}3919; CHECK-NEON-NEXT:    vmov r0, s03920; CHECK-NEON-NEXT:    vmov.f32 s16, s13921; CHECK-NEON-NEXT:    bl __aeabi_h2f3922; CHECK-NEON-NEXT:    mov r8, r03923; CHECK-NEON-NEXT:    vmov r0, s163924; CHECK-NEON-NEXT:    bl __aeabi_h2f3925; CHECK-NEON-NEXT:    vmov s0, r03926; CHECK-NEON-NEXT:    bl __fixsfti3927; CHECK-NEON-NEXT:    mov r4, r13928; CHECK-NEON-NEXT:    mvn r9, #03929; CHECK-NEON-NEXT:    subs r1, r0, r93930; CHECK-NEON-NEXT:    mvn r6, #-21474836483931; CHECK-NEON-NEXT:    sbcs r1, r4, r63932; CHECK-NEON-NEXT:    vmov s0, r83933; CHECK-NEON-NEXT:    sbcs r1, r2, #03934; CHECK-NEON-NEXT:    mov r5, #03935; CHECK-NEON-NEXT:    sbcs r1, r3, #03936; CHECK-NEON-NEXT:    mov r8, #-21474836483937; CHECK-NEON-NEXT:    mov r1, #03938; CHECK-NEON-NEXT:    mov r10, #03939; CHECK-NEON-NEXT:    movwlt r1, #13940; CHECK-NEON-NEXT:    cmp r1, #03941; CHECK-NEON-NEXT:    moveq r3, r13942; CHECK-NEON-NEXT:    movne r1, r23943; CHECK-NEON-NEXT:    moveq r4, r63944; CHECK-NEON-NEXT:    moveq r0, r93945; CHECK-NEON-NEXT:    rsbs r2, r0, #03946; CHECK-NEON-NEXT:    rscs r2, r4, #-21474836483947; CHECK-NEON-NEXT:    sbcs r1, r9, r13948; CHECK-NEON-NEXT:    sbcs r1, r9, r33949; CHECK-NEON-NEXT:    movwlt r5, #13950; CHECK-NEON-NEXT:    cmp r5, #03951; CHECK-NEON-NEXT:    movne r5, r03952; CHECK-NEON-NEXT:    moveq r4, r83953; CHECK-NEON-NEXT:    bl __fixsfti3954; CHECK-NEON-NEXT:    subs r7, r0, r93955; CHECK-NEON-NEXT:    vmov.32 d1[0], r53956; CHECK-NEON-NEXT:    sbcs r7, r1, r63957; CHECK-NEON-NEXT:    sbcs r7, r2, #03958; CHECK-NEON-NEXT:    sbcs r7, r3, #03959; CHECK-NEON-NEXT:    mov r7, #03960; CHECK-NEON-NEXT:    movwlt r7, #13961; CHECK-NEON-NEXT:    cmp r7, #03962; CHECK-NEON-NEXT:    moveq r3, r73963; CHECK-NEON-NEXT:    movne r7, r23964; CHECK-NEON-NEXT:    movne r6, r13965; CHECK-NEON-NEXT:    moveq r0, r93966; CHECK-NEON-NEXT:    rsbs r1, r0, #03967; CHECK-NEON-NEXT:    rscs r1, r6, #-21474836483968; CHECK-NEON-NEXT:    sbcs r1, r9, r73969; CHECK-NEON-NEXT:    sbcs r1, r9, r33970; CHECK-NEON-NEXT:    movwlt r10, #13971; CHECK-NEON-NEXT:    cmp r10, #03972; CHECK-NEON-NEXT:    movne r10, r03973; CHECK-NEON-NEXT:    moveq r6, r83974; CHECK-NEON-NEXT:    vmov.32 d0[0], r103975; CHECK-NEON-NEXT:    vmov.32 d1[1], r43976; CHECK-NEON-NEXT:    vmov.32 d0[1], r63977; CHECK-NEON-NEXT:    vpop {d8}3978; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}3979;3980; CHECK-FP16-LABEL: stest_f16i64_mm:3981; CHECK-FP16:       @ %bb.0: @ %entry3982; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r8, r9, r10, lr}3983; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r8, r9, r10, lr}3984; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]3985; CHECK-FP16-NEXT:    vmov.u16 r7, d0[0]3986; CHECK-FP16-NEXT:    vmov s0, r03987; CHECK-FP16-NEXT:    bl __fixhfti3988; CHECK-FP16-NEXT:    mov r4, r13989; CHECK-FP16-NEXT:    mvn r9, #03990; CHECK-FP16-NEXT:    subs r1, r0, r93991; CHECK-FP16-NEXT:    mvn r5, #-21474836483992; CHECK-FP16-NEXT:    sbcs r1, r4, r53993; CHECK-FP16-NEXT:    vmov s0, r73994; CHECK-FP16-NEXT:    sbcs r1, r2, #03995; CHECK-FP16-NEXT:    mov r7, #03996; CHECK-FP16-NEXT:    sbcs r1, r3, #03997; CHECK-FP16-NEXT:    mov r8, #-21474836483998; CHECK-FP16-NEXT:    mov r1, #03999; CHECK-FP16-NEXT:    mov r10, #04000; CHECK-FP16-NEXT:    movwlt r1, #14001; CHECK-FP16-NEXT:    cmp r1, #04002; CHECK-FP16-NEXT:    moveq r3, r14003; CHECK-FP16-NEXT:    movne r1, r24004; CHECK-FP16-NEXT:    moveq r4, r54005; CHECK-FP16-NEXT:    moveq r0, r94006; CHECK-FP16-NEXT:    rsbs r2, r0, #04007; CHECK-FP16-NEXT:    rscs r2, r4, #-21474836484008; CHECK-FP16-NEXT:    sbcs r1, r9, r14009; CHECK-FP16-NEXT:    sbcs r1, r9, r34010; CHECK-FP16-NEXT:    movwlt r7, #14011; CHECK-FP16-NEXT:    cmp r7, #04012; CHECK-FP16-NEXT:    movne r7, r04013; CHECK-FP16-NEXT:    moveq r4, r84014; CHECK-FP16-NEXT:    bl __fixhfti4015; CHECK-FP16-NEXT:    subs r6, r0, r94016; CHECK-FP16-NEXT:    vmov.32 d1[0], r74017; CHECK-FP16-NEXT:    sbcs r6, r1, r54018; CHECK-FP16-NEXT:    sbcs r6, r2, #04019; CHECK-FP16-NEXT:    sbcs r6, r3, #04020; CHECK-FP16-NEXT:    mov r6, #04021; CHECK-FP16-NEXT:    movwlt r6, #14022; CHECK-FP16-NEXT:    cmp r6, #04023; CHECK-FP16-NEXT:    moveq r3, r64024; CHECK-FP16-NEXT:    movne r6, r24025; CHECK-FP16-NEXT:    movne r5, r14026; CHECK-FP16-NEXT:    moveq r0, r94027; CHECK-FP16-NEXT:    rsbs r1, r0, #04028; CHECK-FP16-NEXT:    rscs r1, r5, #-21474836484029; CHECK-FP16-NEXT:    sbcs r1, r9, r64030; CHECK-FP16-NEXT:    sbcs r1, r9, r34031; CHECK-FP16-NEXT:    movwlt r10, #14032; CHECK-FP16-NEXT:    cmp r10, #04033; CHECK-FP16-NEXT:    movne r10, r04034; CHECK-FP16-NEXT:    moveq r5, r84035; CHECK-FP16-NEXT:    vmov.32 d0[0], r104036; CHECK-FP16-NEXT:    vmov.32 d1[1], r44037; CHECK-FP16-NEXT:    vmov.32 d0[1], r54038; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r8, r9, r10, pc}4039entry:4040  %conv = fptosi <2 x half> %x to <2 x i128>4041  %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)4042  %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> <i128 -9223372036854775808, i128 -9223372036854775808>)4043  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>4044  ret <2 x i64> %conv64045}4046 4047define <2 x i64> @utest_f16i64_mm(<2 x half> %x) {4048; CHECK-NEON-LABEL: utest_f16i64_mm:4049; CHECK-NEON:       @ %bb.0: @ %entry4050; CHECK-NEON-NEXT:    .save {r4, r5, r6, lr}4051; CHECK-NEON-NEXT:    push {r4, r5, r6, lr}4052; CHECK-NEON-NEXT:    .vsave {d8}4053; CHECK-NEON-NEXT:    vpush {d8}4054; CHECK-NEON-NEXT:    vmov r0, s04055; CHECK-NEON-NEXT:    vmov.f32 s16, s14056; CHECK-NEON-NEXT:    bl __aeabi_h2f4057; CHECK-NEON-NEXT:    mov r5, r04058; CHECK-NEON-NEXT:    vmov r0, s164059; CHECK-NEON-NEXT:    bl __aeabi_h2f4060; CHECK-NEON-NEXT:    vmov s0, r04061; CHECK-NEON-NEXT:    bl __fixunssfti4062; CHECK-NEON-NEXT:    mov r4, r14063; CHECK-NEON-NEXT:    subs r1, r2, #14064; CHECK-NEON-NEXT:    vmov s0, r54065; CHECK-NEON-NEXT:    sbcs r1, r3, #04066; CHECK-NEON-NEXT:    mov r5, #04067; CHECK-NEON-NEXT:    mov r6, #04068; CHECK-NEON-NEXT:    movwlo r5, #14069; CHECK-NEON-NEXT:    cmp r5, #04070; CHECK-NEON-NEXT:    moveq r4, r54071; CHECK-NEON-NEXT:    movne r5, r04072; CHECK-NEON-NEXT:    bl __fixunssfti4073; CHECK-NEON-NEXT:    subs r2, r2, #14074; CHECK-NEON-NEXT:    vmov.32 d1[0], r54075; CHECK-NEON-NEXT:    sbcs r2, r3, #04076; CHECK-NEON-NEXT:    movwlo r6, #14077; CHECK-NEON-NEXT:    cmp r6, #04078; CHECK-NEON-NEXT:    moveq r0, r64079; CHECK-NEON-NEXT:    movne r6, r14080; CHECK-NEON-NEXT:    vmov.32 d0[0], r04081; CHECK-NEON-NEXT:    vmov.32 d1[1], r44082; CHECK-NEON-NEXT:    vmov.32 d0[1], r64083; CHECK-NEON-NEXT:    vpop {d8}4084; CHECK-NEON-NEXT:    pop {r4, r5, r6, pc}4085;4086; CHECK-FP16-LABEL: utest_f16i64_mm:4087; CHECK-FP16:       @ %bb.0: @ %entry4088; CHECK-FP16-NEXT:    .save {r4, r5, r6, lr}4089; CHECK-FP16-NEXT:    push {r4, r5, r6, lr}4090; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]4091; CHECK-FP16-NEXT:    vmov.u16 r6, d0[0]4092; CHECK-FP16-NEXT:    vmov s0, r04093; CHECK-FP16-NEXT:    bl __fixunshfti4094; CHECK-FP16-NEXT:    mov r4, r14095; CHECK-FP16-NEXT:    subs r1, r2, #14096; CHECK-FP16-NEXT:    vmov s0, r64097; CHECK-FP16-NEXT:    sbcs r1, r3, #04098; CHECK-FP16-NEXT:    mov r6, #04099; CHECK-FP16-NEXT:    mov r5, #04100; CHECK-FP16-NEXT:    movwlo r6, #14101; CHECK-FP16-NEXT:    cmp r6, #04102; CHECK-FP16-NEXT:    moveq r4, r64103; CHECK-FP16-NEXT:    movne r6, r04104; CHECK-FP16-NEXT:    bl __fixunshfti4105; CHECK-FP16-NEXT:    subs r2, r2, #14106; CHECK-FP16-NEXT:    vmov.32 d1[0], r64107; CHECK-FP16-NEXT:    sbcs r2, r3, #04108; CHECK-FP16-NEXT:    movwlo r5, #14109; CHECK-FP16-NEXT:    cmp r5, #04110; CHECK-FP16-NEXT:    moveq r0, r54111; CHECK-FP16-NEXT:    movne r5, r14112; CHECK-FP16-NEXT:    vmov.32 d0[0], r04113; CHECK-FP16-NEXT:    vmov.32 d1[1], r44114; CHECK-FP16-NEXT:    vmov.32 d0[1], r54115; CHECK-FP16-NEXT:    pop {r4, r5, r6, pc}4116entry:4117  %conv = fptoui <2 x half> %x to <2 x i128>4118  %spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)4119  %conv6 = trunc <2 x i128> %spec.store.select to <2 x i64>4120  ret <2 x i64> %conv64121}4122 4123define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {4124; CHECK-NEON-LABEL: ustest_f16i64_mm:4125; CHECK-NEON:       @ %bb.0: @ %entry4126; CHECK-NEON-NEXT:    .save {r4, r5, r6, r7, r11, lr}4127; CHECK-NEON-NEXT:    push {r4, r5, r6, r7, r11, lr}4128; CHECK-NEON-NEXT:    .vsave {d8}4129; CHECK-NEON-NEXT:    vpush {d8}4130; CHECK-NEON-NEXT:    vmov r0, s04131; CHECK-NEON-NEXT:    vmov.f32 s16, s14132; CHECK-NEON-NEXT:    bl __aeabi_h2f4133; CHECK-NEON-NEXT:    mov r6, r04134; CHECK-NEON-NEXT:    vmov r0, s164135; CHECK-NEON-NEXT:    bl __aeabi_h2f4136; CHECK-NEON-NEXT:    vmov s0, r04137; CHECK-NEON-NEXT:    bl __fixsfti4138; CHECK-NEON-NEXT:    mov r5, r04139; CHECK-NEON-NEXT:    subs r0, r2, #14140; CHECK-NEON-NEXT:    sbcs r0, r3, #04141; CHECK-NEON-NEXT:    vmov s0, r64142; CHECK-NEON-NEXT:    mov r0, #04143; CHECK-NEON-NEXT:    mov r4, r14144; CHECK-NEON-NEXT:    movwlt r0, #14145; CHECK-NEON-NEXT:    cmp r0, #04146; CHECK-NEON-NEXT:    moveq r5, r04147; CHECK-NEON-NEXT:    moveq r4, r04148; CHECK-NEON-NEXT:    movne r0, r34149; CHECK-NEON-NEXT:    cmp r0, #04150; CHECK-NEON-NEXT:    mov r7, #04151; CHECK-NEON-NEXT:    movwmi r4, #04152; CHECK-NEON-NEXT:    movwmi r5, #04153; CHECK-NEON-NEXT:    bl __fixsfti4154; CHECK-NEON-NEXT:    subs r2, r2, #14155; CHECK-NEON-NEXT:    vmov.32 d1[0], r54156; CHECK-NEON-NEXT:    sbcs r2, r3, #04157; CHECK-NEON-NEXT:    movwlt r7, #14158; CHECK-NEON-NEXT:    cmp r7, #04159; CHECK-NEON-NEXT:    moveq r1, r74160; CHECK-NEON-NEXT:    moveq r0, r74161; CHECK-NEON-NEXT:    movne r7, r34162; CHECK-NEON-NEXT:    cmp r7, #04163; CHECK-NEON-NEXT:    movwmi r0, #04164; CHECK-NEON-NEXT:    movwmi r1, #04165; CHECK-NEON-NEXT:    vmov.32 d0[0], r04166; CHECK-NEON-NEXT:    vmov.32 d1[1], r44167; CHECK-NEON-NEXT:    vmov.32 d0[1], r14168; CHECK-NEON-NEXT:    vpop {d8}4169; CHECK-NEON-NEXT:    pop {r4, r5, r6, r7, r11, pc}4170;4171; CHECK-FP16-LABEL: ustest_f16i64_mm:4172; CHECK-FP16:       @ %bb.0: @ %entry4173; CHECK-FP16-NEXT:    .save {r4, r5, r6, r7, r11, lr}4174; CHECK-FP16-NEXT:    push {r4, r5, r6, r7, r11, lr}4175; CHECK-FP16-NEXT:    vmov.u16 r0, d0[1]4176; CHECK-FP16-NEXT:    vmov.u16 r7, d0[0]4177; CHECK-FP16-NEXT:    vmov s0, r04178; CHECK-FP16-NEXT:    bl __fixhfti4179; CHECK-FP16-NEXT:    mov r5, r04180; CHECK-FP16-NEXT:    subs r0, r2, #14181; CHECK-FP16-NEXT:    sbcs r0, r3, #04182; CHECK-FP16-NEXT:    vmov s0, r74183; CHECK-FP16-NEXT:    mov r0, #04184; CHECK-FP16-NEXT:    mov r4, r14185; CHECK-FP16-NEXT:    movwlt r0, #14186; CHECK-FP16-NEXT:    cmp r0, #04187; CHECK-FP16-NEXT:    moveq r5, r04188; CHECK-FP16-NEXT:    moveq r4, r04189; CHECK-FP16-NEXT:    movne r0, r34190; CHECK-FP16-NEXT:    cmp r0, #04191; CHECK-FP16-NEXT:    mov r6, #04192; CHECK-FP16-NEXT:    movwmi r4, #04193; CHECK-FP16-NEXT:    movwmi r5, #04194; CHECK-FP16-NEXT:    bl __fixhfti4195; CHECK-FP16-NEXT:    subs r2, r2, #14196; CHECK-FP16-NEXT:    vmov.32 d1[0], r54197; CHECK-FP16-NEXT:    sbcs r2, r3, #04198; CHECK-FP16-NEXT:    movwlt r6, #14199; CHECK-FP16-NEXT:    cmp r6, #04200; CHECK-FP16-NEXT:    moveq r1, r64201; CHECK-FP16-NEXT:    moveq r0, r64202; CHECK-FP16-NEXT:    movne r6, r34203; CHECK-FP16-NEXT:    cmp r6, #04204; CHECK-FP16-NEXT:    movwmi r0, #04205; CHECK-FP16-NEXT:    movwmi r1, #04206; CHECK-FP16-NEXT:    vmov.32 d0[0], r04207; CHECK-FP16-NEXT:    vmov.32 d1[1], r44208; CHECK-FP16-NEXT:    vmov.32 d0[1], r14209; CHECK-FP16-NEXT:    pop {r4, r5, r6, r7, r11, pc}4210entry:4211  %conv = fptosi <2 x half> %x to <2 x i128>4212  %spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)4213  %spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)4214  %conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>4215  ret <2 x i64> %conv64216}4217 4218; i32 non saturate4219 4220define <4 x i32> @ustest_f16i32_nsat(<4 x half> %x) {4221; CHECK-NEON-LABEL: ustest_f16i32_nsat:4222; CHECK-NEON:       @ %bb.0: @ %entry4223; CHECK-NEON-NEXT:    .save {r4, lr}4224; CHECK-NEON-NEXT:    push {r4, lr}4225; CHECK-NEON-NEXT:    .vsave {d8, d9, d10, d11}4226; CHECK-NEON-NEXT:    vpush {d8, d9, d10, d11}4227; CHECK-NEON-NEXT:    vmov r0, s04228; CHECK-NEON-NEXT:    vmov.f32 s16, s34229; CHECK-NEON-NEXT:    vmov.f32 s18, s24230; CHECK-NEON-NEXT:    vmov.f32 s20, s14231; CHECK-NEON-NEXT:    bl __aeabi_h2f4232; CHECK-NEON-NEXT:    mov r4, r04233; CHECK-NEON-NEXT:    vmov r0, s164234; CHECK-NEON-NEXT:    bl __aeabi_h2f4235; CHECK-NEON-NEXT:    vmov s16, r04236; CHECK-NEON-NEXT:    vmov r0, s184237; CHECK-NEON-NEXT:    bl __aeabi_h2f4238; CHECK-NEON-NEXT:    vmov s0, r04239; CHECK-NEON-NEXT:    vmov r1, s204240; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s04241; CHECK-NEON-NEXT:    vmov s18, r44242; CHECK-NEON-NEXT:    vmov r0, s04243; CHECK-NEON-NEXT:    vmov.32 d11[0], r04244; CHECK-NEON-NEXT:    mov r0, r14245; CHECK-NEON-NEXT:    bl __aeabi_h2f4246; CHECK-NEON-NEXT:    vcvt.s32.f32 s2, s184247; CHECK-NEON-NEXT:    vmov s0, r04248; CHECK-NEON-NEXT:    vcvt.s32.f32 s4, s164249; CHECK-NEON-NEXT:    vcvt.s32.f32 s0, s04250; CHECK-NEON-NEXT:    vmov.i32 q8, #0x04251; CHECK-NEON-NEXT:    vmov r0, s24252; CHECK-NEON-NEXT:    vmov.32 d10[0], r04253; CHECK-NEON-NEXT:    vmov r0, s44254; CHECK-NEON-NEXT:    vmov.32 d11[1], r04255; CHECK-NEON-NEXT:    vmov r0, s04256; CHECK-NEON-NEXT:    vmov.32 d10[1], r04257; CHECK-NEON-NEXT:    vmin.s32 q9, q5, q84258; CHECK-NEON-NEXT:    vmax.s32 q0, q9, q84259; CHECK-NEON-NEXT:    vpop {d8, d9, d10, d11}4260; CHECK-NEON-NEXT:    pop {r4, pc}4261;4262; CHECK-FP16-LABEL: ustest_f16i32_nsat:4263; CHECK-FP16:       @ %bb.0: @ %entry4264; CHECK-FP16-NEXT:    vmovx.f16 s2, s04265; CHECK-FP16-NEXT:    vcvt.s32.f16 s6, s04266; CHECK-FP16-NEXT:    vcvt.s32.f16 s0, s14267; CHECK-FP16-NEXT:    vmovx.f16 s4, s14268; CHECK-FP16-NEXT:    vmov r0, s04269; CHECK-FP16-NEXT:    vcvt.s32.f16 s4, s44270; CHECK-FP16-NEXT:    vcvt.s32.f16 s2, s24271; CHECK-FP16-NEXT:    vmov.i32 q9, #0x04272; CHECK-FP16-NEXT:    vmov.32 d17[0], r04273; CHECK-FP16-NEXT:    vmov r0, s64274; CHECK-FP16-NEXT:    vmov.32 d16[0], r04275; CHECK-FP16-NEXT:    vmov r0, s44276; CHECK-FP16-NEXT:    vmov.32 d17[1], r04277; CHECK-FP16-NEXT:    vmov r0, s24278; CHECK-FP16-NEXT:    vmov.32 d16[1], r04279; CHECK-FP16-NEXT:    vmin.s32 q8, q8, q94280; CHECK-FP16-NEXT:    vmax.s32 q0, q8, q94281; CHECK-FP16-NEXT:    bx lr4282entry:4283  %conv = fptosi <4 x half> %x to <4 x i32>4284  %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> zeroinitializer, <4 x i32> %conv)4285  %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)4286  ret <4 x i32> %spec.store.select74287}4288 4289declare <2 x i32> @llvm.smin.v2i32(<2 x i32>, <2 x i32>)4290declare <2 x i32> @llvm.smax.v2i32(<2 x i32>, <2 x i32>)4291declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)4292declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)4293declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)4294declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)4295declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)4296declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)4297declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)4298declare <2 x i64> @llvm.smin.v2i64(<2 x i64>, <2 x i64>)4299declare <2 x i64> @llvm.smax.v2i64(<2 x i64>, <2 x i64>)4300declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)4301declare <4 x i64> @llvm.smin.v4i64(<4 x i64>, <4 x i64>)4302declare <4 x i64> @llvm.smax.v4i64(<4 x i64>, <4 x i64>)4303declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)4304declare <2 x i128> @llvm.smin.v2i128(<2 x i128>, <2 x i128>)4305declare <2 x i128> @llvm.smax.v2i128(<2 x i128>, <2 x i128>)4306declare <2 x i128> @llvm.umin.v2i128(<2 x i128>, <2 x i128>)4307