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1; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 %s -o - \2; RUN: | FileCheck %s3 4; rdar://74615105; rdar://109646036 7; Disable this optimization unless we know one of them is zero.8define arm_apcscc i32 @t1(ptr %a, ptr %b) nounwind {9entry:10; CHECK-LABEL: t1:11; CHECK: vldr [[S0:s[0-9]+]],12; CHECK: vldr [[S1:s[0-9]+]],13; CHECK: vcmp.f32 [[S1]], [[S0]]14; CHECK: vmrs APSR_nzcv, fpscr15; CHECK: beq16 %0 = load float, ptr %a17 %1 = load float, ptr %b18 %2 = fcmp une float %0, %119 br i1 %2, label %bb1, label %bb220 21bb1:22 %3 = call i32 @bar()23 ret i32 %324 25bb2:26 %4 = call i32 @foo()27 ret i32 %428}29 30; If one side is zero, the other size sign bit is masked off to allow31; +0.0 == -0.032define arm_apcscc i32 @t2(ptr %a, ptr %b) nounwind {33entry:34; CHECK-LABEL: t2:35; CHECK-NOT: vldr36; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]37; CHECK-NOT: b LBB38; CHECK: bic [[REG2]], [[REG2]], #-214748364839; CHECK: cmp [[REG1]], #040; CHECK: cmpeq [[REG2]], #041; CHECK-NOT: vcmp.f3242; CHECK-NOT: vmrs43; CHECK: bne44 %0 = load double, ptr %a45 %1 = fcmp nnan oeq double %0, 0.000000e+0046 br i1 %1, label %bb1, label %bb247 48bb1:49 %2 = call i32 @bar()50 ret i32 %251 52bb2:53 %3 = call i32 @foo()54 ret i32 %355}56 57define arm_apcscc i32 @t3(ptr %a, ptr %b) nounwind {58entry:59; CHECK-LABEL: t3:60; CHECK-NOT: vldr61; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]62; CHECK: mvn [[REG4:(r[0-9]+)]], #-214748364863; CHECK: tst [[REG3]], [[REG4]]64; CHECK-NOT: vcmp.f3265; CHECK-NOT: vmrs66; CHECK: bne67 %0 = load float, ptr %a68 %1 = fcmp nnan oeq float %0, 0.000000e+0069 br i1 %1, label %bb1, label %bb270 71bb1:72 %2 = call i32 @bar()73 ret i32 %274 75bb2:76 %3 = call i32 @foo()77 ret i32 %378}79 80declare i32 @bar()81declare i32 @foo()82