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1; REQUIRES: asserts2; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < %s 2>&1 | FileCheck %s3 4; This test makes sure spills of 64-bit pairs in Thumb mode actually5; generate thumb instructions. Previously we were inserting an ARM6; STMIA which happened to have the same encoding.7 8define void @foo(ptr %addr) {9 %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)10 %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)11 %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)12 %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)14 %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)15 %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(ptr %addr)16 17 ; Make sure we are actually creating the Thumb versions of the spill18 ; instructions.19; CHECK: t2STRDi820; CHECK: t2LDRDi821 22 store volatile i64 %val1, ptr %addr23 store volatile i64 %val2, ptr %addr24 store volatile i64 %val3, ptr %addr25 store volatile i64 %val4, ptr %addr26 store volatile i64 %val5, ptr %addr27 store volatile i64 %val6, ptr %addr28 store volatile i64 %val7, ptr %addr29 ret void30}31