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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=ARM,ARM63; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=ARM,ARM784; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=ARM,ARM785; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=THUMB,THUMB66; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=THUMB,THUMB787; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=THUMB,THUMB788 9; We are looking for the following pattern here:10; (X & (C l>> Y)) ==/!= 011; It may be optimal to hoist the constant:12; ((X << Y) & C) ==/!= 013 14;------------------------------------------------------------------------------;15; A few scalar test16;------------------------------------------------------------------------------;17 18; i8 scalar19 20define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {21; ARM-LABEL: scalar_i8_signbit_eq:22; ARM: @ %bb.0:23; ARM-NEXT: uxtb r1, r124; ARM-NEXT: lsl r0, r0, r125; ARM-NEXT: mov r1, #126; ARM-NEXT: uxtb r0, r027; ARM-NEXT: eor r0, r1, r0, lsr #728; ARM-NEXT: bx lr29;30; THUMB6-LABEL: scalar_i8_signbit_eq:31; THUMB6: @ %bb.0:32; THUMB6-NEXT: uxtb r1, r133; THUMB6-NEXT: lsls r0, r134; THUMB6-NEXT: movs r1, #12835; THUMB6-NEXT: ands r0, r136; THUMB6-NEXT: rsbs r1, r0, #037; THUMB6-NEXT: adcs r0, r138; THUMB6-NEXT: bx lr39;40; THUMB78-LABEL: scalar_i8_signbit_eq:41; THUMB78: @ %bb.0:42; THUMB78-NEXT: uxtb r1, r143; THUMB78-NEXT: lsls r0, r144; THUMB78-NEXT: movs r1, #145; THUMB78-NEXT: uxtb r0, r046; THUMB78-NEXT: eor.w r0, r1, r0, lsr #747; THUMB78-NEXT: bx lr48 %t0 = lshr i8 128, %y49 %t1 = and i8 %t0, %x50 %res = icmp eq i8 %t1, 051 ret i1 %res52}53 54define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {55; ARM-LABEL: scalar_i8_lowestbit_eq:56; ARM: @ %bb.0:57; ARM-NEXT: uxtb r1, r158; ARM-NEXT: mov r2, #159; ARM-NEXT: bic r0, r2, r0, lsl r160; ARM-NEXT: bx lr61;62; THUMB6-LABEL: scalar_i8_lowestbit_eq:63; THUMB6: @ %bb.0:64; THUMB6-NEXT: uxtb r1, r165; THUMB6-NEXT: lsls r0, r166; THUMB6-NEXT: movs r1, #167; THUMB6-NEXT: ands r0, r168; THUMB6-NEXT: rsbs r1, r0, #069; THUMB6-NEXT: adcs r0, r170; THUMB6-NEXT: bx lr71;72; THUMB78-LABEL: scalar_i8_lowestbit_eq:73; THUMB78: @ %bb.0:74; THUMB78-NEXT: uxtb r1, r175; THUMB78-NEXT: lsls r0, r176; THUMB78-NEXT: movs r1, #177; THUMB78-NEXT: bic.w r0, r1, r078; THUMB78-NEXT: bx lr79 %t0 = lshr i8 1, %y80 %t1 = and i8 %t0, %x81 %res = icmp eq i8 %t1, 082 ret i1 %res83}84 85define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {86; ARM-LABEL: scalar_i8_bitsinmiddle_eq:87; ARM: @ %bb.0:88; ARM-NEXT: uxtb r1, r189; ARM-NEXT: mov r2, #2490; ARM-NEXT: and r0, r2, r0, lsl r191; ARM-NEXT: clz r0, r092; ARM-NEXT: lsr r0, r0, #593; ARM-NEXT: bx lr94;95; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:96; THUMB6: @ %bb.0:97; THUMB6-NEXT: uxtb r1, r198; THUMB6-NEXT: lsls r0, r199; THUMB6-NEXT: movs r1, #24100; THUMB6-NEXT: ands r0, r1101; THUMB6-NEXT: rsbs r1, r0, #0102; THUMB6-NEXT: adcs r0, r1103; THUMB6-NEXT: bx lr104;105; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq:106; THUMB78: @ %bb.0:107; THUMB78-NEXT: uxtb r1, r1108; THUMB78-NEXT: lsls r0, r1109; THUMB78-NEXT: and r0, r0, #24110; THUMB78-NEXT: clz r0, r0111; THUMB78-NEXT: lsrs r0, r0, #5112; THUMB78-NEXT: bx lr113 %t0 = lshr i8 24, %y114 %t1 = and i8 %t0, %x115 %res = icmp eq i8 %t1, 0116 ret i1 %res117}118 119; i16 scalar120 121define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {122; ARM-LABEL: scalar_i16_signbit_eq:123; ARM: @ %bb.0:124; ARM-NEXT: uxth r1, r1125; ARM-NEXT: lsl r0, r0, r1126; ARM-NEXT: mov r1, #1127; ARM-NEXT: uxth r0, r0128; ARM-NEXT: eor r0, r1, r0, lsr #15129; ARM-NEXT: bx lr130;131; THUMB6-LABEL: scalar_i16_signbit_eq:132; THUMB6: @ %bb.0:133; THUMB6-NEXT: uxth r1, r1134; THUMB6-NEXT: lsls r0, r1135; THUMB6-NEXT: movs r1, #1136; THUMB6-NEXT: lsls r1, r1, #15137; THUMB6-NEXT: ands r0, r1138; THUMB6-NEXT: rsbs r1, r0, #0139; THUMB6-NEXT: adcs r0, r1140; THUMB6-NEXT: bx lr141;142; THUMB78-LABEL: scalar_i16_signbit_eq:143; THUMB78: @ %bb.0:144; THUMB78-NEXT: uxth r1, r1145; THUMB78-NEXT: lsls r0, r1146; THUMB78-NEXT: movs r1, #1147; THUMB78-NEXT: uxth r0, r0148; THUMB78-NEXT: eor.w r0, r1, r0, lsr #15149; THUMB78-NEXT: bx lr150 %t0 = lshr i16 32768, %y151 %t1 = and i16 %t0, %x152 %res = icmp eq i16 %t1, 0153 ret i1 %res154}155 156define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {157; ARM-LABEL: scalar_i16_lowestbit_eq:158; ARM: @ %bb.0:159; ARM-NEXT: uxth r1, r1160; ARM-NEXT: mov r2, #1161; ARM-NEXT: bic r0, r2, r0, lsl r1162; ARM-NEXT: bx lr163;164; THUMB6-LABEL: scalar_i16_lowestbit_eq:165; THUMB6: @ %bb.0:166; THUMB6-NEXT: uxth r1, r1167; THUMB6-NEXT: lsls r0, r1168; THUMB6-NEXT: movs r1, #1169; THUMB6-NEXT: ands r0, r1170; THUMB6-NEXT: rsbs r1, r0, #0171; THUMB6-NEXT: adcs r0, r1172; THUMB6-NEXT: bx lr173;174; THUMB78-LABEL: scalar_i16_lowestbit_eq:175; THUMB78: @ %bb.0:176; THUMB78-NEXT: uxth r1, r1177; THUMB78-NEXT: lsls r0, r1178; THUMB78-NEXT: movs r1, #1179; THUMB78-NEXT: bic.w r0, r1, r0180; THUMB78-NEXT: bx lr181 %t0 = lshr i16 1, %y182 %t1 = and i16 %t0, %x183 %res = icmp eq i16 %t1, 0184 ret i1 %res185}186 187define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {188; ARM-LABEL: scalar_i16_bitsinmiddle_eq:189; ARM: @ %bb.0:190; ARM-NEXT: uxth r1, r1191; ARM-NEXT: mov r2, #4080192; ARM-NEXT: and r0, r2, r0, lsl r1193; ARM-NEXT: clz r0, r0194; ARM-NEXT: lsr r0, r0, #5195; ARM-NEXT: bx lr196;197; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:198; THUMB6: @ %bb.0:199; THUMB6-NEXT: uxth r1, r1200; THUMB6-NEXT: lsls r0, r1201; THUMB6-NEXT: movs r1, #255202; THUMB6-NEXT: lsls r1, r1, #4203; THUMB6-NEXT: ands r0, r1204; THUMB6-NEXT: rsbs r1, r0, #0205; THUMB6-NEXT: adcs r0, r1206; THUMB6-NEXT: bx lr207;208; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq:209; THUMB78: @ %bb.0:210; THUMB78-NEXT: uxth r1, r1211; THUMB78-NEXT: lsls r0, r1212; THUMB78-NEXT: and r0, r0, #4080213; THUMB78-NEXT: clz r0, r0214; THUMB78-NEXT: lsrs r0, r0, #5215; THUMB78-NEXT: bx lr216 %t0 = lshr i16 4080, %y217 %t1 = and i16 %t0, %x218 %res = icmp eq i16 %t1, 0219 ret i1 %res220}221 222; i32 scalar223 224define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {225; ARM-LABEL: scalar_i32_signbit_eq:226; ARM: @ %bb.0:227; ARM-NEXT: mvn r0, r0, lsl r1228; ARM-NEXT: lsr r0, r0, #31229; ARM-NEXT: bx lr230;231; THUMB6-LABEL: scalar_i32_signbit_eq:232; THUMB6: @ %bb.0:233; THUMB6-NEXT: lsls r0, r1234; THUMB6-NEXT: movs r1, #1235; THUMB6-NEXT: lsls r1, r1, #31236; THUMB6-NEXT: ands r0, r1237; THUMB6-NEXT: rsbs r1, r0, #0238; THUMB6-NEXT: adcs r0, r1239; THUMB6-NEXT: bx lr240;241; THUMB78-LABEL: scalar_i32_signbit_eq:242; THUMB78: @ %bb.0:243; THUMB78-NEXT: lsls r0, r1244; THUMB78-NEXT: mvns r0, r0245; THUMB78-NEXT: lsrs r0, r0, #31246; THUMB78-NEXT: bx lr247 %t0 = lshr i32 2147483648, %y248 %t1 = and i32 %t0, %x249 %res = icmp eq i32 %t1, 0250 ret i1 %res251}252 253define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {254; ARM-LABEL: scalar_i32_lowestbit_eq:255; ARM: @ %bb.0:256; ARM-NEXT: mov r2, #1257; ARM-NEXT: bic r0, r2, r0, lsl r1258; ARM-NEXT: bx lr259;260; THUMB6-LABEL: scalar_i32_lowestbit_eq:261; THUMB6: @ %bb.0:262; THUMB6-NEXT: lsls r0, r1263; THUMB6-NEXT: movs r1, #1264; THUMB6-NEXT: ands r0, r1265; THUMB6-NEXT: rsbs r1, r0, #0266; THUMB6-NEXT: adcs r0, r1267; THUMB6-NEXT: bx lr268;269; THUMB78-LABEL: scalar_i32_lowestbit_eq:270; THUMB78: @ %bb.0:271; THUMB78-NEXT: lsls r0, r1272; THUMB78-NEXT: movs r1, #1273; THUMB78-NEXT: bic.w r0, r1, r0274; THUMB78-NEXT: bx lr275 %t0 = lshr i32 1, %y276 %t1 = and i32 %t0, %x277 %res = icmp eq i32 %t1, 0278 ret i1 %res279}280 281define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {282; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:283; ARM6: @ %bb.0:284; ARM6-NEXT: mov r2, #65280285; ARM6-NEXT: orr r2, r2, #16711680286; ARM6-NEXT: and r0, r2, r0, lsl r1287; ARM6-NEXT: clz r0, r0288; ARM6-NEXT: lsr r0, r0, #5289; ARM6-NEXT: bx lr290;291; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:292; ARM78: @ %bb.0:293; ARM78-NEXT: movw r2, #65280294; ARM78-NEXT: movt r2, #255295; ARM78-NEXT: and r0, r2, r0, lsl r1296; ARM78-NEXT: clz r0, r0297; ARM78-NEXT: lsr r0, r0, #5298; ARM78-NEXT: bx lr299;300; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:301; THUMB6: @ %bb.0:302; THUMB6-NEXT: lsls r0, r1303; THUMB6-NEXT: ldr r1, .LCPI8_0304; THUMB6-NEXT: ands r0, r1305; THUMB6-NEXT: rsbs r1, r0, #0306; THUMB6-NEXT: adcs r0, r1307; THUMB6-NEXT: bx lr308; THUMB6-NEXT: .p2align 2309; THUMB6-NEXT: @ %bb.1:310; THUMB6-NEXT: .LCPI8_0:311; THUMB6-NEXT: .long 16776960 @ 0xffff00312;313; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:314; THUMB78: @ %bb.0:315; THUMB78-NEXT: lsls r0, r1316; THUMB78-NEXT: movw r1, #65280317; THUMB78-NEXT: movt r1, #255318; THUMB78-NEXT: ands r0, r1319; THUMB78-NEXT: clz r0, r0320; THUMB78-NEXT: lsrs r0, r0, #5321; THUMB78-NEXT: bx lr322 %t0 = lshr i32 16776960, %y323 %t1 = and i32 %t0, %x324 %res = icmp eq i32 %t1, 0325 ret i1 %res326}327 328; i64 scalar329 330define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {331; ARM-LABEL: scalar_i64_signbit_eq:332; ARM: @ %bb.0:333; ARM-NEXT: rsb r3, r2, #32334; ARM-NEXT: lsr r3, r0, r3335; ARM-NEXT: orr r1, r3, r1, lsl r2336; ARM-NEXT: subs r2, r2, #32337; ARM-NEXT: lslpl r1, r0, r2338; ARM-NEXT: mvn r0, r1339; ARM-NEXT: lsr r0, r0, #31340; ARM-NEXT: bx lr341;342; THUMB6-LABEL: scalar_i64_signbit_eq:343; THUMB6: @ %bb.0:344; THUMB6-NEXT: push {r7, lr}345; THUMB6-NEXT: bl __ashldi3346; THUMB6-NEXT: movs r0, #1347; THUMB6-NEXT: lsls r2, r0, #31348; THUMB6-NEXT: ands r2, r1349; THUMB6-NEXT: rsbs r0, r2, #0350; THUMB6-NEXT: adcs r0, r2351; THUMB6-NEXT: pop {r7, pc}352;353; THUMB78-LABEL: scalar_i64_signbit_eq:354; THUMB78: @ %bb.0:355; THUMB78-NEXT: rsb.w r3, r2, #32356; THUMB78-NEXT: lsls r1, r2357; THUMB78-NEXT: subs r2, #32358; THUMB78-NEXT: lsr.w r3, r0, r3359; THUMB78-NEXT: orr.w r1, r1, r3360; THUMB78-NEXT: it pl361; THUMB78-NEXT: lslpl.w r1, r0, r2362; THUMB78-NEXT: mvns r0, r1363; THUMB78-NEXT: lsrs r0, r0, #31364; THUMB78-NEXT: bx lr365 %t0 = lshr i64 9223372036854775808, %y366 %t1 = and i64 %t0, %x367 %res = icmp eq i64 %t1, 0368 ret i1 %res369}370 371define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {372; ARM6-LABEL: scalar_i64_lowestbit_eq:373; ARM6: @ %bb.0:374; ARM6-NEXT: subs r1, r2, #32375; ARM6-NEXT: lsl r0, r0, r2376; ARM6-NEXT: movpl r0, #0377; ARM6-NEXT: mov r1, #1378; ARM6-NEXT: bic r0, r1, r0379; ARM6-NEXT: bx lr380;381; ARM78-LABEL: scalar_i64_lowestbit_eq:382; ARM78: @ %bb.0:383; ARM78-NEXT: subs r1, r2, #32384; ARM78-NEXT: lsl r0, r0, r2385; ARM78-NEXT: movwpl r0, #0386; ARM78-NEXT: mov r1, #1387; ARM78-NEXT: bic r0, r1, r0388; ARM78-NEXT: bx lr389;390; THUMB6-LABEL: scalar_i64_lowestbit_eq:391; THUMB6: @ %bb.0:392; THUMB6-NEXT: push {r7, lr}393; THUMB6-NEXT: bl __ashldi3394; THUMB6-NEXT: movs r1, #1395; THUMB6-NEXT: ands r0, r1396; THUMB6-NEXT: rsbs r1, r0, #0397; THUMB6-NEXT: adcs r0, r1398; THUMB6-NEXT: pop {r7, pc}399;400; THUMB78-LABEL: scalar_i64_lowestbit_eq:401; THUMB78: @ %bb.0:402; THUMB78-NEXT: lsls r0, r2403; THUMB78-NEXT: subs.w r1, r2, #32404; THUMB78-NEXT: it pl405; THUMB78-NEXT: movpl r0, #0406; THUMB78-NEXT: movs r1, #1407; THUMB78-NEXT: bic.w r0, r1, r0408; THUMB78-NEXT: bx lr409 %t0 = lshr i64 1, %y410 %t1 = and i64 %t0, %x411 %res = icmp eq i64 %t1, 0412 ret i1 %res413}414 415define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {416; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:417; ARM6: @ %bb.0:418; ARM6-NEXT: rsb r3, r2, #32419; ARM6-NEXT: lsr r3, r0, r3420; ARM6-NEXT: orr r1, r3, r1, lsl r2421; ARM6-NEXT: subs r3, r2, #32422; ARM6-NEXT: lslpl r1, r0, r3423; ARM6-NEXT: lsl r0, r0, r2424; ARM6-NEXT: movpl r0, #0425; ARM6-NEXT: pkhbt r0, r1, r0426; ARM6-NEXT: clz r0, r0427; ARM6-NEXT: lsr r0, r0, #5428; ARM6-NEXT: bx lr429;430; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:431; ARM78: @ %bb.0:432; ARM78-NEXT: rsb r3, r2, #32433; ARM78-NEXT: lsr r3, r0, r3434; ARM78-NEXT: orr r1, r3, r1, lsl r2435; ARM78-NEXT: subs r3, r2, #32436; ARM78-NEXT: lslpl r1, r0, r3437; ARM78-NEXT: lsl r0, r0, r2438; ARM78-NEXT: movwpl r0, #0439; ARM78-NEXT: pkhbt r0, r1, r0440; ARM78-NEXT: clz r0, r0441; ARM78-NEXT: lsr r0, r0, #5442; ARM78-NEXT: bx lr443;444; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:445; THUMB6: @ %bb.0:446; THUMB6-NEXT: push {r7, lr}447; THUMB6-NEXT: bl __ashldi3448; THUMB6-NEXT: ldr r2, .LCPI11_0449; THUMB6-NEXT: ands r2, r0450; THUMB6-NEXT: uxth r0, r1451; THUMB6-NEXT: adds r1, r2, r0452; THUMB6-NEXT: rsbs r0, r1, #0453; THUMB6-NEXT: adcs r0, r1454; THUMB6-NEXT: pop {r7, pc}455; THUMB6-NEXT: .p2align 2456; THUMB6-NEXT: @ %bb.1:457; THUMB6-NEXT: .LCPI11_0:458; THUMB6-NEXT: .long 4294901760 @ 0xffff0000459;460; THUMB78-LABEL: scalar_i64_bitsinmiddle_eq:461; THUMB78: @ %bb.0:462; THUMB78-NEXT: rsb.w r3, r2, #32463; THUMB78-NEXT: lsls r1, r2464; THUMB78-NEXT: lsr.w r3, r0, r3465; THUMB78-NEXT: orrs r1, r3466; THUMB78-NEXT: subs.w r3, r2, #32467; THUMB78-NEXT: it pl468; THUMB78-NEXT: lslpl.w r1, r0, r3469; THUMB78-NEXT: lsl.w r0, r0, r2470; THUMB78-NEXT: it pl471; THUMB78-NEXT: movpl r0, #0472; THUMB78-NEXT: pkhbt r0, r1, r0473; THUMB78-NEXT: clz r0, r0474; THUMB78-NEXT: lsrs r0, r0, #5475; THUMB78-NEXT: bx lr476 %t0 = lshr i64 281474976645120, %y477 %t1 = and i64 %t0, %x478 %res = icmp eq i64 %t1, 0479 ret i1 %res480}481 482;------------------------------------------------------------------------------;483; A few trivial vector tests484;------------------------------------------------------------------------------;485 486define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {487; ARM6-LABEL: vec_4xi32_splat_eq:488; ARM6: @ %bb.0:489; ARM6-NEXT: push {r11, lr}490; ARM6-NEXT: ldr r12, [sp, #8]491; ARM6-NEXT: mov lr, #1492; ARM6-NEXT: bic r0, lr, r0, lsl r12493; ARM6-NEXT: ldr r12, [sp, #12]494; ARM6-NEXT: bic r1, lr, r1, lsl r12495; ARM6-NEXT: ldr r12, [sp, #16]496; ARM6-NEXT: bic r2, lr, r2, lsl r12497; ARM6-NEXT: ldr r12, [sp, #20]498; ARM6-NEXT: bic r3, lr, r3, lsl r12499; ARM6-NEXT: pop {r11, pc}500;501; ARM78-LABEL: vec_4xi32_splat_eq:502; ARM78: @ %bb.0:503; ARM78-NEXT: vmov d17, r2, r3504; ARM78-NEXT: mov r12, sp505; ARM78-NEXT: vld1.64 {d18, d19}, [r12]506; ARM78-NEXT: vmov d16, r0, r1507; ARM78-NEXT: vmov.i32 q10, #0x1508; ARM78-NEXT: vshl.u32 q8, q8, q9509; ARM78-NEXT: vtst.32 q8, q8, q10510; ARM78-NEXT: vmvn q8, q8511; ARM78-NEXT: vmovn.i32 d16, q8512; ARM78-NEXT: vmov r0, r1, d16513; ARM78-NEXT: bx lr514;515; THUMB6-LABEL: vec_4xi32_splat_eq:516; THUMB6: @ %bb.0:517; THUMB6-NEXT: push {r4, r5, r7, lr}518; THUMB6-NEXT: ldr r4, [sp, #16]519; THUMB6-NEXT: lsls r0, r4520; THUMB6-NEXT: movs r4, #1521; THUMB6-NEXT: ands r0, r4522; THUMB6-NEXT: rsbs r5, r0, #0523; THUMB6-NEXT: adcs r0, r5524; THUMB6-NEXT: ldr r5, [sp, #20]525; THUMB6-NEXT: lsls r1, r5526; THUMB6-NEXT: ands r1, r4527; THUMB6-NEXT: rsbs r5, r1, #0528; THUMB6-NEXT: adcs r1, r5529; THUMB6-NEXT: ldr r5, [sp, #24]530; THUMB6-NEXT: lsls r2, r5531; THUMB6-NEXT: ands r2, r4532; THUMB6-NEXT: rsbs r5, r2, #0533; THUMB6-NEXT: adcs r2, r5534; THUMB6-NEXT: ldr r5, [sp, #28]535; THUMB6-NEXT: lsls r3, r5536; THUMB6-NEXT: ands r3, r4537; THUMB6-NEXT: rsbs r4, r3, #0538; THUMB6-NEXT: adcs r3, r4539; THUMB6-NEXT: pop {r4, r5, r7, pc}540;541; THUMB78-LABEL: vec_4xi32_splat_eq:542; THUMB78: @ %bb.0:543; THUMB78-NEXT: vmov d17, r2, r3544; THUMB78-NEXT: mov r12, sp545; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]546; THUMB78-NEXT: vmov d16, r0, r1547; THUMB78-NEXT: vmov.i32 q10, #0x1548; THUMB78-NEXT: vshl.u32 q8, q8, q9549; THUMB78-NEXT: vtst.32 q8, q8, q10550; THUMB78-NEXT: vmvn q8, q8551; THUMB78-NEXT: vmovn.i32 d16, q8552; THUMB78-NEXT: vmov r0, r1, d16553; THUMB78-NEXT: bx lr554 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y555 %t1 = and <4 x i32> %t0, %x556 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>557 ret <4 x i1> %res558}559 560define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {561; ARM6-LABEL: vec_4xi32_nonsplat_eq:562; ARM6: @ %bb.0:563; ARM6-NEXT: ldr r12, [sp, #4]564; ARM6-NEXT: mov r0, #1565; ARM6-NEXT: bic r1, r0, r1, lsl r12566; ARM6-NEXT: ldr r12, [sp, #8]567; ARM6-NEXT: mov r0, #65280568; ARM6-NEXT: orr r0, r0, #16711680569; ARM6-NEXT: and r0, r0, r2, lsl r12570; ARM6-NEXT: clz r0, r0571; ARM6-NEXT: lsr r2, r0, #5572; ARM6-NEXT: ldr r0, [sp, #12]573; ARM6-NEXT: mvn r0, r3, lsl r0574; ARM6-NEXT: lsr r3, r0, #31575; ARM6-NEXT: mov r0, #1576; ARM6-NEXT: bx lr577;578; ARM78-LABEL: vec_4xi32_nonsplat_eq:579; ARM78: @ %bb.0:580; ARM78-NEXT: mov r12, sp581; ARM78-NEXT: vld1.64 {d16, d17}, [r12]582; ARM78-NEXT: adr r12, .LCPI13_0583; ARM78-NEXT: vneg.s32 q8, q8584; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128]585; ARM78-NEXT: vshl.u32 q8, q9, q8586; ARM78-NEXT: vmov d19, r2, r3587; ARM78-NEXT: vmov d18, r0, r1588; ARM78-NEXT: vtst.32 q8, q8, q9589; ARM78-NEXT: vmvn q8, q8590; ARM78-NEXT: vmovn.i32 d16, q8591; ARM78-NEXT: vmov r0, r1, d16592; ARM78-NEXT: bx lr593; ARM78-NEXT: .p2align 4594; ARM78-NEXT: @ %bb.1:595; ARM78-NEXT: .LCPI13_0:596; ARM78-NEXT: .long 0 @ 0x0597; ARM78-NEXT: .long 1 @ 0x1598; ARM78-NEXT: .long 16776960 @ 0xffff00599; ARM78-NEXT: .long 2147483648 @ 0x80000000600;601; THUMB6-LABEL: vec_4xi32_nonsplat_eq:602; THUMB6: @ %bb.0:603; THUMB6-NEXT: push {r4, lr}604; THUMB6-NEXT: ldr r0, [sp, #12]605; THUMB6-NEXT: lsls r1, r0606; THUMB6-NEXT: movs r0, #1607; THUMB6-NEXT: ands r1, r0608; THUMB6-NEXT: rsbs r4, r1, #0609; THUMB6-NEXT: adcs r1, r4610; THUMB6-NEXT: ldr r4, [sp, #16]611; THUMB6-NEXT: lsls r2, r4612; THUMB6-NEXT: ldr r4, .LCPI13_0613; THUMB6-NEXT: ands r2, r4614; THUMB6-NEXT: rsbs r4, r2, #0615; THUMB6-NEXT: adcs r2, r4616; THUMB6-NEXT: ldr r4, [sp, #20]617; THUMB6-NEXT: lsls r3, r4618; THUMB6-NEXT: lsls r4, r0, #31619; THUMB6-NEXT: ands r3, r4620; THUMB6-NEXT: rsbs r4, r3, #0621; THUMB6-NEXT: adcs r3, r4622; THUMB6-NEXT: pop {r4, pc}623; THUMB6-NEXT: .p2align 2624; THUMB6-NEXT: @ %bb.1:625; THUMB6-NEXT: .LCPI13_0:626; THUMB6-NEXT: .long 16776960 @ 0xffff00627;628; THUMB78-LABEL: vec_4xi32_nonsplat_eq:629; THUMB78: @ %bb.0:630; THUMB78-NEXT: mov r12, sp631; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]632; THUMB78-NEXT: adr.w r12, .LCPI13_0633; THUMB78-NEXT: vneg.s32 q8, q8634; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128]635; THUMB78-NEXT: vshl.u32 q8, q9, q8636; THUMB78-NEXT: vmov d19, r2, r3637; THUMB78-NEXT: vmov d18, r0, r1638; THUMB78-NEXT: vtst.32 q8, q8, q9639; THUMB78-NEXT: vmvn q8, q8640; THUMB78-NEXT: vmovn.i32 d16, q8641; THUMB78-NEXT: vmov r0, r1, d16642; THUMB78-NEXT: bx lr643; THUMB78-NEXT: .p2align 4644; THUMB78-NEXT: @ %bb.1:645; THUMB78-NEXT: .LCPI13_0:646; THUMB78-NEXT: .long 0 @ 0x0647; THUMB78-NEXT: .long 1 @ 0x1648; THUMB78-NEXT: .long 16776960 @ 0xffff00649; THUMB78-NEXT: .long 2147483648 @ 0x80000000650 %t0 = lshr <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y651 %t1 = and <4 x i32> %t0, %x652 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>653 ret <4 x i1> %res654}655 656define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {657; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:658; ARM6: @ %bb.0:659; ARM6-NEXT: push {r11, lr}660; ARM6-NEXT: ldr r2, [sp, #12]661; ARM6-NEXT: mov lr, #1662; ARM6-NEXT: ldr r12, [sp, #8]663; ARM6-NEXT: bic r1, lr, r1, lsl r2664; ARM6-NEXT: ldr r2, [sp, #20]665; ARM6-NEXT: bic r0, lr, r0, lsl r12666; ARM6-NEXT: bic r3, lr, r3, lsl r2667; ARM6-NEXT: mov r2, #1668; ARM6-NEXT: pop {r11, pc}669;670; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:671; ARM78: @ %bb.0:672; ARM78-NEXT: vmov d17, r2, r3673; ARM78-NEXT: mov r12, sp674; ARM78-NEXT: vld1.64 {d18, d19}, [r12]675; ARM78-NEXT: vmov d16, r0, r1676; ARM78-NEXT: vmov.i32 q10, #0x1677; ARM78-NEXT: vshl.u32 q8, q8, q9678; ARM78-NEXT: vtst.32 q8, q8, q10679; ARM78-NEXT: vmvn q8, q8680; ARM78-NEXT: vmovn.i32 d16, q8681; ARM78-NEXT: vmov r0, r1, d16682; ARM78-NEXT: bx lr683;684; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:685; THUMB6: @ %bb.0:686; THUMB6-NEXT: push {r4, lr}687; THUMB6-NEXT: ldr r2, [sp, #8]688; THUMB6-NEXT: lsls r0, r2689; THUMB6-NEXT: movs r2, #1690; THUMB6-NEXT: ands r0, r2691; THUMB6-NEXT: rsbs r4, r0, #0692; THUMB6-NEXT: adcs r0, r4693; THUMB6-NEXT: ldr r4, [sp, #12]694; THUMB6-NEXT: lsls r1, r4695; THUMB6-NEXT: ands r1, r2696; THUMB6-NEXT: rsbs r4, r1, #0697; THUMB6-NEXT: adcs r1, r4698; THUMB6-NEXT: ldr r4, [sp, #20]699; THUMB6-NEXT: lsls r3, r4700; THUMB6-NEXT: ands r3, r2701; THUMB6-NEXT: rsbs r4, r3, #0702; THUMB6-NEXT: adcs r3, r4703; THUMB6-NEXT: pop {r4, pc}704;705; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:706; THUMB78: @ %bb.0:707; THUMB78-NEXT: vmov d17, r2, r3708; THUMB78-NEXT: mov r12, sp709; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]710; THUMB78-NEXT: vmov d16, r0, r1711; THUMB78-NEXT: vmov.i32 q10, #0x1712; THUMB78-NEXT: vshl.u32 q8, q8, q9713; THUMB78-NEXT: vtst.32 q8, q8, q10714; THUMB78-NEXT: vmvn q8, q8715; THUMB78-NEXT: vmovn.i32 d16, q8716; THUMB78-NEXT: vmov r0, r1, d16717; THUMB78-NEXT: bx lr718 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y719 %t1 = and <4 x i32> %t0, %x720 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>721 ret <4 x i1> %res722}723define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {724; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:725; ARM6: @ %bb.0:726; ARM6-NEXT: push {r11, lr}727; ARM6-NEXT: ldr r2, [sp, #12]728; ARM6-NEXT: mov lr, #1729; ARM6-NEXT: ldr r12, [sp, #8]730; ARM6-NEXT: bic r1, lr, r1, lsl r2731; ARM6-NEXT: ldr r2, [sp, #20]732; ARM6-NEXT: bic r0, lr, r0, lsl r12733; ARM6-NEXT: bic r3, lr, r3, lsl r2734; ARM6-NEXT: pop {r11, pc}735;736; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:737; ARM78: @ %bb.0:738; ARM78-NEXT: mov r12, sp739; ARM78-NEXT: vld1.64 {d16, d17}, [r12]740; ARM78-NEXT: vmov.i32 q9, #0x1741; ARM78-NEXT: vneg.s32 q8, q8742; ARM78-NEXT: vshl.u32 q8, q9, q8743; ARM78-NEXT: vmov d19, r2, r3744; ARM78-NEXT: vmov d18, r0, r1745; ARM78-NEXT: vtst.32 q8, q8, q9746; ARM78-NEXT: vmvn q8, q8747; ARM78-NEXT: vmovn.i32 d16, q8748; ARM78-NEXT: vmov r0, r1, d16749; ARM78-NEXT: bx lr750;751; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:752; THUMB6: @ %bb.0:753; THUMB6-NEXT: push {r4, lr}754; THUMB6-NEXT: ldr r2, [sp, #8]755; THUMB6-NEXT: lsls r0, r2756; THUMB6-NEXT: movs r2, #1757; THUMB6-NEXT: ands r0, r2758; THUMB6-NEXT: rsbs r4, r0, #0759; THUMB6-NEXT: adcs r0, r4760; THUMB6-NEXT: ldr r4, [sp, #12]761; THUMB6-NEXT: lsls r1, r4762; THUMB6-NEXT: ands r1, r2763; THUMB6-NEXT: rsbs r4, r1, #0764; THUMB6-NEXT: adcs r1, r4765; THUMB6-NEXT: ldr r4, [sp, #20]766; THUMB6-NEXT: lsls r3, r4767; THUMB6-NEXT: ands r3, r2768; THUMB6-NEXT: rsbs r2, r3, #0769; THUMB6-NEXT: adcs r3, r2770; THUMB6-NEXT: pop {r4, pc}771;772; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:773; THUMB78: @ %bb.0:774; THUMB78-NEXT: mov r12, sp775; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]776; THUMB78-NEXT: vmov.i32 q9, #0x1777; THUMB78-NEXT: vneg.s32 q8, q8778; THUMB78-NEXT: vshl.u32 q8, q9, q8779; THUMB78-NEXT: vmov d19, r2, r3780; THUMB78-NEXT: vmov d18, r0, r1781; THUMB78-NEXT: vtst.32 q8, q8, q9782; THUMB78-NEXT: vmvn q8, q8783; THUMB78-NEXT: vmovn.i32 d16, q8784; THUMB78-NEXT: vmov r0, r1, d16785; THUMB78-NEXT: bx lr786 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y787 %t1 = and <4 x i32> %t0, %x788 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>789 ret <4 x i1> %res790}791define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {792; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:793; ARM6: @ %bb.0:794; ARM6-NEXT: push {r11, lr}795; ARM6-NEXT: ldr r2, [sp, #12]796; ARM6-NEXT: mov lr, #1797; ARM6-NEXT: ldr r12, [sp, #8]798; ARM6-NEXT: bic r1, lr, r1, lsl r2799; ARM6-NEXT: ldr r2, [sp, #20]800; ARM6-NEXT: bic r0, lr, r0, lsl r12801; ARM6-NEXT: bic r3, lr, r3, lsl r2802; ARM6-NEXT: pop {r11, pc}803;804; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:805; ARM78: @ %bb.0:806; ARM78-NEXT: mov r12, sp807; ARM78-NEXT: vld1.64 {d16, d17}, [r12]808; ARM78-NEXT: vmov.i32 q9, #0x1809; ARM78-NEXT: vneg.s32 q8, q8810; ARM78-NEXT: vshl.u32 q8, q9, q8811; ARM78-NEXT: vmov d19, r2, r3812; ARM78-NEXT: vmov d18, r0, r1813; ARM78-NEXT: vtst.32 q8, q8, q9814; ARM78-NEXT: vmvn q8, q8815; ARM78-NEXT: vmovn.i32 d16, q8816; ARM78-NEXT: vmov r0, r1, d16817; ARM78-NEXT: bx lr818;819; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:820; THUMB6: @ %bb.0:821; THUMB6-NEXT: push {r4, lr}822; THUMB6-NEXT: ldr r2, [sp, #8]823; THUMB6-NEXT: lsls r0, r2824; THUMB6-NEXT: movs r2, #1825; THUMB6-NEXT: ands r0, r2826; THUMB6-NEXT: rsbs r4, r0, #0827; THUMB6-NEXT: adcs r0, r4828; THUMB6-NEXT: ldr r4, [sp, #12]829; THUMB6-NEXT: lsls r1, r4830; THUMB6-NEXT: ands r1, r2831; THUMB6-NEXT: rsbs r4, r1, #0832; THUMB6-NEXT: adcs r1, r4833; THUMB6-NEXT: ldr r4, [sp, #20]834; THUMB6-NEXT: lsls r3, r4835; THUMB6-NEXT: ands r3, r2836; THUMB6-NEXT: rsbs r2, r3, #0837; THUMB6-NEXT: adcs r3, r2838; THUMB6-NEXT: pop {r4, pc}839;840; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:841; THUMB78: @ %bb.0:842; THUMB78-NEXT: mov r12, sp843; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]844; THUMB78-NEXT: vmov.i32 q9, #0x1845; THUMB78-NEXT: vneg.s32 q8, q8846; THUMB78-NEXT: vshl.u32 q8, q9, q8847; THUMB78-NEXT: vmov d19, r2, r3848; THUMB78-NEXT: vmov d18, r0, r1849; THUMB78-NEXT: vtst.32 q8, q8, q9850; THUMB78-NEXT: vmvn q8, q8851; THUMB78-NEXT: vmovn.i32 d16, q8852; THUMB78-NEXT: vmov r0, r1, d16853; THUMB78-NEXT: bx lr854 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y855 %t1 = and <4 x i32> %t0, %x856 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>857 ret <4 x i1> %res858}859 860;------------------------------------------------------------------------------;861; A special tests862;------------------------------------------------------------------------------;863 864define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {865; ARM-LABEL: scalar_i8_signbit_ne:866; ARM: @ %bb.0:867; ARM-NEXT: uxtb r1, r1868; ARM-NEXT: lsl r0, r0, r1869; ARM-NEXT: uxtb r0, r0870; ARM-NEXT: lsr r0, r0, #7871; ARM-NEXT: bx lr872;873; THUMB-LABEL: scalar_i8_signbit_ne:874; THUMB: @ %bb.0:875; THUMB-NEXT: uxtb r1, r1876; THUMB-NEXT: lsls r0, r1877; THUMB-NEXT: uxtb r0, r0878; THUMB-NEXT: lsrs r0, r0, #7879; THUMB-NEXT: bx lr880 %t0 = lshr i8 128, %y881 %t1 = and i8 %t0, %x882 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate883 ret i1 %res884}885 886;------------------------------------------------------------------------------;887; What if X is a constant too?888;------------------------------------------------------------------------------;889 890define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {891; ARM6-LABEL: scalar_i32_x_is_const_eq:892; ARM6: @ %bb.0:893; ARM6-NEXT: ldr r1, .LCPI18_0894; ARM6-NEXT: mov r2, #1895; ARM6-NEXT: bic r0, r2, r1, lsr r0896; ARM6-NEXT: bx lr897; ARM6-NEXT: .p2align 2898; ARM6-NEXT: @ %bb.1:899; ARM6-NEXT: .LCPI18_0:900; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55901;902; ARM78-LABEL: scalar_i32_x_is_const_eq:903; ARM78: @ %bb.0:904; ARM78-NEXT: movw r1, #43605905; ARM78-NEXT: mov r2, #1906; ARM78-NEXT: movt r1, #43605907; ARM78-NEXT: bic r0, r2, r1, lsr r0908; ARM78-NEXT: bx lr909;910; THUMB6-LABEL: scalar_i32_x_is_const_eq:911; THUMB6: @ %bb.0:912; THUMB6-NEXT: ldr r1, .LCPI18_0913; THUMB6-NEXT: lsrs r1, r0914; THUMB6-NEXT: movs r2, #1915; THUMB6-NEXT: ands r2, r1916; THUMB6-NEXT: rsbs r0, r2, #0917; THUMB6-NEXT: adcs r0, r2918; THUMB6-NEXT: bx lr919; THUMB6-NEXT: .p2align 2920; THUMB6-NEXT: @ %bb.1:921; THUMB6-NEXT: .LCPI18_0:922; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55923;924; THUMB78-LABEL: scalar_i32_x_is_const_eq:925; THUMB78: @ %bb.0:926; THUMB78-NEXT: movw r1, #43605927; THUMB78-NEXT: movt r1, #43605928; THUMB78-NEXT: lsr.w r0, r1, r0929; THUMB78-NEXT: movs r1, #1930; THUMB78-NEXT: bic.w r0, r1, r0931; THUMB78-NEXT: bx lr932 %t0 = lshr i32 2857740885, %y933 %t1 = and i32 %t0, 1934 %res = icmp eq i32 %t1, 0935 ret i1 %res936}937define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {938; ARM-LABEL: scalar_i32_x_is_const2_eq:939; ARM: @ %bb.0:940; ARM-NEXT: mov r1, #1941; ARM-NEXT: eor r0, r1, r1, lsr r0942; ARM-NEXT: bx lr943;944; THUMB6-LABEL: scalar_i32_x_is_const2_eq:945; THUMB6: @ %bb.0:946; THUMB6-NEXT: movs r1, #1947; THUMB6-NEXT: lsrs r1, r0948; THUMB6-NEXT: rsbs r0, r1, #0949; THUMB6-NEXT: adcs r0, r1950; THUMB6-NEXT: bx lr951;952; THUMB78-LABEL: scalar_i32_x_is_const2_eq:953; THUMB78: @ %bb.0:954; THUMB78-NEXT: movs r1, #1955; THUMB78-NEXT: lsr.w r0, r1, r0956; THUMB78-NEXT: eor r0, r0, #1957; THUMB78-NEXT: bx lr958 %t0 = lshr i32 1, %y959 %t1 = and i32 %t0, 2857740885960 %res = icmp eq i32 %t1, 0961 ret i1 %res962}963 964;------------------------------------------------------------------------------;965; A few negative tests966;------------------------------------------------------------------------------;967 968define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {969; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:970; ARM6: @ %bb.0:971; ARM6-NEXT: uxtb r1, r1972; ARM6-NEXT: mov r2, #24973; ARM6-NEXT: ands r0, r0, r2, lsr r1974; ARM6-NEXT: mov r0, #0975; ARM6-NEXT: movmi r0, #1976; ARM6-NEXT: bx lr977;978; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:979; ARM78: @ %bb.0:980; ARM78-NEXT: uxtb r1, r1981; ARM78-NEXT: mov r2, #24982; ARM78-NEXT: ands r0, r0, r2, lsr r1983; ARM78-NEXT: mov r0, #0984; ARM78-NEXT: movwmi r0, #1985; ARM78-NEXT: bx lr986;987; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:988; THUMB6: @ %bb.0:989; THUMB6-NEXT: uxtb r1, r1990; THUMB6-NEXT: movs r2, #24991; THUMB6-NEXT: lsrs r2, r1992; THUMB6-NEXT: ands r2, r0993; THUMB6-NEXT: bmi .LBB20_2994; THUMB6-NEXT: @ %bb.1:995; THUMB6-NEXT: movs r0, #0996; THUMB6-NEXT: bx lr997; THUMB6-NEXT: .LBB20_2:998; THUMB6-NEXT: movs r0, #1999; THUMB6-NEXT: bx lr1000;1001; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:1002; THUMB78: @ %bb.0:1003; THUMB78-NEXT: uxtb r1, r11004; THUMB78-NEXT: movs r2, #241005; THUMB78-NEXT: lsr.w r1, r2, r11006; THUMB78-NEXT: ands r0, r11007; THUMB78-NEXT: mov.w r0, #01008; THUMB78-NEXT: it mi1009; THUMB78-NEXT: movmi r0, #11010; THUMB78-NEXT: bx lr1011 %t0 = lshr i8 24, %y1012 %t1 = and i8 %t0, %x1013 %res = icmp slt i8 %t1, 01014 ret i1 %res1015}1016 1017define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {1018; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:1019; ARM: @ %bb.0:1020; ARM-NEXT: uxtb r1, r11021; ARM-NEXT: mov r2, #1281022; ARM-NEXT: and r0, r0, r2, lsr r11023; ARM-NEXT: sub r0, r0, #11024; ARM-NEXT: clz r0, r01025; ARM-NEXT: lsr r0, r0, #51026; ARM-NEXT: bx lr1027;1028; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:1029; THUMB6: @ %bb.0:1030; THUMB6-NEXT: uxtb r1, r11031; THUMB6-NEXT: movs r2, #1281032; THUMB6-NEXT: lsrs r2, r11033; THUMB6-NEXT: ands r2, r01034; THUMB6-NEXT: subs r1, r2, #11035; THUMB6-NEXT: rsbs r0, r1, #01036; THUMB6-NEXT: adcs r0, r11037; THUMB6-NEXT: bx lr1038;1039; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:1040; THUMB78: @ %bb.0:1041; THUMB78-NEXT: uxtb r1, r11042; THUMB78-NEXT: movs r2, #1281043; THUMB78-NEXT: lsr.w r1, r2, r11044; THUMB78-NEXT: ands r0, r11045; THUMB78-NEXT: subs r0, #11046; THUMB78-NEXT: clz r0, r01047; THUMB78-NEXT: lsrs r0, r0, #51048; THUMB78-NEXT: bx lr1049 %t0 = lshr i8 128, %y1050 %t1 = and i8 %t0, %x1051 %res = icmp eq i8 %t1, 1 ; should be comparing with 01052 ret i1 %res1053}1054