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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=ARM,ARM63; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=ARM,ARM784; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=ARM,ARM785; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=THUMB,THUMB66; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=THUMB,THUMB787; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=THUMB,THUMB788 9; We are looking for the following pattern here:10; (X & (C << Y)) ==/!= 011; It may be optimal to hoist the constant:12; ((X l>> Y) & C) ==/!= 013 14;------------------------------------------------------------------------------;15; A few scalar test16;------------------------------------------------------------------------------;17 18; i8 scalar19 20define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {21; ARM-LABEL: scalar_i8_signbit_eq:22; ARM: @ %bb.0:23; ARM-NEXT: uxtb r1, r124; ARM-NEXT: uxtb r0, r025; ARM-NEXT: lsr r0, r0, r126; ARM-NEXT: mov r1, #127; ARM-NEXT: eor r0, r1, r0, lsr #728; ARM-NEXT: bx lr29;30; THUMB6-LABEL: scalar_i8_signbit_eq:31; THUMB6: @ %bb.0:32; THUMB6-NEXT: uxtb r1, r133; THUMB6-NEXT: uxtb r0, r034; THUMB6-NEXT: lsrs r0, r135; THUMB6-NEXT: movs r1, #12836; THUMB6-NEXT: ands r1, r037; THUMB6-NEXT: rsbs r0, r1, #038; THUMB6-NEXT: adcs r0, r139; THUMB6-NEXT: bx lr40;41; THUMB78-LABEL: scalar_i8_signbit_eq:42; THUMB78: @ %bb.0:43; THUMB78-NEXT: uxtb r1, r144; THUMB78-NEXT: uxtb r0, r045; THUMB78-NEXT: lsrs r0, r146; THUMB78-NEXT: movs r1, #147; THUMB78-NEXT: eor.w r0, r1, r0, lsr #748; THUMB78-NEXT: bx lr49 %t0 = shl i8 128, %y50 %t1 = and i8 %t0, %x51 %res = icmp eq i8 %t1, 052 ret i1 %res53}54 55define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {56; ARM-LABEL: scalar_i8_lowestbit_eq:57; ARM: @ %bb.0:58; ARM-NEXT: uxtb r1, r159; ARM-NEXT: uxtb r0, r060; ARM-NEXT: mov r2, #161; ARM-NEXT: bic r0, r2, r0, lsr r162; ARM-NEXT: bx lr63;64; THUMB6-LABEL: scalar_i8_lowestbit_eq:65; THUMB6: @ %bb.0:66; THUMB6-NEXT: uxtb r1, r167; THUMB6-NEXT: uxtb r0, r068; THUMB6-NEXT: lsrs r0, r169; THUMB6-NEXT: movs r1, #170; THUMB6-NEXT: ands r1, r071; THUMB6-NEXT: rsbs r0, r1, #072; THUMB6-NEXT: adcs r0, r173; THUMB6-NEXT: bx lr74;75; THUMB78-LABEL: scalar_i8_lowestbit_eq:76; THUMB78: @ %bb.0:77; THUMB78-NEXT: uxtb r1, r178; THUMB78-NEXT: uxtb r0, r079; THUMB78-NEXT: lsrs r0, r180; THUMB78-NEXT: movs r1, #181; THUMB78-NEXT: bic.w r0, r1, r082; THUMB78-NEXT: bx lr83 %t0 = shl i8 1, %y84 %t1 = and i8 %t0, %x85 %res = icmp eq i8 %t1, 086 ret i1 %res87}88 89define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {90; ARM-LABEL: scalar_i8_bitsinmiddle_eq:91; ARM: @ %bb.0:92; ARM-NEXT: uxtb r1, r193; ARM-NEXT: uxtb r0, r094; ARM-NEXT: mov r2, #2495; ARM-NEXT: and r0, r2, r0, lsr r196; ARM-NEXT: clz r0, r097; ARM-NEXT: lsr r0, r0, #598; ARM-NEXT: bx lr99;100; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:101; THUMB6: @ %bb.0:102; THUMB6-NEXT: uxtb r1, r1103; THUMB6-NEXT: uxtb r0, r0104; THUMB6-NEXT: lsrs r0, r1105; THUMB6-NEXT: movs r1, #24106; THUMB6-NEXT: ands r1, r0107; THUMB6-NEXT: rsbs r0, r1, #0108; THUMB6-NEXT: adcs r0, r1109; THUMB6-NEXT: bx lr110;111; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq:112; THUMB78: @ %bb.0:113; THUMB78-NEXT: uxtb r1, r1114; THUMB78-NEXT: uxtb r0, r0115; THUMB78-NEXT: lsrs r0, r1116; THUMB78-NEXT: and r0, r0, #24117; THUMB78-NEXT: clz r0, r0118; THUMB78-NEXT: lsrs r0, r0, #5119; THUMB78-NEXT: bx lr120 %t0 = shl i8 24, %y121 %t1 = and i8 %t0, %x122 %res = icmp eq i8 %t1, 0123 ret i1 %res124}125 126; i16 scalar127 128define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {129; ARM-LABEL: scalar_i16_signbit_eq:130; ARM: @ %bb.0:131; ARM-NEXT: uxth r1, r1132; ARM-NEXT: uxth r0, r0133; ARM-NEXT: lsr r0, r0, r1134; ARM-NEXT: mov r1, #1135; ARM-NEXT: eor r0, r1, r0, lsr #15136; ARM-NEXT: bx lr137;138; THUMB6-LABEL: scalar_i16_signbit_eq:139; THUMB6: @ %bb.0:140; THUMB6-NEXT: uxth r1, r1141; THUMB6-NEXT: uxth r0, r0142; THUMB6-NEXT: lsrs r0, r1143; THUMB6-NEXT: movs r1, #1144; THUMB6-NEXT: lsls r1, r1, #15145; THUMB6-NEXT: ands r1, r0146; THUMB6-NEXT: rsbs r0, r1, #0147; THUMB6-NEXT: adcs r0, r1148; THUMB6-NEXT: bx lr149;150; THUMB78-LABEL: scalar_i16_signbit_eq:151; THUMB78: @ %bb.0:152; THUMB78-NEXT: uxth r1, r1153; THUMB78-NEXT: uxth r0, r0154; THUMB78-NEXT: lsrs r0, r1155; THUMB78-NEXT: movs r1, #1156; THUMB78-NEXT: eor.w r0, r1, r0, lsr #15157; THUMB78-NEXT: bx lr158 %t0 = shl i16 32768, %y159 %t1 = and i16 %t0, %x160 %res = icmp eq i16 %t1, 0161 ret i1 %res162}163 164define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {165; ARM-LABEL: scalar_i16_lowestbit_eq:166; ARM: @ %bb.0:167; ARM-NEXT: uxth r1, r1168; ARM-NEXT: uxth r0, r0169; ARM-NEXT: mov r2, #1170; ARM-NEXT: bic r0, r2, r0, lsr r1171; ARM-NEXT: bx lr172;173; THUMB6-LABEL: scalar_i16_lowestbit_eq:174; THUMB6: @ %bb.0:175; THUMB6-NEXT: uxth r1, r1176; THUMB6-NEXT: uxth r0, r0177; THUMB6-NEXT: lsrs r0, r1178; THUMB6-NEXT: movs r1, #1179; THUMB6-NEXT: ands r1, r0180; THUMB6-NEXT: rsbs r0, r1, #0181; THUMB6-NEXT: adcs r0, r1182; THUMB6-NEXT: bx lr183;184; THUMB78-LABEL: scalar_i16_lowestbit_eq:185; THUMB78: @ %bb.0:186; THUMB78-NEXT: uxth r1, r1187; THUMB78-NEXT: uxth r0, r0188; THUMB78-NEXT: lsrs r0, r1189; THUMB78-NEXT: movs r1, #1190; THUMB78-NEXT: bic.w r0, r1, r0191; THUMB78-NEXT: bx lr192 %t0 = shl i16 1, %y193 %t1 = and i16 %t0, %x194 %res = icmp eq i16 %t1, 0195 ret i1 %res196}197 198define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {199; ARM-LABEL: scalar_i16_bitsinmiddle_eq:200; ARM: @ %bb.0:201; ARM-NEXT: uxth r1, r1202; ARM-NEXT: uxth r0, r0203; ARM-NEXT: mov r2, #4080204; ARM-NEXT: and r0, r2, r0, lsr r1205; ARM-NEXT: clz r0, r0206; ARM-NEXT: lsr r0, r0, #5207; ARM-NEXT: bx lr208;209; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:210; THUMB6: @ %bb.0:211; THUMB6-NEXT: uxth r1, r1212; THUMB6-NEXT: uxth r0, r0213; THUMB6-NEXT: lsrs r0, r1214; THUMB6-NEXT: movs r1, #255215; THUMB6-NEXT: lsls r1, r1, #4216; THUMB6-NEXT: ands r1, r0217; THUMB6-NEXT: rsbs r0, r1, #0218; THUMB6-NEXT: adcs r0, r1219; THUMB6-NEXT: bx lr220;221; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq:222; THUMB78: @ %bb.0:223; THUMB78-NEXT: uxth r1, r1224; THUMB78-NEXT: uxth r0, r0225; THUMB78-NEXT: lsrs r0, r1226; THUMB78-NEXT: and r0, r0, #4080227; THUMB78-NEXT: clz r0, r0228; THUMB78-NEXT: lsrs r0, r0, #5229; THUMB78-NEXT: bx lr230 %t0 = shl i16 4080, %y231 %t1 = and i16 %t0, %x232 %res = icmp eq i16 %t1, 0233 ret i1 %res234}235 236; i32 scalar237 238define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {239; ARM-LABEL: scalar_i32_signbit_eq:240; ARM: @ %bb.0:241; ARM-NEXT: mvn r0, r0, lsr r1242; ARM-NEXT: lsr r0, r0, #31243; ARM-NEXT: bx lr244;245; THUMB6-LABEL: scalar_i32_signbit_eq:246; THUMB6: @ %bb.0:247; THUMB6-NEXT: lsrs r0, r1248; THUMB6-NEXT: movs r1, #1249; THUMB6-NEXT: lsls r1, r1, #31250; THUMB6-NEXT: ands r0, r1251; THUMB6-NEXT: rsbs r1, r0, #0252; THUMB6-NEXT: adcs r0, r1253; THUMB6-NEXT: bx lr254;255; THUMB78-LABEL: scalar_i32_signbit_eq:256; THUMB78: @ %bb.0:257; THUMB78-NEXT: lsrs r0, r1258; THUMB78-NEXT: mvns r0, r0259; THUMB78-NEXT: lsrs r0, r0, #31260; THUMB78-NEXT: bx lr261 %t0 = shl i32 2147483648, %y262 %t1 = and i32 %t0, %x263 %res = icmp eq i32 %t1, 0264 ret i1 %res265}266 267define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {268; ARM-LABEL: scalar_i32_lowestbit_eq:269; ARM: @ %bb.0:270; ARM-NEXT: mov r2, #1271; ARM-NEXT: bic r0, r2, r0, lsr r1272; ARM-NEXT: bx lr273;274; THUMB6-LABEL: scalar_i32_lowestbit_eq:275; THUMB6: @ %bb.0:276; THUMB6-NEXT: lsrs r0, r1277; THUMB6-NEXT: movs r1, #1278; THUMB6-NEXT: ands r0, r1279; THUMB6-NEXT: rsbs r1, r0, #0280; THUMB6-NEXT: adcs r0, r1281; THUMB6-NEXT: bx lr282;283; THUMB78-LABEL: scalar_i32_lowestbit_eq:284; THUMB78: @ %bb.0:285; THUMB78-NEXT: lsrs r0, r1286; THUMB78-NEXT: movs r1, #1287; THUMB78-NEXT: bic.w r0, r1, r0288; THUMB78-NEXT: bx lr289 %t0 = shl i32 1, %y290 %t1 = and i32 %t0, %x291 %res = icmp eq i32 %t1, 0292 ret i1 %res293}294 295define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {296; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:297; ARM6: @ %bb.0:298; ARM6-NEXT: mov r2, #65280299; ARM6-NEXT: orr r2, r2, #16711680300; ARM6-NEXT: and r0, r2, r0, lsr r1301; ARM6-NEXT: clz r0, r0302; ARM6-NEXT: lsr r0, r0, #5303; ARM6-NEXT: bx lr304;305; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:306; ARM78: @ %bb.0:307; ARM78-NEXT: movw r2, #65280308; ARM78-NEXT: movt r2, #255309; ARM78-NEXT: and r0, r2, r0, lsr r1310; ARM78-NEXT: clz r0, r0311; ARM78-NEXT: lsr r0, r0, #5312; ARM78-NEXT: bx lr313;314; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:315; THUMB6: @ %bb.0:316; THUMB6-NEXT: lsrs r0, r1317; THUMB6-NEXT: ldr r1, .LCPI8_0318; THUMB6-NEXT: ands r0, r1319; THUMB6-NEXT: rsbs r1, r0, #0320; THUMB6-NEXT: adcs r0, r1321; THUMB6-NEXT: bx lr322; THUMB6-NEXT: .p2align 2323; THUMB6-NEXT: @ %bb.1:324; THUMB6-NEXT: .LCPI8_0:325; THUMB6-NEXT: .long 16776960 @ 0xffff00326;327; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:328; THUMB78: @ %bb.0:329; THUMB78-NEXT: lsrs r0, r1330; THUMB78-NEXT: movw r1, #65280331; THUMB78-NEXT: movt r1, #255332; THUMB78-NEXT: ands r0, r1333; THUMB78-NEXT: clz r0, r0334; THUMB78-NEXT: lsrs r0, r0, #5335; THUMB78-NEXT: bx lr336 %t0 = shl i32 16776960, %y337 %t1 = and i32 %t0, %x338 %res = icmp eq i32 %t1, 0339 ret i1 %res340}341 342; i64 scalar343 344define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {345; ARM6-LABEL: scalar_i64_signbit_eq:346; ARM6: @ %bb.0:347; ARM6-NEXT: lsr r0, r1, r2348; ARM6-NEXT: subs r1, r2, #32349; ARM6-NEXT: movpl r0, #0350; ARM6-NEXT: mvn r0, r0351; ARM6-NEXT: lsr r0, r0, #31352; ARM6-NEXT: bx lr353;354; ARM78-LABEL: scalar_i64_signbit_eq:355; ARM78: @ %bb.0:356; ARM78-NEXT: lsr r0, r1, r2357; ARM78-NEXT: subs r1, r2, #32358; ARM78-NEXT: movwpl r0, #0359; ARM78-NEXT: mvn r0, r0360; ARM78-NEXT: lsr r0, r0, #31361; ARM78-NEXT: bx lr362;363; THUMB6-LABEL: scalar_i64_signbit_eq:364; THUMB6: @ %bb.0:365; THUMB6-NEXT: push {r7, lr}366; THUMB6-NEXT: bl __lshrdi3367; THUMB6-NEXT: movs r0, #1368; THUMB6-NEXT: lsls r2, r0, #31369; THUMB6-NEXT: ands r2, r1370; THUMB6-NEXT: rsbs r0, r2, #0371; THUMB6-NEXT: adcs r0, r2372; THUMB6-NEXT: pop {r7, pc}373;374; THUMB78-LABEL: scalar_i64_signbit_eq:375; THUMB78: @ %bb.0:376; THUMB78-NEXT: lsr.w r0, r1, r2377; THUMB78-NEXT: subs.w r1, r2, #32378; THUMB78-NEXT: it pl379; THUMB78-NEXT: movpl r0, #0380; THUMB78-NEXT: mvns r0, r0381; THUMB78-NEXT: lsrs r0, r0, #31382; THUMB78-NEXT: bx lr383 %t0 = shl i64 9223372036854775808, %y384 %t1 = and i64 %t0, %x385 %res = icmp eq i64 %t1, 0386 ret i1 %res387}388 389define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {390; ARM-LABEL: scalar_i64_lowestbit_eq:391; ARM: @ %bb.0:392; ARM-NEXT: rsb r3, r2, #32393; ARM-NEXT: lsr r0, r0, r2394; ARM-NEXT: subs r2, r2, #32395; ARM-NEXT: orr r0, r0, r1, lsl r3396; ARM-NEXT: lsrpl r0, r1, r2397; ARM-NEXT: mov r1, #1398; ARM-NEXT: bic r0, r1, r0399; ARM-NEXT: bx lr400;401; THUMB6-LABEL: scalar_i64_lowestbit_eq:402; THUMB6: @ %bb.0:403; THUMB6-NEXT: push {r7, lr}404; THUMB6-NEXT: bl __lshrdi3405; THUMB6-NEXT: movs r1, #1406; THUMB6-NEXT: ands r0, r1407; THUMB6-NEXT: rsbs r1, r0, #0408; THUMB6-NEXT: adcs r0, r1409; THUMB6-NEXT: pop {r7, pc}410;411; THUMB78-LABEL: scalar_i64_lowestbit_eq:412; THUMB78: @ %bb.0:413; THUMB78-NEXT: rsb.w r3, r2, #32414; THUMB78-NEXT: lsrs r0, r2415; THUMB78-NEXT: subs r2, #32416; THUMB78-NEXT: lsl.w r3, r1, r3417; THUMB78-NEXT: orr.w r0, r0, r3418; THUMB78-NEXT: it pl419; THUMB78-NEXT: lsrpl.w r0, r1, r2420; THUMB78-NEXT: movs r1, #1421; THUMB78-NEXT: bic.w r0, r1, r0422; THUMB78-NEXT: bx lr423 %t0 = shl i64 1, %y424 %t1 = and i64 %t0, %x425 %res = icmp eq i64 %t1, 0426 ret i1 %res427}428 429define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {430; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:431; ARM6: @ %bb.0:432; ARM6-NEXT: rsb r3, r2, #32433; ARM6-NEXT: lsr r0, r0, r2434; ARM6-NEXT: orr r0, r0, r1, lsl r3435; ARM6-NEXT: subs r3, r2, #32436; ARM6-NEXT: lsrpl r0, r1, r3437; ARM6-NEXT: lsr r1, r1, r2438; ARM6-NEXT: movpl r1, #0439; ARM6-NEXT: pkhbt r0, r1, r0440; ARM6-NEXT: clz r0, r0441; ARM6-NEXT: lsr r0, r0, #5442; ARM6-NEXT: bx lr443;444; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:445; ARM78: @ %bb.0:446; ARM78-NEXT: rsb r3, r2, #32447; ARM78-NEXT: lsr r0, r0, r2448; ARM78-NEXT: orr r0, r0, r1, lsl r3449; ARM78-NEXT: subs r3, r2, #32450; ARM78-NEXT: lsrpl r0, r1, r3451; ARM78-NEXT: lsr r1, r1, r2452; ARM78-NEXT: movwpl r1, #0453; ARM78-NEXT: pkhbt r0, r1, r0454; ARM78-NEXT: clz r0, r0455; ARM78-NEXT: lsr r0, r0, #5456; ARM78-NEXT: bx lr457;458; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:459; THUMB6: @ %bb.0:460; THUMB6-NEXT: push {r7, lr}461; THUMB6-NEXT: bl __lshrdi3462; THUMB6-NEXT: ldr r2, .LCPI11_0463; THUMB6-NEXT: ands r2, r0464; THUMB6-NEXT: uxth r0, r1465; THUMB6-NEXT: adds r1, r2, r0466; THUMB6-NEXT: rsbs r0, r1, #0467; THUMB6-NEXT: adcs r0, r1468; THUMB6-NEXT: pop {r7, pc}469; THUMB6-NEXT: .p2align 2470; THUMB6-NEXT: @ %bb.1:471; THUMB6-NEXT: .LCPI11_0:472; THUMB6-NEXT: .long 4294901760 @ 0xffff0000473;474; THUMB78-LABEL: scalar_i64_bitsinmiddle_eq:475; THUMB78: @ %bb.0:476; THUMB78-NEXT: rsb.w r3, r2, #32477; THUMB78-NEXT: lsrs r0, r2478; THUMB78-NEXT: lsl.w r3, r1, r3479; THUMB78-NEXT: orrs r0, r3480; THUMB78-NEXT: subs.w r3, r2, #32481; THUMB78-NEXT: it pl482; THUMB78-NEXT: lsrpl.w r0, r1, r3483; THUMB78-NEXT: lsr.w r1, r1, r2484; THUMB78-NEXT: it pl485; THUMB78-NEXT: movpl r1, #0486; THUMB78-NEXT: pkhbt r0, r1, r0487; THUMB78-NEXT: clz r0, r0488; THUMB78-NEXT: lsrs r0, r0, #5489; THUMB78-NEXT: bx lr490 %t0 = shl i64 281474976645120, %y491 %t1 = and i64 %t0, %x492 %res = icmp eq i64 %t1, 0493 ret i1 %res494}495 496;------------------------------------------------------------------------------;497; A few trivial vector tests498;------------------------------------------------------------------------------;499 500define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {501; ARM6-LABEL: vec_4xi32_splat_eq:502; ARM6: @ %bb.0:503; ARM6-NEXT: push {r11, lr}504; ARM6-NEXT: ldr r12, [sp, #8]505; ARM6-NEXT: mov lr, #1506; ARM6-NEXT: bic r0, lr, r0, lsr r12507; ARM6-NEXT: ldr r12, [sp, #12]508; ARM6-NEXT: bic r1, lr, r1, lsr r12509; ARM6-NEXT: ldr r12, [sp, #16]510; ARM6-NEXT: bic r2, lr, r2, lsr r12511; ARM6-NEXT: ldr r12, [sp, #20]512; ARM6-NEXT: bic r3, lr, r3, lsr r12513; ARM6-NEXT: pop {r11, pc}514;515; ARM78-LABEL: vec_4xi32_splat_eq:516; ARM78: @ %bb.0:517; ARM78-NEXT: mov r12, sp518; ARM78-NEXT: vld1.64 {d16, d17}, [r12]519; ARM78-NEXT: vmov d19, r2, r3520; ARM78-NEXT: vneg.s32 q8, q8521; ARM78-NEXT: vmov d18, r0, r1522; ARM78-NEXT: vmov.i32 q10, #0x1523; ARM78-NEXT: vshl.u32 q8, q9, q8524; ARM78-NEXT: vtst.32 q8, q8, q10525; ARM78-NEXT: vmvn q8, q8526; ARM78-NEXT: vmovn.i32 d16, q8527; ARM78-NEXT: vmov r0, r1, d16528; ARM78-NEXT: bx lr529;530; THUMB6-LABEL: vec_4xi32_splat_eq:531; THUMB6: @ %bb.0:532; THUMB6-NEXT: push {r4, r5, r7, lr}533; THUMB6-NEXT: ldr r4, [sp, #16]534; THUMB6-NEXT: lsrs r0, r4535; THUMB6-NEXT: movs r4, #1536; THUMB6-NEXT: ands r0, r4537; THUMB6-NEXT: rsbs r5, r0, #0538; THUMB6-NEXT: adcs r0, r5539; THUMB6-NEXT: ldr r5, [sp, #20]540; THUMB6-NEXT: lsrs r1, r5541; THUMB6-NEXT: ands r1, r4542; THUMB6-NEXT: rsbs r5, r1, #0543; THUMB6-NEXT: adcs r1, r5544; THUMB6-NEXT: ldr r5, [sp, #24]545; THUMB6-NEXT: lsrs r2, r5546; THUMB6-NEXT: ands r2, r4547; THUMB6-NEXT: rsbs r5, r2, #0548; THUMB6-NEXT: adcs r2, r5549; THUMB6-NEXT: ldr r5, [sp, #28]550; THUMB6-NEXT: lsrs r3, r5551; THUMB6-NEXT: ands r3, r4552; THUMB6-NEXT: rsbs r4, r3, #0553; THUMB6-NEXT: adcs r3, r4554; THUMB6-NEXT: pop {r4, r5, r7, pc}555;556; THUMB78-LABEL: vec_4xi32_splat_eq:557; THUMB78: @ %bb.0:558; THUMB78-NEXT: mov r12, sp559; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]560; THUMB78-NEXT: vmov d19, r2, r3561; THUMB78-NEXT: vneg.s32 q8, q8562; THUMB78-NEXT: vmov d18, r0, r1563; THUMB78-NEXT: vmov.i32 q10, #0x1564; THUMB78-NEXT: vshl.u32 q8, q9, q8565; THUMB78-NEXT: vtst.32 q8, q8, q10566; THUMB78-NEXT: vmvn q8, q8567; THUMB78-NEXT: vmovn.i32 d16, q8568; THUMB78-NEXT: vmov r0, r1, d16569; THUMB78-NEXT: bx lr570 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y571 %t1 = and <4 x i32> %t0, %x572 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>573 ret <4 x i1> %res574}575 576define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {577; ARM6-LABEL: vec_4xi32_nonsplat_eq:578; ARM6: @ %bb.0:579; ARM6-NEXT: ldr r12, [sp, #4]580; ARM6-NEXT: mov r0, #1581; ARM6-NEXT: bic r1, r0, r1, lsr r12582; ARM6-NEXT: ldr r12, [sp, #8]583; ARM6-NEXT: mov r0, #65280584; ARM6-NEXT: orr r0, r0, #16711680585; ARM6-NEXT: and r0, r0, r2, lsr r12586; ARM6-NEXT: clz r0, r0587; ARM6-NEXT: lsr r2, r0, #5588; ARM6-NEXT: ldr r0, [sp, #12]589; ARM6-NEXT: mvn r0, r3, lsr r0590; ARM6-NEXT: lsr r3, r0, #31591; ARM6-NEXT: mov r0, #1592; ARM6-NEXT: bx lr593;594; ARM78-LABEL: vec_4xi32_nonsplat_eq:595; ARM78: @ %bb.0:596; ARM78-NEXT: mov r12, sp597; ARM78-NEXT: vld1.64 {d16, d17}, [r12]598; ARM78-NEXT: adr r12, .LCPI13_0599; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128]600; ARM78-NEXT: vshl.u32 q8, q9, q8601; ARM78-NEXT: vmov d19, r2, r3602; ARM78-NEXT: vmov d18, r0, r1603; ARM78-NEXT: vtst.32 q8, q8, q9604; ARM78-NEXT: vmvn q8, q8605; ARM78-NEXT: vmovn.i32 d16, q8606; ARM78-NEXT: vmov r0, r1, d16607; ARM78-NEXT: bx lr608; ARM78-NEXT: .p2align 4609; ARM78-NEXT: @ %bb.1:610; ARM78-NEXT: .LCPI13_0:611; ARM78-NEXT: .long 0 @ 0x0612; ARM78-NEXT: .long 1 @ 0x1613; ARM78-NEXT: .long 16776960 @ 0xffff00614; ARM78-NEXT: .long 2147483648 @ 0x80000000615;616; THUMB6-LABEL: vec_4xi32_nonsplat_eq:617; THUMB6: @ %bb.0:618; THUMB6-NEXT: push {r4, lr}619; THUMB6-NEXT: ldr r0, [sp, #12]620; THUMB6-NEXT: lsrs r1, r0621; THUMB6-NEXT: movs r0, #1622; THUMB6-NEXT: ands r1, r0623; THUMB6-NEXT: rsbs r4, r1, #0624; THUMB6-NEXT: adcs r1, r4625; THUMB6-NEXT: ldr r4, [sp, #16]626; THUMB6-NEXT: lsrs r2, r4627; THUMB6-NEXT: ldr r4, .LCPI13_0628; THUMB6-NEXT: ands r2, r4629; THUMB6-NEXT: rsbs r4, r2, #0630; THUMB6-NEXT: adcs r2, r4631; THUMB6-NEXT: ldr r4, [sp, #20]632; THUMB6-NEXT: lsrs r3, r4633; THUMB6-NEXT: lsls r4, r0, #31634; THUMB6-NEXT: ands r3, r4635; THUMB6-NEXT: rsbs r4, r3, #0636; THUMB6-NEXT: adcs r3, r4637; THUMB6-NEXT: pop {r4, pc}638; THUMB6-NEXT: .p2align 2639; THUMB6-NEXT: @ %bb.1:640; THUMB6-NEXT: .LCPI13_0:641; THUMB6-NEXT: .long 16776960 @ 0xffff00642;643; THUMB78-LABEL: vec_4xi32_nonsplat_eq:644; THUMB78: @ %bb.0:645; THUMB78-NEXT: mov r12, sp646; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]647; THUMB78-NEXT: adr.w r12, .LCPI13_0648; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128]649; THUMB78-NEXT: vshl.u32 q8, q9, q8650; THUMB78-NEXT: vmov d19, r2, r3651; THUMB78-NEXT: vmov d18, r0, r1652; THUMB78-NEXT: vtst.32 q8, q8, q9653; THUMB78-NEXT: vmvn q8, q8654; THUMB78-NEXT: vmovn.i32 d16, q8655; THUMB78-NEXT: vmov r0, r1, d16656; THUMB78-NEXT: bx lr657; THUMB78-NEXT: .p2align 4658; THUMB78-NEXT: @ %bb.1:659; THUMB78-NEXT: .LCPI13_0:660; THUMB78-NEXT: .long 0 @ 0x0661; THUMB78-NEXT: .long 1 @ 0x1662; THUMB78-NEXT: .long 16776960 @ 0xffff00663; THUMB78-NEXT: .long 2147483648 @ 0x80000000664 %t0 = shl <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y665 %t1 = and <4 x i32> %t0, %x666 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>667 ret <4 x i1> %res668}669 670define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {671; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:672; ARM6: @ %bb.0:673; ARM6-NEXT: push {r11, lr}674; ARM6-NEXT: ldr r2, [sp, #12]675; ARM6-NEXT: mov lr, #1676; ARM6-NEXT: ldr r12, [sp, #8]677; ARM6-NEXT: bic r1, lr, r1, lsr r2678; ARM6-NEXT: ldr r2, [sp, #20]679; ARM6-NEXT: bic r0, lr, r0, lsr r12680; ARM6-NEXT: bic r3, lr, r3, lsr r2681; ARM6-NEXT: mov r2, #1682; ARM6-NEXT: pop {r11, pc}683;684; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:685; ARM78: @ %bb.0:686; ARM78-NEXT: mov r12, sp687; ARM78-NEXT: vld1.64 {d16, d17}, [r12]688; ARM78-NEXT: vmov d19, r2, r3689; ARM78-NEXT: vneg.s32 q8, q8690; ARM78-NEXT: vmov d18, r0, r1691; ARM78-NEXT: vmov.i32 q10, #0x1692; ARM78-NEXT: vshl.u32 q8, q9, q8693; ARM78-NEXT: vtst.32 q8, q8, q10694; ARM78-NEXT: vmvn q8, q8695; ARM78-NEXT: vmovn.i32 d16, q8696; ARM78-NEXT: vmov r0, r1, d16697; ARM78-NEXT: bx lr698;699; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:700; THUMB6: @ %bb.0:701; THUMB6-NEXT: push {r4, lr}702; THUMB6-NEXT: ldr r2, [sp, #8]703; THUMB6-NEXT: lsrs r0, r2704; THUMB6-NEXT: movs r2, #1705; THUMB6-NEXT: ands r0, r2706; THUMB6-NEXT: rsbs r4, r0, #0707; THUMB6-NEXT: adcs r0, r4708; THUMB6-NEXT: ldr r4, [sp, #12]709; THUMB6-NEXT: lsrs r1, r4710; THUMB6-NEXT: ands r1, r2711; THUMB6-NEXT: rsbs r4, r1, #0712; THUMB6-NEXT: adcs r1, r4713; THUMB6-NEXT: ldr r4, [sp, #20]714; THUMB6-NEXT: lsrs r3, r4715; THUMB6-NEXT: ands r3, r2716; THUMB6-NEXT: rsbs r4, r3, #0717; THUMB6-NEXT: adcs r3, r4718; THUMB6-NEXT: pop {r4, pc}719;720; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:721; THUMB78: @ %bb.0:722; THUMB78-NEXT: mov r12, sp723; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]724; THUMB78-NEXT: vmov d19, r2, r3725; THUMB78-NEXT: vneg.s32 q8, q8726; THUMB78-NEXT: vmov d18, r0, r1727; THUMB78-NEXT: vmov.i32 q10, #0x1728; THUMB78-NEXT: vshl.u32 q8, q9, q8729; THUMB78-NEXT: vtst.32 q8, q8, q10730; THUMB78-NEXT: vmvn q8, q8731; THUMB78-NEXT: vmovn.i32 d16, q8732; THUMB78-NEXT: vmov r0, r1, d16733; THUMB78-NEXT: bx lr734 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y735 %t1 = and <4 x i32> %t0, %x736 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>737 ret <4 x i1> %res738}739define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {740; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:741; ARM6: @ %bb.0:742; ARM6-NEXT: push {r11, lr}743; ARM6-NEXT: ldr r2, [sp, #12]744; ARM6-NEXT: mov lr, #1745; ARM6-NEXT: ldr r12, [sp, #8]746; ARM6-NEXT: bic r1, lr, r1, lsr r2747; ARM6-NEXT: ldr r2, [sp, #20]748; ARM6-NEXT: bic r0, lr, r0, lsr r12749; ARM6-NEXT: bic r3, lr, r3, lsr r2750; ARM6-NEXT: pop {r11, pc}751;752; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:753; ARM78: @ %bb.0:754; ARM78-NEXT: vmov.i32 q8, #0x1755; ARM78-NEXT: mov r12, sp756; ARM78-NEXT: vld1.64 {d18, d19}, [r12]757; ARM78-NEXT: vshl.u32 q8, q8, q9758; ARM78-NEXT: vmov d19, r2, r3759; ARM78-NEXT: vmov d18, r0, r1760; ARM78-NEXT: vtst.32 q8, q8, q9761; ARM78-NEXT: vmvn q8, q8762; ARM78-NEXT: vmovn.i32 d16, q8763; ARM78-NEXT: vmov r0, r1, d16764; ARM78-NEXT: bx lr765;766; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:767; THUMB6: @ %bb.0:768; THUMB6-NEXT: push {r4, lr}769; THUMB6-NEXT: ldr r2, [sp, #8]770; THUMB6-NEXT: lsrs r0, r2771; THUMB6-NEXT: movs r2, #1772; THUMB6-NEXT: ands r0, r2773; THUMB6-NEXT: rsbs r4, r0, #0774; THUMB6-NEXT: adcs r0, r4775; THUMB6-NEXT: ldr r4, [sp, #12]776; THUMB6-NEXT: lsrs r1, r4777; THUMB6-NEXT: ands r1, r2778; THUMB6-NEXT: rsbs r4, r1, #0779; THUMB6-NEXT: adcs r1, r4780; THUMB6-NEXT: ldr r4, [sp, #20]781; THUMB6-NEXT: lsrs r3, r4782; THUMB6-NEXT: ands r3, r2783; THUMB6-NEXT: rsbs r2, r3, #0784; THUMB6-NEXT: adcs r3, r2785; THUMB6-NEXT: pop {r4, pc}786;787; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:788; THUMB78: @ %bb.0:789; THUMB78-NEXT: vmov.i32 q8, #0x1790; THUMB78-NEXT: mov r12, sp791; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]792; THUMB78-NEXT: vshl.u32 q8, q8, q9793; THUMB78-NEXT: vmov d19, r2, r3794; THUMB78-NEXT: vmov d18, r0, r1795; THUMB78-NEXT: vtst.32 q8, q8, q9796; THUMB78-NEXT: vmvn q8, q8797; THUMB78-NEXT: vmovn.i32 d16, q8798; THUMB78-NEXT: vmov r0, r1, d16799; THUMB78-NEXT: bx lr800 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y801 %t1 = and <4 x i32> %t0, %x802 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>803 ret <4 x i1> %res804}805define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {806; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:807; ARM6: @ %bb.0:808; ARM6-NEXT: push {r11, lr}809; ARM6-NEXT: ldr r2, [sp, #12]810; ARM6-NEXT: mov lr, #1811; ARM6-NEXT: ldr r12, [sp, #8]812; ARM6-NEXT: bic r1, lr, r1, lsr r2813; ARM6-NEXT: ldr r2, [sp, #20]814; ARM6-NEXT: bic r0, lr, r0, lsr r12815; ARM6-NEXT: bic r3, lr, r3, lsr r2816; ARM6-NEXT: pop {r11, pc}817;818; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:819; ARM78: @ %bb.0:820; ARM78-NEXT: vmov.i32 q8, #0x1821; ARM78-NEXT: mov r12, sp822; ARM78-NEXT: vld1.64 {d18, d19}, [r12]823; ARM78-NEXT: vshl.u32 q8, q8, q9824; ARM78-NEXT: vmov d19, r2, r3825; ARM78-NEXT: vmov d18, r0, r1826; ARM78-NEXT: vtst.32 q8, q8, q9827; ARM78-NEXT: vmvn q8, q8828; ARM78-NEXT: vmovn.i32 d16, q8829; ARM78-NEXT: vmov r0, r1, d16830; ARM78-NEXT: bx lr831;832; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:833; THUMB6: @ %bb.0:834; THUMB6-NEXT: push {r4, lr}835; THUMB6-NEXT: ldr r2, [sp, #8]836; THUMB6-NEXT: lsrs r0, r2837; THUMB6-NEXT: movs r2, #1838; THUMB6-NEXT: ands r0, r2839; THUMB6-NEXT: rsbs r4, r0, #0840; THUMB6-NEXT: adcs r0, r4841; THUMB6-NEXT: ldr r4, [sp, #12]842; THUMB6-NEXT: lsrs r1, r4843; THUMB6-NEXT: ands r1, r2844; THUMB6-NEXT: rsbs r4, r1, #0845; THUMB6-NEXT: adcs r1, r4846; THUMB6-NEXT: ldr r4, [sp, #20]847; THUMB6-NEXT: lsrs r3, r4848; THUMB6-NEXT: ands r3, r2849; THUMB6-NEXT: rsbs r2, r3, #0850; THUMB6-NEXT: adcs r3, r2851; THUMB6-NEXT: pop {r4, pc}852;853; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:854; THUMB78: @ %bb.0:855; THUMB78-NEXT: vmov.i32 q8, #0x1856; THUMB78-NEXT: mov r12, sp857; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]858; THUMB78-NEXT: vshl.u32 q8, q8, q9859; THUMB78-NEXT: vmov d19, r2, r3860; THUMB78-NEXT: vmov d18, r0, r1861; THUMB78-NEXT: vtst.32 q8, q8, q9862; THUMB78-NEXT: vmvn q8, q8863; THUMB78-NEXT: vmovn.i32 d16, q8864; THUMB78-NEXT: vmov r0, r1, d16865; THUMB78-NEXT: bx lr866 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y867 %t1 = and <4 x i32> %t0, %x868 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>869 ret <4 x i1> %res870}871 872;------------------------------------------------------------------------------;873; A special tests874;------------------------------------------------------------------------------;875 876define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {877; ARM-LABEL: scalar_i8_signbit_ne:878; ARM: @ %bb.0:879; ARM-NEXT: uxtb r1, r1880; ARM-NEXT: uxtb r0, r0881; ARM-NEXT: lsr r0, r0, r1882; ARM-NEXT: lsr r0, r0, #7883; ARM-NEXT: bx lr884;885; THUMB-LABEL: scalar_i8_signbit_ne:886; THUMB: @ %bb.0:887; THUMB-NEXT: uxtb r1, r1888; THUMB-NEXT: uxtb r0, r0889; THUMB-NEXT: lsrs r0, r1890; THUMB-NEXT: lsrs r0, r0, #7891; THUMB-NEXT: bx lr892 %t0 = shl i8 128, %y893 %t1 = and i8 %t0, %x894 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate895 ret i1 %res896}897 898;------------------------------------------------------------------------------;899; What if X is a constant too?900;------------------------------------------------------------------------------;901 902define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {903; ARM6-LABEL: scalar_i32_x_is_const_eq:904; ARM6: @ %bb.0:905; ARM6-NEXT: ldr r1, .LCPI18_0906; ARM6-NEXT: mov r2, #1907; ARM6-NEXT: bic r0, r2, r1, lsl r0908; ARM6-NEXT: bx lr909; ARM6-NEXT: .p2align 2910; ARM6-NEXT: @ %bb.1:911; ARM6-NEXT: .LCPI18_0:912; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55913;914; ARM78-LABEL: scalar_i32_x_is_const_eq:915; ARM78: @ %bb.0:916; ARM78-NEXT: movw r1, #43605917; ARM78-NEXT: mov r2, #1918; ARM78-NEXT: movt r1, #43605919; ARM78-NEXT: bic r0, r2, r1, lsl r0920; ARM78-NEXT: bx lr921;922; THUMB6-LABEL: scalar_i32_x_is_const_eq:923; THUMB6: @ %bb.0:924; THUMB6-NEXT: ldr r1, .LCPI18_0925; THUMB6-NEXT: lsls r1, r0926; THUMB6-NEXT: movs r2, #1927; THUMB6-NEXT: ands r2, r1928; THUMB6-NEXT: rsbs r0, r2, #0929; THUMB6-NEXT: adcs r0, r2930; THUMB6-NEXT: bx lr931; THUMB6-NEXT: .p2align 2932; THUMB6-NEXT: @ %bb.1:933; THUMB6-NEXT: .LCPI18_0:934; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55935;936; THUMB78-LABEL: scalar_i32_x_is_const_eq:937; THUMB78: @ %bb.0:938; THUMB78-NEXT: movw r1, #43605939; THUMB78-NEXT: movt r1, #43605940; THUMB78-NEXT: lsl.w r0, r1, r0941; THUMB78-NEXT: movs r1, #1942; THUMB78-NEXT: bic.w r0, r1, r0943; THUMB78-NEXT: bx lr944 %t0 = shl i32 2857740885, %y945 %t1 = and i32 %t0, 1946 %res = icmp eq i32 %t1, 0947 ret i1 %res948}949define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {950; ARM6-LABEL: scalar_i32_x_is_const2_eq:951; ARM6: @ %bb.0:952; ARM6-NEXT: ldr r2, .LCPI19_0953; ARM6-NEXT: mov r1, #1954; ARM6-NEXT: and r0, r2, r1, lsl r0955; ARM6-NEXT: clz r0, r0956; ARM6-NEXT: lsr r0, r0, #5957; ARM6-NEXT: bx lr958; ARM6-NEXT: .p2align 2959; ARM6-NEXT: @ %bb.1:960; ARM6-NEXT: .LCPI19_0:961; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55962;963; ARM78-LABEL: scalar_i32_x_is_const2_eq:964; ARM78: @ %bb.0:965; ARM78-NEXT: movw r1, #43605966; ARM78-NEXT: mov r2, #1967; ARM78-NEXT: movt r1, #43605968; ARM78-NEXT: and r0, r1, r2, lsl r0969; ARM78-NEXT: clz r0, r0970; ARM78-NEXT: lsr r0, r0, #5971; ARM78-NEXT: bx lr972;973; THUMB6-LABEL: scalar_i32_x_is_const2_eq:974; THUMB6: @ %bb.0:975; THUMB6-NEXT: movs r1, #1976; THUMB6-NEXT: lsls r1, r0977; THUMB6-NEXT: ldr r2, .LCPI19_0978; THUMB6-NEXT: ands r2, r1979; THUMB6-NEXT: rsbs r0, r2, #0980; THUMB6-NEXT: adcs r0, r2981; THUMB6-NEXT: bx lr982; THUMB6-NEXT: .p2align 2983; THUMB6-NEXT: @ %bb.1:984; THUMB6-NEXT: .LCPI19_0:985; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55986;987; THUMB78-LABEL: scalar_i32_x_is_const2_eq:988; THUMB78: @ %bb.0:989; THUMB78-NEXT: movs r1, #1990; THUMB78-NEXT: lsl.w r0, r1, r0991; THUMB78-NEXT: movw r1, #43605992; THUMB78-NEXT: movt r1, #43605993; THUMB78-NEXT: ands r0, r1994; THUMB78-NEXT: clz r0, r0995; THUMB78-NEXT: lsrs r0, r0, #5996; THUMB78-NEXT: bx lr997 %t0 = shl i32 1, %y998 %t1 = and i32 %t0, 2857740885999 %res = icmp eq i32 %t1, 01000 ret i1 %res1001}1002 1003;------------------------------------------------------------------------------;1004; A few negative tests1005;------------------------------------------------------------------------------;1006 1007define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {1008; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:1009; ARM6: @ %bb.0:1010; ARM6-NEXT: uxtb r1, r11011; ARM6-NEXT: mov r2, #241012; ARM6-NEXT: and r0, r0, r2, lsl r11013; ARM6-NEXT: sxtb r1, r01014; ARM6-NEXT: mov r0, #01015; ARM6-NEXT: cmp r1, #01016; ARM6-NEXT: movmi r0, #11017; ARM6-NEXT: bx lr1018;1019; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:1020; ARM78: @ %bb.0:1021; ARM78-NEXT: uxtb r1, r11022; ARM78-NEXT: mov r2, #241023; ARM78-NEXT: and r0, r0, r2, lsl r11024; ARM78-NEXT: sxtb r1, r01025; ARM78-NEXT: mov r0, #01026; ARM78-NEXT: cmp r1, #01027; ARM78-NEXT: movwmi r0, #11028; ARM78-NEXT: bx lr1029;1030; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:1031; THUMB6: @ %bb.0:1032; THUMB6-NEXT: uxtb r1, r11033; THUMB6-NEXT: movs r2, #241034; THUMB6-NEXT: lsls r2, r11035; THUMB6-NEXT: ands r2, r01036; THUMB6-NEXT: sxtb r0, r21037; THUMB6-NEXT: cmp r0, #01038; THUMB6-NEXT: bmi .LBB20_21039; THUMB6-NEXT: @ %bb.1:1040; THUMB6-NEXT: movs r0, #01041; THUMB6-NEXT: bx lr1042; THUMB6-NEXT: .LBB20_2:1043; THUMB6-NEXT: movs r0, #11044; THUMB6-NEXT: bx lr1045;1046; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:1047; THUMB78: @ %bb.0:1048; THUMB78-NEXT: uxtb r1, r11049; THUMB78-NEXT: movs r2, #241050; THUMB78-NEXT: lsl.w r1, r2, r11051; THUMB78-NEXT: ands r0, r11052; THUMB78-NEXT: sxtb r1, r01053; THUMB78-NEXT: movs r0, #01054; THUMB78-NEXT: cmp r1, #01055; THUMB78-NEXT: it mi1056; THUMB78-NEXT: movmi r0, #11057; THUMB78-NEXT: bx lr1058 %t0 = shl i8 24, %y1059 %t1 = and i8 %t0, %x1060 %res = icmp slt i8 %t1, 01061 ret i1 %res1062}1063 1064define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {1065; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:1066; ARM: @ %bb.0:1067; ARM-NEXT: mov r0, #01068; ARM-NEXT: bx lr1069;1070; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:1071; THUMB6: @ %bb.0:1072; THUMB6-NEXT: uxtb r1, r11073; THUMB6-NEXT: movs r2, #1271074; THUMB6-NEXT: mvns r2, r21075; THUMB6-NEXT: lsls r2, r11076; THUMB6-NEXT: ands r2, r01077; THUMB6-NEXT: uxtb r0, r21078; THUMB6-NEXT: subs r1, r0, #11079; THUMB6-NEXT: rsbs r0, r1, #01080; THUMB6-NEXT: adcs r0, r11081; THUMB6-NEXT: bx lr1082;1083; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:1084; THUMB78: @ %bb.0:1085; THUMB78-NEXT: movs r0, #01086; THUMB78-NEXT: bx lr1087 %t0 = shl i8 128, %y1088 %t1 = and i8 %t0, %x1089 %res = icmp eq i8 %t1, 1 ; should be comparing with 01090 ret i1 %res1091}1092