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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s3 4; Optimize expanded SRL/SHL used as an input of5; SETCC comparing it with zero by removing rotation.6;7; See https://bugs.llvm.org/show_bug.cgi?id=501978define i64 @opt_setcc_lt_power_of_2(i64 %a) nounwind {9; CHECK-LABEL: opt_setcc_lt_power_of_2:10; CHECK: @ %bb.0:11; CHECK-NEXT: .LBB0_1: @ %loop12; CHECK-NEXT: @ =>This Inner Loop Header: Depth=113; CHECK-NEXT: adds r0, r0, #114; CHECK-NEXT: adc r1, r1, #015; CHECK-NEXT: orrs r2, r1, r0, lsr #1616; CHECK-NEXT: bne .LBB0_117; CHECK-NEXT: @ %bb.2: @ %exit18; CHECK-NEXT: bx lr19 br label %loop20 21loop:22 %phi.a = phi i64 [ %a, %0 ], [ %inc, %loop ]23 %inc = add i64 %phi.a, 124 %cmp = icmp ult i64 %inc, 6553625 br i1 %cmp, label %exit, label %loop26 27exit:28 ret i64 %inc29}30 31define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind {32; CHECK-LABEL: opt_setcc_srl_eq_zero:33; CHECK: @ %bb.0:34; CHECK-NEXT: orr r0, r1, r0, lsr #1735; CHECK-NEXT: clz r0, r036; CHECK-NEXT: lsr r0, r0, #537; CHECK-NEXT: bx lr38 %srl = lshr i64 %a, 1739 %cmp = icmp eq i64 %srl, 040 ret i1 %cmp41}42 43define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind {44; CHECK-LABEL: opt_setcc_srl_ne_zero:45; CHECK: @ %bb.0:46; CHECK-NEXT: orrs r0, r1, r0, lsr #1747; CHECK-NEXT: movwne r0, #148; CHECK-NEXT: bx lr49 %srl = lshr i64 %a, 1750 %cmp = icmp ne i64 %srl, 051 ret i1 %cmp52}53 54define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind {55; CHECK-LABEL: opt_setcc_shl_eq_zero:56; CHECK: @ %bb.0:57; CHECK-NEXT: orr r0, r0, r1, lsl #1758; CHECK-NEXT: clz r0, r059; CHECK-NEXT: lsr r0, r0, #560; CHECK-NEXT: bx lr61 %shl = shl i64 %a, 1762 %cmp = icmp eq i64 %shl, 063 ret i1 %cmp64}65 66define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind {67; CHECK-LABEL: opt_setcc_shl_ne_zero:68; CHECK: @ %bb.0:69; CHECK-NEXT: orrs r0, r0, r1, lsl #1770; CHECK-NEXT: movwne r0, #171; CHECK-NEXT: bx lr72 %shl = shl i64 %a, 1773 %cmp = icmp ne i64 %shl, 074 ret i1 %cmp75}76 77; Negative test: optimization should not be applied if shift has multiple users.78define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i64 %a) nounwind {79; CHECK-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users:80; CHECK: @ %bb.0:81; CHECK-NEXT: push {r4, r5, r11, lr}82; CHECK-NEXT: mov r4, r083; CHECK-NEXT: lsl r0, r1, #1784; CHECK-NEXT: orr r5, r0, r4, lsr #1585; CHECK-NEXT: lsl r0, r4, #1786; CHECK-NEXT: mov r1, r587; CHECK-NEXT: bl use88; CHECK-NEXT: orr r0, r5, r4, lsl #1789; CHECK-NEXT: clz r0, r090; CHECK-NEXT: lsr r0, r0, #591; CHECK-NEXT: pop {r4, r5, r11, pc}92 %shl = shl i64 %a, 1793 %cmp = icmp eq i64 %shl, 094 call void @use(i64 %shl)95 ret i1 %cmp96}97 98; Check that optimization is applied to DAG having appropriate shape99; even if there were no actual shift's expansion.100define i1 @opt_setcc_expanded_shl_correct_shifts(i32 %a, i32 %b) nounwind {101; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts:102; CHECK: @ %bb.0:103; CHECK-NEXT: orr r0, r1, r0, lsl #17104; CHECK-NEXT: clz r0, r0105; CHECK-NEXT: lsr r0, r0, #5106; CHECK-NEXT: bx lr107 %shl.a = shl i32 %a, 17108 %srl.b = lshr i32 %b, 15109 %or.0 = or i32 %shl.a, %srl.b110 %shl.b = shl i32 %b, 17111 %or.1 = or i32 %or.0, %shl.b112 %cmp = icmp eq i32 %or.1, 0113 ret i1 %cmp114}115 116; Negative test: optimization should not be applied as117; constants used in shifts do not match.118define i1 @opt_setcc_expanded_shl_wrong_shifts(i32 %a, i32 %b) nounwind {119; CHECK-LABEL: opt_setcc_expanded_shl_wrong_shifts:120; CHECK: @ %bb.0:121; CHECK-NEXT: lsl r0, r0, #17122; CHECK-NEXT: orr r0, r0, r1, lsr #15123; CHECK-NEXT: orr r0, r0, r1, lsl #18124; CHECK-NEXT: clz r0, r0125; CHECK-NEXT: lsr r0, r0, #5126; CHECK-NEXT: bx lr127 %shl.a = shl i32 %a, 17128 %srl.b = lshr i32 %b, 15129 %or.0 = or i32 %shl.a, %srl.b130 %shl.b = shl i32 %b, 18131 %or.1 = or i32 %or.0, %shl.b132 %cmp = icmp eq i32 %or.1, 0133 ret i1 %cmp134}135 136define i1 @opt_setcc_shl_ne_zero_i128(i128 %a) nounwind {137; CHECK-LABEL: opt_setcc_shl_ne_zero_i128:138; CHECK: @ %bb.0:139; CHECK-NEXT: orr r0, r2, r0140; CHECK-NEXT: orr r0, r1, r0141; CHECK-NEXT: orr r1, r0, r3142; CHECK-NEXT: lsl r1, r1, #17143; CHECK-NEXT: orrs r0, r1, r0, lsr #15144; CHECK-NEXT: movwne r0, #1145; CHECK-NEXT: bx lr146 %shl = shl i128 %a, 17147 %cmp = icmp ne i128 %shl, 0148 ret i1 %cmp149}150 151declare void @use(i64 %a)152