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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s3; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-CMP4; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX5 6define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {7; CHECK-LABEL: t1:8; CHECK: @ %bb.0:9; CHECK-NEXT: cmp r2, #110; CHECK-NEXT: cmpne r2, #711; CHECK-NEXT: addne r0, r1, r012; CHECK-NEXT: addeq r0, r0, r113; CHECK-NEXT: addeq r0, r0, #114; CHECK-NEXT: bx lr15;16; CHECK-V4-CMP-LABEL: t1:17; CHECK-V4-CMP: @ %bb.0:18; CHECK-V4-CMP-NEXT: cmp r2, #719; CHECK-V4-CMP-NEXT: cmpne r2, #120; CHECK-V4-CMP-NEXT: addne r0, r1, r021; CHECK-V4-CMP-NEXT: addeq r0, r0, r122; CHECK-V4-CMP-NEXT: addeq r0, r0, #123; CHECK-V4-CMP-NEXT: bx lr24;25; CHECK-V4-BX-LABEL: t1:26; CHECK-V4-BX: @ %bb.0:27; CHECK-V4-BX-NEXT: cmp r2, #728; CHECK-V4-BX-NEXT: cmpne r2, #129; CHECK-V4-BX-NEXT: addne r0, r1, r030; CHECK-V4-BX-NEXT: addeq r0, r0, r131; CHECK-V4-BX-NEXT: addeq r0, r0, #132; CHECK-V4-BX-NEXT: bx lr33 switch i32 %c, label %cond_next [34 i32 1, label %cond_true35 i32 7, label %cond_true36 ]37 38cond_true:39 %tmp12 = add i32 %a, 140 %tmp1518 = add i32 %tmp12, %b41 ret i32 %tmp151842 43cond_next:44 %tmp15 = add i32 %b, %a45 ret i32 %tmp1546}47