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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=arm-eabi | FileCheck %s -check-prefix=LE3; RUN: llc < %s -mtriple=armeb-eabi | FileCheck %s -check-prefix=BE4 5define void @i24_or(ptr %a) {6; LE-LABEL: i24_or:7; LE: @ %bb.0:8; LE-NEXT: ldrh r1, [r0]9; LE-NEXT: orr r1, r1, #38410; LE-NEXT: strh r1, [r0]11; LE-NEXT: mov pc, lr12;13; BE-LABEL: i24_or:14; BE: @ %bb.0:15; BE-NEXT: ldrh r1, [r0]16; BE-NEXT: ldrb r2, [r0, #2]17; BE-NEXT: orr r1, r2, r1, lsl #818; BE-NEXT: orr r1, r1, #38419; BE-NEXT: strb r1, [r0, #2]20; BE-NEXT: lsr r1, r1, #821; BE-NEXT: strh r1, [r0]22; BE-NEXT: mov pc, lr23 %aa = load i24, ptr %a, align 124 %b = or i24 %aa, 38425 store i24 %b, ptr %a, align 126 ret void27}28 29define void @i24_and_or(ptr %a) {30; LE-LABEL: i24_and_or:31; LE: @ %bb.0:32; LE-NEXT: ldrh r1, [r0]33; LE-NEXT: orr r1, r1, #38434; LE-NEXT: bic r1, r1, #12735; LE-NEXT: strh r1, [r0]36; LE-NEXT: mov pc, lr37;38; BE-LABEL: i24_and_or:39; BE: @ %bb.0:40; BE-NEXT: mov r1, #12841; BE-NEXT: strb r1, [r0, #2]42; BE-NEXT: ldrh r1, [r0]43; BE-NEXT: orr r1, r1, #144; BE-NEXT: strh r1, [r0]45; BE-NEXT: mov pc, lr46 %b = load i24, ptr %a, align 147 %c = and i24 %b, -12848 %d = or i24 %c, 38449 store i24 %d, ptr %a, align 150 ret void51}52 53define void @i24_insert_bit(ptr %a, i1 zeroext %bit) {54; LE-LABEL: i24_insert_bit:55; LE: @ %bb.0:56; LE-NEXT: mov r3, #25557; LE-NEXT: ldrh r2, [r0]58; LE-NEXT: orr r3, r3, #5708859; LE-NEXT: and r2, r2, r360; LE-NEXT: orr r1, r2, r1, lsl #1361; LE-NEXT: strh r1, [r0]62; LE-NEXT: mov pc, lr63;64; BE-LABEL: i24_insert_bit:65; BE: @ %bb.0:66; BE-NEXT: ldrh r2, [r0]67; BE-NEXT: mov r3, #5708868; BE-NEXT: orr r3, r3, #1671168069; BE-NEXT: and r2, r3, r2, lsl #870; BE-NEXT: orr r1, r2, r1, lsl #1371; BE-NEXT: lsr r1, r1, #872; BE-NEXT: strh r1, [r0]73; BE-NEXT: mov pc, lr74 %extbit = zext i1 %bit to i2475 %b = load i24, ptr %a, align 176 %extbit.shl = shl nuw nsw i24 %extbit, 1377 %c = and i24 %b, -819378 %d = or i24 %c, %extbit.shl79 store i24 %d, ptr %a, align 180 ret void81}82 83define void @i56_or(ptr %a) {84; LE-LABEL: i56_or:85; LE: @ %bb.0:86; LE-NEXT: ldr r1, [r0]87; LE-NEXT: orr r1, r1, #38488; LE-NEXT: str r1, [r0]89; LE-NEXT: mov pc, lr90;91; BE-LABEL: i56_or:92; BE: @ %bb.0:93; BE-NEXT: mov r1, r094; BE-NEXT: ldr r0, [r0]95; BE-NEXT: ldrh r2, [r1, #4]!96; BE-NEXT: ldrb r3, [r1, #2]97; BE-NEXT: orr r2, r3, r2, lsl #898; BE-NEXT: orr r0, r2, r0, lsl #2499; BE-NEXT: orr r0, r0, #384100; BE-NEXT: strb r0, [r1, #2]101; BE-NEXT: lsr r0, r0, #8102; BE-NEXT: strh r0, [r1]103; BE-NEXT: mov pc, lr104 %aa = load i56, ptr %a105 %b = or i56 %aa, 384106 store i56 %b, ptr %a107 ret void108}109 110define void @i56_and_or(ptr %a) {111; LE-LABEL: i56_and_or:112; LE: @ %bb.0:113; LE-NEXT: ldr r1, [r0]114; LE-NEXT: orr r1, r1, #384115; LE-NEXT: bic r1, r1, #127116; LE-NEXT: str r1, [r0]117; LE-NEXT: mov pc, lr118;119; BE-LABEL: i56_and_or:120; BE: @ %bb.0:121; BE-NEXT: ldrh r1, [r0, #4]!122; BE-NEXT: mov r2, #128123; BE-NEXT: orr r1, r1, #1124; BE-NEXT: strb r2, [r0, #2]125; BE-NEXT: strh r1, [r0]126; BE-NEXT: mov pc, lr127 128 %b = load i56, ptr %a, align 1129 %c = and i56 %b, -128130 %d = or i56 %c, 384131 store i56 %d, ptr %a, align 1132 ret void133}134 135define void @i56_insert_bit(ptr %a, i1 zeroext %bit) {136; LE-LABEL: i56_insert_bit:137; LE: @ %bb.0:138; LE-NEXT: ldr r2, [r0]139; LE-NEXT: bic r2, r2, #8192140; LE-NEXT: orr r1, r2, r1, lsl #13141; LE-NEXT: str r1, [r0]142; LE-NEXT: mov pc, lr143;144; BE-LABEL: i56_insert_bit:145; BE: @ %bb.0:146; BE-NEXT: ldrh r2, [r0, #4]!147; BE-NEXT: mov r3, #57088148; BE-NEXT: orr r3, r3, #16711680149; BE-NEXT: and r2, r3, r2, lsl #8150; BE-NEXT: orr r1, r2, r1, lsl #13151; BE-NEXT: lsr r1, r1, #8152; BE-NEXT: strh r1, [r0]153; BE-NEXT: mov pc, lr154 %extbit = zext i1 %bit to i56155 %b = load i56, ptr %a, align 1156 %extbit.shl = shl nuw nsw i56 %extbit, 13157 %c = and i56 %b, -8193158 %d = or i56 %c, %extbit.shl159 store i56 %d, ptr %a, align 1160 ret void161}162 163