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1; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi -no-integrated-as | FileCheck %s2; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-as < %s | FileCheck %s3; check if regs are passing correctly4define void @i64_write(ptr %p, i64 %val) nounwind {5; CHECK-LABEL: i64_write:6; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]7; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}8 %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(ptr elementtype(i64) %p, ptr %p, i64 %val) nounwind9 ret void10}11 12; check if register allocation can reuse the registers13define void @multi_writes(ptr %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {14entry:15; CHECK-LABEL: multi_writes:16; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]17; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]18; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]19; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]20; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]21; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]22 23; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]24; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]25; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]26; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]27; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]28; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]29 30; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]31; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]32; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]33; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]34; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]35; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]36 37 tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(ptr %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind38 %incdec.ptr = getelementptr inbounds i64, ptr %p, i32 139 tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(ptr %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind40 tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(ptr %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind41 ret void42}43 44 45; check if callee-saved registers used by inline asm are saved/restored46define void @foo(ptr %p, i64 %i) nounwind {47; CHECK-LABEL:foo:48; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}49; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]50; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}51; CHECK: {{pop|pop.w}} {{{r[4-9]|r10|r11}}52 %1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(ptr elementtype(i64) %p, ptr %p, i64 %i) nounwind53 ret void54}55 56; return *p;57define i64 @ldrd_test(ptr %p) nounwind {58; CHECK-LABEL: ldrd_test:59 %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(ptr %p) nounwind60 ret i64 %161}62 63define i64 @QR_test(ptr %p) nounwind {64; CHECK-LABEL: QR_test:65; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}66 %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(ptr %p) nounwind67 ret i64 %168}69 70define i64 @defuse_test(i64 %p) nounwind {71; CHECK-LABEL: defuse_test:72; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #173 %1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind74 ret i64 %175}76 77; *p = (hi << 32) | lo;78define void @strd_test(ptr %p, i32 %lo, i32 %hi) nounwind {79; CHECK-LABEL: strd_test:80; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}81 %1 = zext i32 %hi to i6482 %2 = shl nuw i64 %1, 3283 %3 = sext i32 %lo to i6484 %4 = or i64 %2, %385 tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, ptr %p) nounwind86 ret void87}88 89; Make sure we don't untie operands by mistake.90define i64 @tied_64bit_test(i64 %in) nounwind {91; CHECK-LABEL: tied_64bit_test:92; CHECK: OUT([[OUTREG:r[0-9]+]]), IN([[OUTREG]])93 %addr = alloca i6494 call void asm "OUT($0), IN($1)", "=*rm,0"(ptr elementtype(i64) %addr, i64 %in)95 ret i64 %in96}97 98; If we explicitly name a tied operand, then the code should lookup the operand99; we were tied to for information about register class and so on.100define i64 @tied_64bit_lookback_test(i64 %in) nounwind {101; CHECK-LABEL: tied_64bit_lookback_test:102; CHECK: OUTLO([[LO:r[0-9]+]]) OUTHI([[HI:r[0-9]+]]) INLO([[LO]]) INHI([[HI]])103 %vars = call {i64, i32, i64} asm "OUTLO(${2:Q}) OUTHI(${2:R}) INLO(${3:Q}) INHI(${3:R})", "=r,=r,=r,2"(i64 %in)104 %res = extractvalue {i64, i32, i64} %vars, 2105 ret i64 %res106}107 108; Check access to low and high part with a specific register pair constraint109define i64 @low_high_specific_reg_pair(i64 %in) nounwind {110; CHECK-LABEL: low_high_specific_reg_pair111; CHECK: mov r3, r2112 %res = call i64 asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(i64 %in)113 ret i64 %res114}115