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1; RUN: llc -mtriple=armv8-eabi -mattr=+neon %s -o - | FileCheck %s2 3define i32 @test1(i32 %tmp54) {4 %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) ; <i32> [#uses=1]5 ret i32 %tmp566}7 8define void @test2() {9 tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )10 ret void11}12 13define float @t-constraint-int(i32 %i) {14 ; CHECK-LABEL: t-constraint-int15 ; CHECK: vcvt.f32.s32 {{s[0-9]+}}, {{s[0-9]+}}16 %ret = call float asm "vcvt.f32.s32 $0, $1\0A", "=t,t"(i32 %i)17 ret float %ret18}19 20define <2 x i32> @t-constraint-int-vector-64bit(<2 x float> %x) {21entry:22 ; CHECK-LABEL: t-constraint-int-vector-64bit23 ; CHECK: vcvt.s32.f32 {{d[0-9]+}}, {{d[0-9]+}}24 %0 = tail call <2 x i32> asm "vcvt.s32.f32 $0, $1", "=t,t"(<2 x float> %x)25 ret <2 x i32> %026}27 28define <4 x i32> @t-constraint-int-vector-128bit(<4 x float> %x) {29entry:30 ; CHECK-LABEL: t-constraint-int-vector-128bit31 ; CHECK: vcvt.s32.f32 {{q[0-7]}}, {{q[0-7]}}32 %0 = tail call <4 x i32> asm "vcvt.s32.f32 $0, $1", "=t,t"(<4 x float> %x)33 ret <4 x i32> %034}35 36define <2 x float> @t-constraint-float-vector-64bit(<2 x float> %a, <2 x float> %b) {37entry:38 ; CHECK-LABEL: t-constraint-float-vector-64bit39 ; CHECK: vadd.f32 d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}40 %0 = tail call <2 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<2 x float> %a, <2 x float> %b)41 ret <2 x float> %042}43 44define <4 x float> @t-constraint-float-vector-128bit(<4 x float> %a, <4 x float> %b) {45entry:46 ; CHECK-LABEL: t-constraint-float-vector-128bit47 ; CHECK: vadd.f32 q{{[0-7]}}, q{{[0-7]}}, q{{[0-7]}}48 %0 = tail call <4 x float> asm "vadd.f32 $0, $1, $2", "=t,t,t"(<4 x float> %a, <4 x float> %b)49 ret <4 x float> %050}51 52define i32 @even-GPR-constraint() {53entry:54 ; CHECK-LABEL: even-GPR-constraint55 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #156 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #257 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #358 ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #459 %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3"(i32 0, i32 0, i32 0, i32 0)60 %asmresult = extractvalue { i32, i32, i32, i32 } %0, 061 ret i32 %asmresult62}63 64define i32 @odd-GPR-constraint() {65entry:66 ; CHECK-LABEL: odd-GPR-constraint67 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #168 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #269 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #370 ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #471 %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3"(i32 0, i32 0, i32 0, i32 0)72 %asmresult = extractvalue { i32, i32, i32, i32 } %0, 073 ret i32 %asmresult74}75