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1; RUN: llc -mtriple=arm-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A %s2; RUN: llc -mtriple=thumb-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A-THUMB %s3; RUN: llc -mtriple=thumb-apple-none-macho -mcpu=cortex-m3 -o - %s | FileCheck --check-prefix=CHECK-M %s4 5declare arm_aapcscc void @bar()6 7@bigvar = global [16 x i32] zeroinitializer8 9define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" {10 ; Must save all registers except banked sp and lr (we save lr anyway because11 ; we actually need it at the end to execute the return ourselves).12 13 ; Also need special function return setting pc and CPSR simultaneously.14; CHECK-A-LABEL: irq_fn:15; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}16; CHECK-A: add r11, sp, #2017; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}18; CHECK-A: bfc sp, #0, #319; CHECK-A: bl bar20; CHECK-A: sub sp, r11, #2021; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}22; CHECK-A: subs pc, lr, #423 24; CHECK-A-THUMB-LABEL: irq_fn:25; CHECK-A-THUMB: push.w {r0, r1, r2, r3, r4, r7, r12, lr}26; CHECK-A-THUMB: add r7, sp, #2027; CHECK-A-THUMB: mov r4, sp28; CHECK-A-THUMB: bfc r4, #0, #329; CHECK-A-THUMB: bl bar30; CHECK-A-THUMB: sub.w r4, r7, #2031; CHECK-A-THUMB: mov sp, r432; CHECK-A-THUMB: pop.w {r0, r1, r2, r3, r4, r7, r12, lr}33; CHECK-A-THUMB: subs pc, lr, #434 35 ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to36 ; appropriate sentinel so no special return needed).37; CHECK-M-LABEL: irq_fn:38; CHECK-M: push {r4, r6, r7, lr}39; CHECK-M: add r7, sp, #840; CHECK-M: mov r4, sp41; CHECK-M: bfc r4, #0, #342; CHECK-M: mov sp, r443; CHECK-M: bl _bar44; CHECK-M: sub.w r4, r7, #845; CHECK-M: mov sp, r446; CHECK-M: pop {r4, r6, r7, pc}47 48 call arm_aapcscc void @bar()49 ret void50}51 52; We don't push/pop r12, as it is banked for FIQ53define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" {54; CHECK-A-LABEL: fiq_fn:55; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr}56 ; 32 to get past r0, r1, ..., r757; CHECK-A: add r11, sp, #3258; CHECK-A: sub sp, sp, #{{[0-9]+}}59; CHECK-A: bfc sp, #0, #360; [...]61 ; 32 must match above62; CHECK-A: sub sp, r11, #3263; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr}64; CHECK-A: subs pc, lr, #465 66; CHECK-A-THUMB-LABEL: fiq_fn:67; CHECK-M-LABEL: fiq_fn:68 %val = load volatile [16 x i32], ptr @bigvar69 store volatile [16 x i32] %val, ptr @bigvar70 ret void71}72 73define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" {74; CHECK-A-LABEL: swi_fn:75; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}76; CHECK-A: add r11, sp, #4477; CHECK-A: sub sp, sp, #{{[0-9]+}}78; CHECK-A: bfc sp, #0, #379; [...]80; CHECK-A: sub sp, r11, #4481; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr}82; CHECK-A: subs pc, lr, #083 84 %val = load volatile [16 x i32], ptr @bigvar85 store volatile [16 x i32] %val, ptr @bigvar86 ret void87}88 89define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" {90; CHECK-A-LABEL: undef_fn:91; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}92; CHECK-A: add r11, sp, #2093; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}94; CHECK-A: bfc sp, #0, #395; [...]96; CHECK-A: sub sp, r11, #2097; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}98; CHECK-A: subs pc, lr, #099 100 call void @bar()101 ret void102}103 104define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" {105; CHECK-A-LABEL: abort_fn:106; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr}107; CHECK-A: add r11, sp, #20108; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}}109; CHECK-A: bfc sp, #0, #3110; [...]111; CHECK-A: sub sp, r11, #20112; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr}113; CHECK-A: subs pc, lr, #4114 115 call void @bar()116 ret void117}118 119@var = global double 0.0120 121; We don't save VFP regs, since it would be a massive overhead in the general122; case.123define arm_aapcscc void @floating_fn() alignstack(8) "interrupt"="IRQ" {124; CHECK-A-LABEL: floating_fn:125; CHECK-A-NOT: vpush126; CHECK-A-NOT: vstr127; CHECK-A-NOT: vstm128; CHECK-A: vadd.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}129 %lhs = load volatile double, ptr @var130 %rhs = load volatile double, ptr @var131 %sum = fadd double %lhs, %rhs132 store double %sum, ptr @var133 ret void134}135