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1; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s2 3define void @coproc(ptr %i) nounwind {4entry:5 ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #46 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind7 ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #48 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind9 ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #410 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind11 ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #412 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind13 ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c114 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind15 ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c116 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind17 ; CHECK: cdp p7, #3, c1, c1, c1, #518 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind19 ; CHECK: cdp2 p7, #3, c1, c1, c1, #520 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind21 ; CHECK: ldc p7, c3, [r{{[0-9]+}}]22 tail call void @llvm.arm.ldc(i32 7, i32 3, ptr %i) nounwind23 ; CHECK: ldcl p7, c3, [r{{[0-9]+}}]24 tail call void @llvm.arm.ldcl(i32 7, i32 3, ptr %i) nounwind25 ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}]26 tail call void @llvm.arm.ldc2(i32 7, i32 3, ptr %i) nounwind27 ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}]28 tail call void @llvm.arm.ldc2l(i32 7, i32 3, ptr %i) nounwind29 ; CHECK: stc p7, c3, [r{{[0-9]+}}]30 tail call void @llvm.arm.stc(i32 7, i32 3, ptr %i) nounwind31 ; CHECK: stcl p7, c3, [r{{[0-9]+}}]32 tail call void @llvm.arm.stcl(i32 7, i32 3, ptr %i) nounwind33 ; CHECK: stc2 p7, c3, [r{{[0-9]+}}]34 tail call void @llvm.arm.stc2(i32 7, i32 3, ptr %i) nounwind35 ; CHECK: stc2l p7, c3, [r{{[0-9]+}}]36 tail call void @llvm.arm.stc2l(i32 7, i32 3, ptr %i) nounwind37 ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c338 %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind39 ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c340 %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind41 ret void42}43 44declare void @llvm.arm.ldc(i32, i32, ptr) nounwind45 46declare void @llvm.arm.ldcl(i32, i32, ptr) nounwind47 48declare void @llvm.arm.ldc2(i32, i32, ptr) nounwind49 50declare void @llvm.arm.ldc2l(i32, i32, ptr) nounwind51 52declare void @llvm.arm.stc(i32, i32, ptr) nounwind53 54declare void @llvm.arm.stcl(i32, i32, ptr) nounwind55 56declare void @llvm.arm.stc2(i32, i32, ptr) nounwind57 58declare void @llvm.arm.stc2l(i32, i32, ptr) nounwind59 60declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind61 62declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind63 64declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind65 66declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind67 68declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind69 70declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind71 72declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind73 74declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind75 76declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind77 78declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind79