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1; RUN: llc < %s -mtriple=arm-linux -mcpu=generic -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ARM2; RUN: llc < %s -mtriple=thumbv6m-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV63; RUN: llc < %s -mtriple=thumbv7-eabi -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=THUMBV74 5define i32 @uadd_overflow(i32 %a, i32 %b) #0 {6 %sadd = tail call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)7 %1 = extractvalue { i32, i1 } %sadd, 18 %2 = zext i1 %1 to i329 ret i32 %210 11 ; CHECK-LABEL: uadd_overflow:12 13 ; ARM: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]14 ; ARM: mov r[[R2:[0-9]+]], #015 ; ARM: adc r[[R0]], r[[R2]], #016 17 ; THUMBV6: movs r[[R2:[0-9]+]], #018 ; THUMBV6: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]19 ; THUMBV6: adcs r[[R2]], r[[R2]]20 ; THUMBV6: mov r[[R0]], r[[R2]]21 22 ; THUMBV7: adds r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]23 ; THUMBV7: mov.w r[[R2:[0-9]+]], #024 ; THUMBV7: adc r[[R0]], r[[R2]], #025}26 27 28define i32 @sadd_overflow(i32 %a, i32 %b) #0 {29 %sadd = tail call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b)30 %1 = extractvalue { i32, i1 } %sadd, 131 %2 = zext i1 %1 to i3232 ret i32 %233 34 ; CHECK-LABEL: sadd_overflow:35 36 ; ARM: adds r[[R2:[0-9]+]], r[[R0:[0-9]+]], r[[R1:[0-9]+]]37 ; ARM: mov r[[R0]], #138 ; ARM: movvc r[[R0]], #039 ; ARM: mov pc, lr40 41 ; THUMBV6: adds r0, r0, r142 ; THUMBV6: bvc .LBB1_243 44 ; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]45 ; THUMBV7: mov.w r[[R0:[0-9]+]], #146 ; THUMBV7: it vc47 ; THUMBV7: movvc r[[R0]], #048}49 50define i32 @usub_overflow(i32 %a, i32 %b) #0 {51 %sadd = tail call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)52 %1 = extractvalue { i32, i1 } %sadd, 153 %2 = zext i1 %1 to i3254 ret i32 %255 56 ; CHECK-LABEL: usub_overflow:57 58 ; ARM: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]59 ; ARM: mov r[[R2:[0-9]+]], #060 ; ARM: adc r[[R0]], r[[R2]], #061 ; ARM: eor r[[R0]], r[[R0]], #162 63 ; THUMBV6: movs r[[R2:[0-9]+]], #064 ; THUMBV6: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]65 ; THUMBV6: adcs r[[R2]], r[[R2]]66 ; THUMBV6: movs r[[R0]], #167 ; THUMBV6: eors r[[R0]], r[[R2]]68 69 ; THUMBV7: subs r[[R0:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]70 ; THUMBV7: mov.w r[[R2:[0-9]+]], #071 ; THUMBV7: adc r[[R0]], r[[R2]], #072 ; THUMBV7: eor r[[R0]], r[[R0]], #173 74 ; We should know that the overflow is just 1 bit,75 ; no need to clear any other bit76 ; CHECK-NOT: and77}78 79define i32 @ssub_overflow(i32 %a, i32 %b) #0 {80 %sadd = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)81 %1 = extractvalue { i32, i1 } %sadd, 182 %2 = zext i1 %1 to i3283 ret i32 %284 85 ; CHECK-LABEL: ssub_overflow:86 87 ; ARM: mov r[[R2]], #188 ; ARM: cmp r[[R0]], r[[R1]]89 ; ARM: movvc r[[R2]], #090 91 ; THUMBV6: cmp r0, r192 ; THUMBV6: bvc .LBB3_293 94 ; THUMBV7: movs r[[R2:[0-9]+]], #195 ; THUMBV7: cmp r[[R0:[0-9]+]], r[[R1:[0-9]+]]96 ; THUMBV7: it vc97 ; THUMBV7: movvc r[[R2]], #098 ; THUMBV7: mov r[[R0]], r[[R2]]99}100 101declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1102declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) #2103declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #3104declare { i32, i1 } @llvm.ssub.with.overflow.i32(i32, i32) #4105