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1; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s2; RUN: llc < %s -mtriple=thumbv7-apple-darwin > %t3; RUN: FileCheck %s < %t4; RUN: FileCheck %s < %t --check-prefix=CHECK-T2ADDRMODE5 6%0 = type { i32, i32 }7 8; CHECK-LABEL: f0:9; CHECK: ldrexd10define i64 @f0(ptr %p) nounwind readonly {11entry:12 %ldrexd = tail call %0 @llvm.arm.ldrexd(ptr %p)13 %0 = extractvalue %0 %ldrexd, 114 %1 = extractvalue %0 %ldrexd, 015 %2 = zext i32 %0 to i6416 %3 = zext i32 %1 to i6417 %shl = shl nuw i64 %2, 3218 %4 = or i64 %shl, %319 ret i64 %420}21 22; CHECK-LABEL: f1:23; CHECK: strexd24define i32 @f1(ptr %ptr, i64 %val) nounwind {25entry:26 %tmp4 = trunc i64 %val to i3227 %tmp6 = lshr i64 %val, 3228 %tmp7 = trunc i64 %tmp6 to i3229 %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, ptr %ptr)30 ret i32 %strexd31}32 33declare %0 @llvm.arm.ldrexd(ptr) nounwind readonly34declare i32 @llvm.arm.strexd(i32, i32, ptr) nounwind35 36; CHECK-LABEL: test_load_i8:37; CHECK: ldrexb r0, [r0]38; CHECK-NOT: uxtb39; CHECK-NOT: and40define zeroext i8 @test_load_i8(ptr %addr) {41 %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %addr)42 %val8 = trunc i32 %val to i843 ret i8 %val844}45 46; CHECK-LABEL: test_load_i16:47; CHECK: ldrexh r0, [r0]48; CHECK-NOT: uxth49; CHECK-NOT: and50define zeroext i16 @test_load_i16(ptr %addr) {51 %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %addr)52 %val16 = trunc i32 %val to i1653 ret i16 %val1654}55 56; CHECK-LABEL: test_load_i32:57; CHECK: ldrex r0, [r0]58define i32 @test_load_i32(ptr %addr) {59 %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr)60 ret i32 %val61}62 63declare i32 @llvm.arm.ldrex.p0(ptr) nounwind readonly64 65; CHECK-LABEL: test_store_i8:66; CHECK-NOT: uxtb67; CHECK: strexb r0, r1, [r2]68define i32 @test_store_i8(i32, i8 %val, ptr %addr) {69 %extval = zext i8 %val to i3270 %res = call i32 @llvm.arm.strex.p0(i32 %extval, ptr elementtype(i8) %addr)71 ret i32 %res72}73 74; CHECK-LABEL: test_store_i16:75; CHECK-NOT: uxth76; CHECK: strexh r0, r1, [r2]77define i32 @test_store_i16(i32, i16 %val, ptr %addr) {78 %extval = zext i16 %val to i3279 %res = call i32 @llvm.arm.strex.p0(i32 %extval, ptr elementtype(i16) %addr)80 ret i32 %res81}82 83; CHECK-LABEL: test_store_i32:84; CHECK: strex r0, r1, [r2]85define i32 @test_store_i32(i32, i32 %val, ptr %addr) {86 %res = call i32 @llvm.arm.strex.p0(i32 %val, ptr elementtype(i32) %addr)87 ret i32 %res88}89 90declare i32 @llvm.arm.strex.p0(i32, ptr) nounwind91 92; CHECK-LABEL: test_clear:93; CHECK: clrex94define void @test_clear() {95 call void @llvm.arm.clrex()96 ret void97}98 99declare void @llvm.arm.clrex() nounwind100 101@base = global ptr null102 103define void @excl_addrmode() {104; CHECK-T2ADDRMODE-LABEL: excl_addrmode:105 %base1020 = load ptr, ptr @base106 %offset1020 = getelementptr i32, ptr %base1020, i32 255107 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %offset1020)108 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %offset1020)109; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [{{r[0-9]+}}, #1020]110; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [{{r[0-9]+}}, #1020]111 112 %base1024 = load ptr, ptr @base113 %offset1024 = getelementptr i32, ptr %base1024, i32 256114 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %offset1024)115 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %offset1024)116; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], {{r[0-9]+}}, #1024117; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]118; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]119 120 %base1 = load ptr, ptr @base121 %offset1_8 = getelementptr i8, ptr %base1, i32 1122 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %offset1_8)123 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %offset1_8)124; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #1125; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]126; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]127 128 %local = alloca i8, i32 1024129 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local)130 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local)131; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp132; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]133; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]134 135 ret void136}137 138define void @test_excl_addrmode_folded() {139; CHECK-LABEL: test_excl_addrmode_folded:140 %local = alloca i8, i32 4096141 142 %local.0 = getelementptr i8, ptr %local, i32 4143 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)144 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)145; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #4]146; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #4]147 148 %local.1 = getelementptr i8, ptr %local, i32 1020149 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.1)150 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.1)151; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #1020]152; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #1020]153 154 ret void155}156 157define void @test_excl_addrmode_range() {158; CHECK-LABEL: test_excl_addrmode_range:159 %local = alloca i8, i32 4096160 161 %local.0 = getelementptr i8, ptr %local, i32 1024162 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)163 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)164; CHECK-T2ADDRMODE: mov r[[TMP:[0-9]+]], sp165; CHECK-T2ADDRMODE: add.w r[[ADDR:[0-9]+]], r[[TMP]], #1024166; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]167; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]168 169 ret void170}171 172define void @test_excl_addrmode_align() {173; CHECK-LABEL: test_excl_addrmode_align:174 %local = alloca i8, i32 4096175 176 %local.0 = getelementptr i8, ptr %local, i32 2177 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)178 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)179; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp180; CHECK-T2ADDRMODE: adds r[[ADDR:[0-9]+]], #2181; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]182; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]183 184 ret void185}186 187define void @test_excl_addrmode_sign() {188; CHECK-LABEL: test_excl_addrmode_sign:189 %local = alloca i8, i32 4096190 191 %local.0 = getelementptr i8, ptr %local, i32 -4192 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)193 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)194; CHECK-T2ADDRMODE: mov r[[ADDR:[0-9]+]], sp195; CHECK-T2ADDRMODE: subs r[[ADDR:[0-9]+]], #4196; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [r[[ADDR]]]197; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]198 199 ret void200}201 202define void @test_excl_addrmode_combination() {203; CHECK-LABEL: test_excl_addrmode_combination:204 %local = alloca i8, i32 4096205 %unused = alloca i8, i32 64206 207 %local.0 = getelementptr i8, ptr %local, i32 4208 call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %local.0)209 call i32 @llvm.arm.strex.p0(i32 0, ptr elementtype(i32) %local.0)210; CHECK-T2ADDRMODE: ldrex {{r[0-9]+}}, [sp, #68]211; CHECK-T2ADDRMODE: strex {{r[0-9]+}}, {{r[0-9]+}}, [sp, #68]212 213 ret void214}215 216 217; LLVM should know, even across basic blocks, that ldrex is setting the high218; bits of its i32 to 0. There should be no zero-extend operation.219define zeroext i8 @test_cross_block_zext_i8(i1 %tst, ptr %addr) {220; CHECK: test_cross_block_zext_i8:221; CHECK-NOT: uxtb222; CHECK-NOT: and223; CHECK: bx lr224 %val = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %addr)225 br i1 %tst, label %end, label %mid226mid:227 ret i8 42228end:229 %val8 = trunc i32 %val to i8230 ret i8 %val8231}232