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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -O0 -mtriple=armebv7 -target-abi apcs -o - %s | FileCheck %s3 4@vec6_p = external global <6 x i16>5 6define i32 @vec_to_int() {7; CHECK-LABEL: vec_to_int:8; CHECK: @ %bb.0: @ %bb.09; CHECK-NEXT: push {r4}10; CHECK-NEXT: sub sp, sp, #1611; CHECK-NEXT: movw r0, :lower16:vec6_p12; CHECK-NEXT: movt r0, :upper16:vec6_p13; CHECK-NEXT: vld1.8 {d16}, [r0]!14; CHECK-NEXT: ldr r0, [r0]15; CHECK-NEXT: @ implicit-def: $d1716; CHECK-NEXT: vmov.32 d17[0], r017; CHECK-NEXT: vrev32.16 d18, d1718; CHECK-NEXT: vrev16.8 d16, d1619; CHECK-NEXT: @ kill: def $d16 killed $d16 def $q820; CHECK-NEXT: vmov.f64 d17, d1821; CHECK-NEXT: vstmia sp, {d16, d17} @ 16-byte Spill22; CHECK-NEXT: b .LBB0_123; CHECK-NEXT: .LBB0_1: @ %bb.124; CHECK-NEXT: vldmia sp, {d16, d17} @ 16-byte Reload25; CHECK-NEXT: vrev32.16 q8, q826; CHECK-NEXT: vmov.f64 d16, d1727; CHECK-NEXT: vmov.32 r0, d16[0]28; CHECK-NEXT: add sp, sp, #1629; CHECK-NEXT: pop {r4}30; CHECK-NEXT: bx lr31bb.0:32 %vec6 = load <6 x i16>, ptr @vec6_p, align 133 br label %bb.134 35bb.1:36 %0 = bitcast <6 x i16> %vec6 to i9637 %1 = trunc i96 %0 to i3238 ret i32 %139}40 41define i16 @int_to_vec(i80 %in) {42; CHECK-LABEL: int_to_vec:43; CHECK: @ %bb.0:44; CHECK-NEXT: @ kill: def $r2 killed $r145; CHECK-NEXT: @ kill: def $r2 killed $r046; CHECK-NEXT: lsl r0, r0, #1647; CHECK-NEXT: orr r0, r0, r1, lsr #1648; CHECK-NEXT: @ implicit-def: $d1849; CHECK-NEXT: vmov.32 d18[0], r050; CHECK-NEXT: @ implicit-def: $q851; CHECK-NEXT: vmov.f64 d16, d1852; CHECK-NEXT: vrev32.16 q8, q853; CHECK-NEXT: @ kill: def $d16 killed $d16 killed $q854; CHECK-NEXT: vmov.u16 r0, d16[0]55; CHECK-NEXT: bx lr56 %vec = bitcast i80 %in to <5 x i16>57 %e0 = extractelement <5 x i16> %vec, i32 058 ret i16 %e059}60