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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=armv7-none-eabi -float-abi=soft | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT3; RUN: llc < %s -mtriple=armv7-none-eabihf -mattr=+vfp2 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP164; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FPv85; RUN: llc < %s -mtriple=armv8-none-eabihf -mattr=+fp-armv8,+fullfp16 -float-abi=hard | FileCheck %s --check-prefixes=CHECK,CHECK-FP166 7define i64 @testmsxh_builtin(half %x) {8; CHECK-SOFT-LABEL: testmsxh_builtin:9; CHECK-SOFT: @ %bb.0: @ %entry10; CHECK-SOFT-NEXT: .save {r11, lr}11; CHECK-SOFT-NEXT: push {r11, lr}12; CHECK-SOFT-NEXT: bl __aeabi_h2f13; CHECK-SOFT-NEXT: bl llrintf14; CHECK-SOFT-NEXT: pop {r11, pc}15;16; CHECK-NOFP16-LABEL: testmsxh_builtin:17; CHECK-NOFP16: @ %bb.0: @ %entry18; CHECK-NOFP16-NEXT: .save {r11, lr}19; CHECK-NOFP16-NEXT: push {r11, lr}20; CHECK-NOFP16-NEXT: vmov r0, s021; CHECK-NOFP16-NEXT: bl __aeabi_h2f22; CHECK-NOFP16-NEXT: vmov s0, r023; CHECK-NOFP16-NEXT: bl llrintf24; CHECK-NOFP16-NEXT: pop {r11, pc}25;26; CHECK-FPv8-LABEL: testmsxh_builtin:27; CHECK-FPv8: @ %bb.0: @ %entry28; CHECK-FPv8-NEXT: .save {r11, lr}29; CHECK-FPv8-NEXT: push {r11, lr}30; CHECK-FPv8-NEXT: vcvtb.f32.f16 s0, s031; CHECK-FPv8-NEXT: bl llrintf32; CHECK-FPv8-NEXT: pop {r11, pc}33;34; CHECK-FP16-LABEL: testmsxh_builtin:35; CHECK-FP16: @ %bb.0: @ %entry36; CHECK-FP16-NEXT: .save {r11, lr}37; CHECK-FP16-NEXT: push {r11, lr}38; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s039; CHECK-FP16-NEXT: bl llrintf40; CHECK-FP16-NEXT: pop {r11, pc}41entry:42 %0 = tail call i64 @llvm.llrint.i64.f16(half %x)43 ret i64 %044}45 46define i64 @testmsxs_builtin(float %x) {47; CHECK-LABEL: testmsxs_builtin:48; CHECK: @ %bb.0: @ %entry49; CHECK-NEXT: .save {r11, lr}50; CHECK-NEXT: push {r11, lr}51; CHECK-NEXT: bl llrintf52; CHECK-NEXT: pop {r11, pc}53entry:54 %0 = tail call i64 @llvm.llrint.i64.f32(float %x)55 ret i64 %056}57 58define i64 @testmsxd_builtin(double %x) {59; CHECK-LABEL: testmsxd_builtin:60; CHECK: @ %bb.0: @ %entry61; CHECK-NEXT: .save {r11, lr}62; CHECK-NEXT: push {r11, lr}63; CHECK-NEXT: bl llrint64; CHECK-NEXT: pop {r11, pc}65entry:66 %0 = tail call i64 @llvm.llrint.i64.f64(double %x)67 ret i64 %068}69 70define i64 @testmsxq_builtin(fp128 %x) {71; CHECK-LABEL: testmsxq_builtin:72; CHECK: @ %bb.0: @ %entry73; CHECK-NEXT: .save {r11, lr}74; CHECK-NEXT: push {r11, lr}75; CHECK-NEXT: bl llrintl76; CHECK-NEXT: pop {r11, pc}77entry:78 %0 = tail call i64 @llvm.llrint.i64.f128(fp128 %x)79 ret i64 %080}81