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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s3---4name: f5# Make sure the load into $r0 doesn't clobber the base register before the second load uses it.6body: |7 bb.0:8 liveins: $r0, $r39 ; CHECK-LABEL: name: f10 ; CHECK: $r3 = LDRi12 $r0, 12, 14 /* CC::al */, $noreg11 ; CHECK: $r0 = LDRi12 $r0, 8, 14 /* CC::al */, $noreg12 $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg13...14