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1; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE2; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-V7-LE3; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE4; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7-BE5; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6-THUMB6; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP7; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP8; RUN: llc -mtriple=thumbebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7-THUMB-BE9; RUN: llc -mtriple=thumbv6m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6M-THUMB10; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7M-THUMB11; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP12; RUN: llc -mtriple=armv5te-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V5TE13; Check generated signed and unsigned multiply accumulate long.14 15define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {16;CHECK-LABEL: MACLongTest1:17;CHECK-V6-THUMB-NOT: umlal18;CHECK-LE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]19;CHECK-LE: mov r0, [[RDLO]]20;CHECK-LE: mov r1, [[RDHI]]21;CHECK-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]22;CHECK-BE: mov r0, [[RDHI]]23;CHECK-BE: mov r1, [[RDLO]]24;CHECK-T2-DSP: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]25;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]26;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]27;CHECK-V7-THUMB-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]28;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]29;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]30 %conv = zext i32 %a to i6431 %conv1 = zext i32 %b to i6432 %mul = mul i64 %conv1, %conv33 %add = add i64 %mul, %c34 ret i64 %add35}36 37define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {38;CHECK-LABEL: MACLongTest2:39;CHECK-LE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]40;CHECK-LE: mov r0, [[RDLO]]41;CHECK-LE: mov r1, [[RDHI]]42;CHECK-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]43;CHECK-BE: mov r0, [[RDHI]]44;CHECK-BE: mov r1, [[RDLO]]45;CHECK-T2-DSP: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]46;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]47;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]48;CHECK-V7-THUMB-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]49;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]50;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]51 %conv = sext i32 %a to i6452 %conv1 = sext i32 %b to i6453 %mul = mul nsw i64 %conv1, %conv54 %add = add nsw i64 %mul, %c55 ret i64 %add56}57 58; Two things to check here: the @earlyclobber constraint (on <= v5) and the "$Rd = $R" ones.59; + Without @earlyclobber the v7 code is natural. With it, the first two60; registers must be distinct from the third.61; + Without "$Rd = $R", this can be satisfied without a mov before the umlal62; by trying to use 6 different registers in the MachineInstr. The natural63; evolution of this attempt currently leaves only two movs in the final64; function, both after the umlal. With it, *some* move has to happen65; before the umlal.66define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {67;CHECK-LABEL: MACLongTest3:68;CHECK-LE: mov [[RDHI:r[0-9]+]], #069;CHECK-LE: umlal [[RDLO:r[0-9]+]], [[RDHI]], r1, r070;CHECK-LE: mov r0, [[RDLO]]71;CHECK-LE: mov r1, [[RDHI]]72;CHECK-BE: mov [[RDHI:r[0-9]+]], #073;CHECK-BE: umlal [[RDLO:r[0-9]+]], [[RDHI]], r1, r074;CHECK-BE: mov r0, [[RDHI]]75;CHECK-BE: mov r1, [[RDLO]]76;CHECK-T2-DSP: umlal77;CHECK-V6-THUMB-NOT: umlal78 %conv = zext i32 %b to i6479 %conv1 = zext i32 %a to i6480 %mul = mul i64 %conv, %conv181 %conv2 = zext i32 %c to i6482 %add = add i64 %mul, %conv283 ret i64 %add84}85 86define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {87;CHECK-LABEL: MACLongTest4:88;CHECK-V6-THUMB-NOT: smlal89;CHECK-T2-DSP: smlal90;CHECK-LE: asr [[RDHI:r[0-9]+]], [[RDLO:r[0-9]+]], #3191;CHECK-LE: smlal [[RDLO]], [[RDHI]], r1, r092;CHECK-LE: mov r0, [[RDLO]]93;CHECK-LE: mov r1, [[RDHI]]94;CHECK-BE: asr [[RDHI:r[0-9]+]], [[RDLO:r[0-9]+]], #3195;CHECK-BE: smlal [[RDLO]], [[RDHI]], r1, r096;CHECK-BE: mov r0, [[RDHI]]97;CHECK-BE: mov r1, [[RDLO]]98 %conv = sext i32 %b to i6499 %conv1 = sext i32 %a to i64100 %mul = mul nsw i64 %conv, %conv1101 %conv2 = sext i32 %c to i64102 %add = add nsw i64 %mul, %conv2103 ret i64 %add104}105 106define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) {107;CHECK-LABEL: MACLongTest6:108;CHECK-V6-THUMB-NOT: smull109;CHECK-V6-THUMB-NOT: smlal110;CHECK-LE: smull r12, lr, r1, r0111;CHECK-LE: smlal r12, lr, r3, r2112;CHECK-V7: smull [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], r1, r0113;CHECK-V7: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]114;CHECK-T2-DSP: smull [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], r1, r0115;CHECK-T2-DSP: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]116 %conv = sext i32 %a to i64117 %conv1 = sext i32 %b to i64118 %mul = mul nsw i64 %conv1, %conv119 %conv2 = sext i32 %c to i64120 %conv3 = sext i32 %d to i64121 %mul4 = mul nsw i64 %conv3, %conv2122 %add = add nsw i64 %mul4, %mul123 ret i64 %add124}125 126define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) {127;CHECK-LABEL: MACLongTest7:128;CHECK-NOT: smlal129;CHECK-V6-THUMB2-NOT: smlal130;CHECK-V7-THUMB-NOT: smlal131;CHECK-V6-THUMB-NOT: smlal132 %conv = sext i32 %lhs to i64133 %conv1 = sext i32 %rhs to i64134 %mul = mul nsw i64 %conv1, %conv135 %shl = shl i64 %mul, 32136 %shr = lshr i64 %mul, 32137 %or = or i64 %shl, %shr138 %add = add i64 %or, %acc139 ret i64 %add140}141 142define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) {143;CHECK-LABEL: MACLongTest8:144;CHECK-NOT: smlal145;CHECK-V6-THUMB2-NOT: smlal146;CHECK-V7-THUMB-NOT: smlal147;CHECK-V6-THUMB-NOT: smlal148 %conv = zext i32 %lhs to i64149 %conv1 = zext i32 %rhs to i64150 %mul = mul nuw i64 %conv1, %conv151 %and = and i64 %mul, 4294967295152 %shl = shl i64 %mul, 32153 %or = or i64 %and, %shl154 %add = add i64 %or, %acc155 ret i64 %add156}157 158define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {159;CHECK-LABEL: MACLongTest9:160;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]161;CHECK-V7-LE: mov r0, [[RDLO]]162;CHECK-V7-LE: mov r1, [[RDHI]]163;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]164;CHECK-V7-BE: mov r0, [[RDHI]]165;CHECK-V7-BE: mov r1, [[RDLO]]166;CHECK-T2-DSP: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]167;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]168;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]169;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]170;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]171;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]172;CHECK-NOT:umaal173;CHECK-V6-THUMB-NOT: umaal174;CHECK-V6M-THUMB-NOT: umaal175;CHECK-V7M-THUMB-NOT: umaal176 %conv = zext i32 %lhs to i64177 %conv1 = zext i32 %rhs to i64178 %mul = mul nuw i64 %conv1, %conv179 %conv2 = zext i32 %lo to i64180 %add = add i64 %mul, %conv2181 %conv3 = zext i32 %hi to i64182 %add2 = add i64 %add, %conv3183 ret i64 %add2184}185 186define i64 @MACLongTest10(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {187;CHECK-LABEL: MACLongTest10:188;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]189;CHECK-V7-LE: mov r0, [[RDLO]]190;CHECK-V7-LE: mov r1, [[RDHI]]191;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]192;CHECK-V7-BE: mov r0, [[RDHI]]193;CHECK-V7-BE: mov r1, [[RDLO]]194;CHECK-T2-DSP: umaal r2, r3, r1, r0195;CHECK-T2-DSP-NEXT: mov r0, r2196;CHECK-T2-DSP-NEXT: mov r1, r3197;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]198;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]199;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]200;CHECK-NOT:umaal201;CHECK-V6-THUMB-NOT:umaal202;CHECK-V6M-THUMB-NOT: umaal203;CHECK-V7M-THUMB-NOT: umaal204 %conv = zext i32 %lhs to i64205 %conv1 = zext i32 %rhs to i64206 %mul = mul nuw i64 %conv1, %conv207 %conv2 = zext i32 %lo to i64208 %conv3 = zext i32 %hi to i64209 %add = add i64 %conv2, %conv3210 %add2 = add i64 %add, %mul211 ret i64 %add2212}213 214define i64 @MACLongTest11(i16 %a, i16 %b, i64 %c) {215;CHECK-LABEL: MACLongTest11:216;CHECK-T2-DSP-NOT: sxth217;CHECK-T2-DSP: smlalbb r2, r3218;CHECK-T2-DSP-NEXT: mov r0, r2219;CHECK-T2-DSP-NEXT: mov r1, r3220;CHECK-V5TE-NOT: sxth221;CHECK-V5TE: smlalbb r2, r3222;CHECK-V5TE-NEXT: mov r0, r2223;CHECK-V5TE-NEXT: mov r1, r3224;CHECK-V7-LE-NOT: sxth225;CHECK-V7-LE: smlalbb r2, r3226;CHECK-V7-LE-NEXT: mov r0, r2227;CHECK-V7-LE-NEXT: mov r1, r3228;CHECK-V7-THUMB-BE: smlalbb r3, r2229;CHECK-V7-THUMB-BE-NEXT: mov r0, r2230;CHECK-V7-THUMB-BE-NEXT: mov r1, r3231;CHECK-LE-NOT: smlalbb232;CHECK-BE-NOT: smlalbb233;CHECK-V6M-THUMB-NOT: smlalbb234;CHECK-V7M-THUMB-NOT: smlalbb235 %conv = sext i16 %a to i32236 %conv1 = sext i16 %b to i32237 %mul = mul nsw i32 %conv1, %conv238 %conv2 = sext i32 %mul to i64239 %add = add nsw i64 %conv2, %c240 ret i64 %add241}242 243define i64 @MACLongTest12(i16 %b, i32 %t, i64 %c) {244;CHECK-LABEL: MACLongTest12:245;CHECK-T2-DSP-NOT: sxth246;CHECK-T2-DSP-NOT: {{asr|lsr}}247;CHECK-T2-DSP: smlalbt r2, r3, r0, r1248;CHECK-T2-DSP-NEXT: mov r0, r2249;CHECK-T2-DSP-NEXT: mov r1, r3250;CHECK-T2-DSP-NOT: sxth251;CHECK-V5TE-NOT: sxth252;CHECK-V5TE-NOT: {{asr|lsr}}253;CHECK-V5TE: smlalbt r2, r3, r0, r1254;CHECK-V5TE-NEXT: mov r0, r2255;CHECK-V5TE-NEXT: mov r1, r3256;CHECK-V7-LE-NOT: sxth257;CHECK-V7-LE-NOT: {{asr|lsr}}258;CHECK-V7-LE: smlalbt r2, r3, r0, r1259;CHECK-V7-LE-NEXT: mov r0, r2260;CHECK-V7-LE-NEXT: mov r1, r3261;CHECK-V7-THUMB-BE: smlalbt r3, r2,262;CHECK-V7-THUMB-BE-NEXT: mov r0, r2263;CHECK-V7-THUMB-BE-NEXT: mov r1, r3264;CHECK-LE-NOT: smlalbt265;CHECK-BE-NOT: smlalbt266;CHECK-V6M-THUMB-NOT: smlalbt267;CHECK-V7M-THUMB-NOT: smlalbt268 %conv0 = sext i16 %b to i32269 %conv1 = ashr i32 %t, 16270 %mul = mul nsw i32 %conv0, %conv1271 %conv2 = sext i32 %mul to i64272 %add = add nsw i64 %conv2, %c273 ret i64 %add274}275 276define i64 @MACLongTest13(i32 %t, i16 %b, i64 %c) {277;CHECK-LABEL: MACLongTest13:278;CHECK-T2-DSP-NOT: sxth279;CHECK-T2-DSP-NOT: {{asr|lsr}}280;CHECK-T2-DSP: smlaltb r2, r3, r0, r1281;CHECK-T2-DSP-NEXT: mov r0, r2282;CHECK-T2-DSP-NEXT: mov r1, r3283;CHECK-V5TE-NOT: sxth284;CHECK-V5TE-NOT: {{asr|lsr}}285;CHECK-V5TE: smlaltb r2, r3, r0, r1286;CHECK-V5TE-NEXT: mov r0, r2287;CHECK-V5TE-NEXT: mov r1, r3288;CHECK-V7-LE-NOT: sxth289;CHECK-V7-LE-NOT: {{asr|lsr}}290;CHECK-V7-LE: smlaltb r2, r3, r0, r1291;CHECK-V7-LE-NEXT: mov r0, r2292;CHECK-V7-LE-NEXT: mov r1, r3293;CHECK-V7-THUMB-BE: smlaltb r3, r2, r0, r1294;CHECK-V7-THUMB-BE-NEXT: mov r0, r2295;CHECK-V7-THUMB-BE-NEXT: mov r1, r3296;CHECK-LE-NOT: smlaltb297;CHECK-BE-NOT: smlaltb298;CHECK-V6M-THUMB-NOT: smlaltb299;CHECK-V7M-THUMB-NOT: smlaltb300 %conv0 = ashr i32 %t, 16301 %conv1= sext i16 %b to i32302 %mul = mul nsw i32 %conv0, %conv1303 %conv2 = sext i32 %mul to i64304 %add = add nsw i64 %conv2, %c305 ret i64 %add306}307 308define i64 @MACLongTest14(i32 %a, i32 %b, i64 %c) {309;CHECK-LABEL: MACLongTest14:310;CHECK-T2-DSP-NOT: {{asr|lsr}}311;CHECK-T2-DSP: smlaltt r2, r3,312;CHECK-T2-DSP-NEXT: mov r0, r2313;CHECK-T2-DSP-NEXT: mov r1, r3314;CHECK-V5TE-NOT: {{asr|lsr}}315;CHECK-V5TE: smlaltt r2, r3,316;CHECK-V5TE-NEXT: mov r0, r2317;CHECK-V5TE-NEXT: mov r1, r3318;CHECK-V7-LE-NOT: {{asr|lsr}}319;CHECK-V7-LE: smlaltt r2, r3,320;CHECK-V7-LE-NEXT: mov r0, r2321;CHECK-V7-LE-NEXT: mov r1, r3322;CHECK-V7-THUMB-BE: smlaltt r3, r2,323;CHECK-V7-THUMB-BE-NEXT: mov r0, r2324;CHECK-V7-THUMB-BE-NEXT: mov r1, r3325;CHECK-LE-NOT: smlaltt326;CHECK-BE-NOT: smlaltt327;CHECK-V6M-THUMB-NOT: smlaltt328;CHECK-V7M-THUMB-NOT: smlaltt329 %conv0 = ashr i32 %a, 16330 %conv1 = ashr i32 %b, 16331 %mul = mul nsw i32 %conv1, %conv0332 %conv2 = sext i32 %mul to i64333 %add = add nsw i64 %conv2, %c334 ret i64 %add335}336 337@global_b = external global i16, align 2338;CHECK-LABEL: MACLongTest15339;CHECK-T2-DSP-NOT: {{asr|lsr}}340;CHECK-T2-DSP: mov r1, r3341;CHECK-T2-DSP: smlaltb r2, r1, r0, r3342;CHECK-T2-DSP-NEXT: mov r0, r2343;CHECK-V5TE-NOT: {{asr|lsr}}344;CHECK-V5TE: mov r1, r3345;CHECK-V5TE: smlaltb r2, r1, r0, r3346;CHECK-V5TE-NEXT: mov r0, r2347;CHECK-V7-LE-NOT: {{asr|lsr}}348;CHECK-V7-LE: mov r1, r3349;CHECK-V7-LE: smlaltb r2, r1, r0, r3350;CHECK-V7-LE-NEXT: mov r0, r2351;CHECK-V7-THUMB-BE: mov r1, r3352;CHECK-V7-THUMB-BE: smlaltb r1, r2, r0, r3353;CHECK-V7-THUMB-BE-NEXT: mov r0, r2354;CHECK-LE-NOT: smlaltb355;CHECK-BE-NOT: smlaltb356;CHECK-V6M-THUMB-NOT: smlaltb357;CHECK-V7M-THUMB-NOT: smlaltb358define i64 @MACLongTest15(i32 %t, i64 %acc) {359entry:360 %0 = load i16, ptr @global_b, align 2361 %conv = sext i16 %0 to i32362 %shr = ashr i32 %t, 16363 %mul = mul nsw i32 %shr, %conv364 %conv1 = sext i32 %mul to i64365 %add = add nsw i64 %conv1, %acc366 ret i64 %add367}368 369;CHECK-LABEL: MACLongTest16370;CHECK-T2-DSP-NOT: {{asr|lsr}}371;CHECK-T2-DSP: mov r1, r3372;CHECK-T2-DSP: smlalbt r2, r1, r3, r0373;CHECK-T2-DSP-NEXT: mov r0, r2374;CHECK-V5TE-NOT: {{asr|lsr}}375;CHECK-V5TE: mov r1, r3376;CHECK-V5TE: smlalbt r2, r1, r3, r0377;CHECK-V5TE-NEXT: mov r0, r2378;CHECK-V7-LE: mov r1, r3379;CHECK-V7-LE: smlalbt r2, r1, r3, r0380;CHECK-V7-LE-NEXT: mov r0, r2381;CHECK-V7-THUMB-BE: mov r1, r3382;CHECK-V7-THUMB-BE: smlalbt r1, r2, r3, r0383;CHECK-V7-THUMB-BE-NEXT: mov r0, r2384;CHECK-LE-NOT: smlalbt385;CHECK-BE-NOT: smlalbt386;CHECK-V6M-THUMB-NOT: smlalbt387;CHECK-V7M-THUMB-NOT: smlalbt388define i64 @MACLongTest16(i32 %t, i64 %acc) {389entry:390 %0 = load i16, ptr @global_b, align 2391 %conv = sext i16 %0 to i32392 %shr = ashr i32 %t, 16393 %mul = mul nsw i32 %conv, %shr394 %conv1 = sext i32 %mul to i64395 %add = add nsw i64 %conv1, %acc396 ret i64 %add397}398