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1; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s2; Should use scaled addressing mode.3 4; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF5; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF6; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF7; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52plus %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF8; Should not generate negated register offset9 10define void @sintzero(ptr %a) nounwind {11entry:12 store i32 0, ptr %a13 br label %cond_next14 15cond_next: ; preds = %cond_next, %entry16 %indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ] ; <i32> [#uses=1]17 %tmp25 = add i32 %indvar, 1 ; <i32> [#uses=3]18 %tmp36 = getelementptr i32, ptr %a, i32 %tmp25 ; <ptr> [#uses=1]19 store i32 0, ptr %tmp3620 icmp eq i32 %tmp25, -1 ; <i1>:0 [#uses=1]21 br i1 %0, label %return, label %cond_next22 23return: ; preds = %cond_next24 ret void25}26 27; CHECK: lsl{{.*}}#2]28; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]29 30