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1# RUN: llc -mtriple=armv7-- -run-pass=prologepilog -run-pass=machine-outliner \2# RUN: -verify-machineinstrs %s -o - | FileCheck %s3 4--- |5 define void @CheckAddrMode_i12() { ret void }6 define void @CheckAddrMode3() { ret void }7 define void @CheckAddrMode5() { ret void }8 define void @CheckAddrMode5FP16() { ret void }9 define void @foo() { ret void }10 11...12---13 14name: CheckAddrMode_i1215tracksRegLiveness: true16body: |17 bb.0:18 liveins: $r019 ; CHECK-LABEL: name: CheckAddrMode_i1220 ; CHECK: $r1 = MOVr killed $r0, 14 /* CC::al */, $noreg, $noreg21 ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp22 ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I12:[0-9]+]]23 ; CHECK-NEXT: $r6 = LDRi12 $sp, 4088, 14 /* CC::al */, $noreg24 $r1 = MOVr killed $r0, 14, $noreg, $noreg25 BL @foo, implicit-def dead $lr, implicit $sp26 $r1 = LDRi12 $sp, 0, 14, $noreg27 $r2 = LDRi12 $sp, 8, 14, $noreg28 $r5 = LDRi12 $sp, 4086, 14, $noreg29 $r6 = LDRi12 $sp, 4088, 14, $noreg30 BL @foo, implicit-def dead $lr, implicit $sp31 $r1 = LDRi12 $sp, 0, 14, $noreg32 $r2 = LDRi12 $sp, 8, 14, $noreg33 $r5 = LDRi12 $sp, 4086, 14, $noreg34 $r6 = LDRi12 $sp, 4088, 14, $noreg35 BL @foo, implicit-def dead $lr, implicit $sp36 $r1 = LDRi12 $sp, 0, 14, $noreg37 $r2 = LDRi12 $sp, 8, 14, $noreg38 $r5 = LDRi12 $sp, 4086, 14, $noreg39 $r6 = LDRi12 $sp, 4088, 14, $noreg40 BX_RET 14, $noreg41...42---43 44name: CheckAddrMode345tracksRegLiveness: true46body: |47 bb.0:48 liveins: $r149 ; CHECK-LABEL: name: CheckAddrMode350 ; CHECK: $r0 = MOVr killed $r1, 14 /* CC::al */, $noreg, $noreg51 ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp52 ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I3:[0-9]+]]53 ; CHECK-NEXT: $r6 = LDRSH $sp, $noreg, 248, 14 /* CC::al */, $noreg54 $r0 = MOVr killed $r1, 14, $noreg, $noreg55 BL @foo, implicit-def dead $lr, implicit $sp56 $r1 = LDRSH $sp, $noreg, 0, 14, $noreg57 $r2 = LDRSH $sp, $noreg, 8, 14, $noreg58 $r5 = LDRSH $sp, $noreg, 247, 14, $noreg59 $r6 = LDRSH $sp, $noreg, 248, 14, $noreg60 BL @foo, implicit-def dead $lr, implicit $sp61 $r1 = LDRSH $sp, $noreg, 0, 14, $noreg62 $r2 = LDRSH $sp, $noreg, 8, 14, $noreg63 $r5 = LDRSH $sp, $noreg, 247, 14, $noreg64 $r6 = LDRSH $sp, $noreg, 248, 14, $noreg65 BL @foo, implicit-def dead $lr, implicit $sp66 $r1 = LDRSH $sp, $noreg, 0, 14, $noreg67 $r2 = LDRSH $sp, $noreg, 8, 14, $noreg68 $r5 = LDRSH $sp, $noreg, 247, 14, $noreg69 $r6 = LDRSH $sp, $noreg, 248, 14, $noreg70 BX_RET 14, $noreg71...72---73 74name: CheckAddrMode575tracksRegLiveness: true76body: |77 bb.0:78 liveins: $r279 ; CHECK-LABEL: name: CheckAddrMode580 ; CHECK: $r0 = MOVr killed $r2, 14 /* CC::al */, $noreg, $noreg81 ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp82 ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I5:[0-9]+]]83 ; CHECK-NEXT: $d5 = VLDRD $sp, 254, 14 /* CC::al */, $noreg84 $r0 = MOVr killed $r2, 14, $noreg, $noreg85 BL @foo, implicit-def dead $lr, implicit $sp86 $d0 = VLDRD $sp, 0, 14, $noreg87 $d1 = VLDRD $sp, 8, 14, $noreg88 $d4 = VLDRD $sp, 253, 14, $noreg89 $d5 = VLDRD $sp, 254, 14, $noreg90 BL @foo, implicit-def dead $lr, implicit $sp91 $d0 = VLDRD $sp, 0, 14, $noreg92 $d1 = VLDRD $sp, 8, 14, $noreg93 $d4 = VLDRD $sp, 253, 14, $noreg94 $d5 = VLDRD $sp, 254, 14, $noreg95 BL @foo, implicit-def dead $lr, implicit $sp96 $d0 = VLDRD $sp, 0, 14, $noreg97 $d1 = VLDRD $sp, 8, 14, $noreg98 $d4 = VLDRD $sp, 253, 14, $noreg99 $d5 = VLDRD $sp, 254, 14, $noreg100 BL @foo, implicit-def dead $lr, implicit $sp101 $d0 = VLDRD $sp, 0, 14, $noreg102 $d1 = VLDRD $sp, 8, 14, $noreg103 $d4 = VLDRD $sp, 253, 14, $noreg104 $d5 = VLDRD $sp, 254, 14, $noreg105 BX_RET 14, $noreg106...107---108 109name: CheckAddrMode5FP16110tracksRegLiveness: true111body: |112 bb.0:113 liveins: $r3114 ; CHECK-LABEL: name: CheckAddrMode5FP16115 ; CHECK: $r0 = MOVr killed $r3, 14 /* CC::al */, $noreg, $noreg116 ; CHECK-NEXT: BL @foo, implicit-def dead $lr, implicit $sp117 ; CHECK-NEXT: BL @OUTLINED_FUNCTION_[[I5FP16:[0-9]+]]118 ; CHECK-NEXT: $s6 = VLDRH $sp, 252, 14, $noreg119 $r0 = MOVr killed $r3, 14, $noreg, $noreg120 BL @foo, implicit-def dead $lr, implicit $sp121 $s1 = VLDRH $sp, 0, 14, $noreg122 $s2 = VLDRH $sp, 8, 14, $noreg123 $s5 = VLDRH $sp, 240, 14, $noreg124 $s6 = VLDRH $sp, 252, 14, $noreg125 BL @foo, implicit-def dead $lr, implicit $sp126 $s1 = VLDRH $sp, 0, 14, $noreg127 $s2 = VLDRH $sp, 8, 14, $noreg128 $s5 = VLDRH $sp, 240, 14, $noreg129 $s6 = VLDRH $sp, 252, 14, $noreg130 BL @foo, implicit-def dead $lr, implicit $sp131 $s1 = VLDRH $sp, 0, 14, $noreg132 $s2 = VLDRH $sp, 8, 14, $noreg133 $s5 = VLDRH $sp, 240, 14, $noreg134 $s6 = VLDRH $sp, 252, 14, $noreg135 BL @foo, implicit-def dead $lr, implicit $sp136 $s1 = VLDRH $sp, 0, 14, $noreg137 $s2 = VLDRH $sp, 8, 14, $noreg138 $s5 = VLDRH $sp, 240, 14, $noreg139 $s6 = VLDRH $sp, 252, 14, $noreg140 BX_RET 14, $noreg141...142---143 144name: foo145tracksRegLiveness: true146body: |147 bb.0:148 liveins: $lr149 150 BX_RET 14, $noreg151 152 ;CHECK: name: OUTLINED_FUNCTION_[[I5]]153 ;CHECK: liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8154 ;CHECK: $d0 = VLDRD $sp, 0, 14 /* CC::al */, $noreg155 ;CHECK-NEXT: $d1 = VLDRD $sp, 8, 14 /* CC::al */, $noreg156 ;CHECK-NEXT: $d4 = VLDRD $sp, 253, 14 /* CC::al */, $noreg157 ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg158 159 ;CHECK: name: OUTLINED_FUNCTION_[[I5FP16]]160 ;CHECK: liveins: $r10, $r9, $r8, $r7, $r6, $r5, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9, $d8161 ;CHECK: $s1 = VLDRH $sp, 0, 14, $noreg162 ;CHECK-NEXT: $s2 = VLDRH $sp, 8, 14, $noreg163 ;CHECK-NEXT: $s5 = VLDRH $sp, 240, 14, $noreg164 ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg165 166 ;CHECK: name: OUTLINED_FUNCTION_[[I12]]167 ;CHECK: liveins: $r10, $r9, $r8, $r7, $d8, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9168 ;CHECK: $r1 = LDRi12 $sp, 0, 14 /* CC::al */, $noreg169 ;CHECK-NEXT: $r2 = LDRi12 $sp, 8, 14 /* CC::al */, $noreg170 ;CHECK-NEXT: $r5 = LDRi12 $sp, 4086, 14 /* CC::al */, $noreg171 ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg172 173 ;CHECK: name: OUTLINED_FUNCTION_[[I3]]174 ;CHECK: liveins: $r10, $r9, $r8, $r7, $d8, $r4, $d15, $d14, $d13, $d12, $d11, $d10, $d9175 ;CHECK: $r1 = LDRSH $sp, $noreg, 0, 14 /* CC::al */, $noreg176 ;CHECK-NEXT: $r2 = LDRSH $sp, $noreg, 8, 14 /* CC::al */, $noreg177 ;CHECK-NEXT: $r5 = LDRSH $sp, $noreg, 247, 14 /* CC::al */, $noreg178 ;CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg179