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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=thumbv7-- -run-pass=machine-outliner -verify-machineinstrs \3# RUN: %s -o - | FileCheck %s4 5--- |6 define void @dont_outline_asm() #0 { ret void }7 define void @dont_outline_lr() #0 { ret void }8 define void @dont_outline_lr2() #0 { ret void }9 define void @dont_outline_it() #0 { ret void }10 define void @dont_outline_pic() #0 { ret void }11 define void @dont_outline_mve() #0 { ret void }12 declare void @z(i32, i32, i32, i32)13 14 attributes #0 = { minsize optsize }15...16---17 18name: dont_outline_asm19tracksRegLiveness: true20body: |21 ; CHECK-LABEL: name: dont_outline_asm22 ; CHECK: bb.0:23 ; CHECK: INLINEASM &"movs r0, #42", 124 ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_025 ; CHECK: bb.1:26 ; CHECK: INLINEASM &"movs r0, #42", 127 ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_028 bb.0:29 INLINEASM &"movs r0, #42", 130 $r0, dead $cpsr = tMOVi8 1, 14, $noreg31 $r1, dead $cpsr = tMOVi8 1, 14, $noreg32 $r2, dead $cpsr = tMOVi8 1, 14, $noreg33 $r3, dead $cpsr = tMOVi8 1, 14, $noreg34 tBL 14, $noreg, @z35 bb.1:36 INLINEASM &"movs r0, #42", 137 $r0, dead $cpsr = tMOVi8 1, 14, $noreg38 $r1, dead $cpsr = tMOVi8 1, 14, $noreg39 $r2, dead $cpsr = tMOVi8 1, 14, $noreg40 $r3, dead $cpsr = tMOVi8 1, 14, $noreg41 tBL 14, $noreg, @z42 bb.2:43 tBX_RET 14, $noreg44...45---46 47name: dont_outline_lr48tracksRegLiveness: true49body: |50 ; CHECK-LABEL: name: dont_outline_lr51 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION52 bb.0:53 liveins: $lr54 $r0 = tMOVr $lr, 14, $noreg55 $r1 = tMOVr $lr, 14, $noreg56 $r2 = tMOVr $lr, 14, $noreg57 $r3 = tMOVr $lr, 14, $noreg58 tBL 14, $noreg, @z59 bb.1:60 liveins: $lr61 $r0 = tMOVr $lr, 14, $noreg62 $r1 = tMOVr $lr, 14, $noreg63 $r2 = tMOVr $lr, 14, $noreg64 $r3 = tMOVr $lr, 14, $noreg65 tBL 14, $noreg, @z66 bb.2:67 tBX_RET 14, $noreg68...69---70 71name: dont_outline_lr272tracksRegLiveness: true73body: |74 ; CHECK-LABEL: name: dont_outline_lr275 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION76 bb.0:77 liveins: $r078 $lr = tMOVr $r0, 14, $noreg79 $r1 = tMOVr $r0, 14, $noreg80 $r2 = tMOVr $r0, 14, $noreg81 $r3 = tMOVr $r0, 14, $noreg82 $r4 = tMOVr $r0, 14, $noreg83 tBLXr 14, $noreg, $lr84 bb.1:85 liveins: $r086 $lr = tMOVr $r0, 14, $noreg87 $r1 = tMOVr $r0, 14, $noreg88 $r2 = tMOVr $r0, 14, $noreg89 $r3 = tMOVr $r0, 14, $noreg90 $r4 = tMOVr $r0, 14, $noreg91 tBLXr 14, $noreg, $lr92 bb.2:93 tBX_RET 14, $noreg94...95---96 97name: dont_outline_it98tracksRegLiveness: true99body: |100 ; CHECK-LABEL: name: dont_outline_it101 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION102 bb.0:103 t2IT 0, 1, implicit-def $itstate104 $r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate105 $r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate106 $r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate107 $r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate108 tBL 14, $noreg, @z109 bb.1:110 t2IT 0, 1, implicit-def $itstate111 $r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate112 $r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate113 $r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate114 $r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate115 tBL 14, $noreg, @z116 bb.2:117 tBX_RET 14, $noreg118...119---120 121name: dont_outline_pic122tracksRegLiveness: true123body: |124 ; CHECK-LABEL: name: dont_outline_pic125 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION126 bb.0:127 $r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0128 $r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0129 $r0 = PICADD $r0, 1, 14, $noreg130 $r1 = PICLDR $r0, 2, 14, $noreg131 PICSTR $r0, $r1, 3, 14, $noreg132 tBL 14, $noreg, @z133 bb.1:134 $r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0135 $r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0136 $r0 = PICADD $r0, 1, 14, $noreg137 $r1 = PICLDR $r0, 2, 14, $noreg138 PICSTR $r0, $r1, 3, 14, $noreg139 tBL 14, $noreg, @z140 bb.2:141 tBX_RET 14, $noreg142...143---144 145name: dont_outline_mve146tracksRegLiveness: true147body: |148 ; CHECK-LABEL: name: dont_outline_mve149 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION150 bb.0:151 liveins: $r3, $r4, $q0, $q3, $q4, $q5152 $q5 = MVE_VDUP32 $r3, 0, $noreg, $noreg, $q5153 $q4 = MVE_VDUP32 $r4, 0, $noreg, $noreg, $q4154 $q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $noreg, $q0155 $lr = t2DoLoopStart $r4156 $r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg157 tBL 14, $noreg, @z158 bb.1:159 liveins: $r3, $r4, $q0, $q3, $q4, $q5160 $q5 = MVE_VDUP32 $r3, 0, $noreg, $noreg, $q5161 $q4 = MVE_VDUP32 $r4, 0, $noreg, $noreg, $q4162 $q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $noreg, $q0163 $lr = t2DoLoopStart $r4164 $r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg165 tBL 14, $noreg, @z166 bb.2:167 tBX_RET 14, $noreg168