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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -o - -run-pass=machine-sink -mtriple=arm-none-eabi | FileCheck %s3 4# RUN: llc %s -o - -passes=machine-sink -mtriple=arm-none-eabi | FileCheck %s5 6--- |7 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"8 target triple = "arm-none-unknown-eabi"9 10 %struct.anon = type { i32, i32 }11 12 @e = external constant [2 x %struct.anon], align 413 14 define arm_aapcscc void @g(ptr noalias %a, ptr %b, i32 %x) {15 entry:16 %c = getelementptr inbounds [2 x %struct.anon], ptr @e, i32 0, i32 %x, i32 017 %l1 = load i32, ptr %c, align 418 %d = getelementptr inbounds [2 x %struct.anon], ptr @e, i32 0, i32 %x, i32 119 %l2 = load i32, ptr %d, align 420 br i1 undef, label %land.lhs.true, label %if.end21 22 land.lhs.true: ; preds = %entry23 br label %if.end24 25 if.end: ; preds = %land.lhs.true, %entry26 %h.0 = phi i32 [ %l1, %entry ], [ 0, %land.lhs.true ]27 ret void28 }29 30...31---32name: g33tracksRegLiveness: true34registers:35 - { id: 0, class: gpr, preferred-register: '' }36 - { id: 1, class: gpr, preferred-register: '' }37 - { id: 2, class: gpr, preferred-register: '' }38 - { id: 6, class: gpr, preferred-register: '' }39 - { id: 7, class: gpr, preferred-register: '' }40 - { id: 8, class: gpr, preferred-register: '' }41 - { id: 9, class: gprnopc, preferred-register: '' }42liveins:43 - { reg: '$r0', virtual-reg: '%8' }44 - { reg: '$r1', virtual-reg: '%9' }45body: |46 ; CHECK-LABEL: name: g47 ; CHECK: bb.0:48 ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)49 ; CHECK: liveins: $r0, $r150 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r151 ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r052 ; CHECK: [[LDR_PRE_REG:%[0-9]+]]:gpr, [[LDR_PRE_REG1:%[0-9]+]]:gpr = LDR_PRE_REG [[COPY]], killed [[COPY1]], 16387, 14 /* CC::al */, $noreg :: (load (s32) from %ir.c)53 ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg54 ; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr55 ; CHECK: Bcc %bb.1, 0 /* CC::eq */, $cpsr56 ; CHECK: bb.3:57 ; CHECK: successors: %bb.2(0x80000000)58 ; CHECK: B %bb.259 ; CHECK: bb.1:60 ; CHECK: successors: %bb.2(0x80000000)61 ; CHECK: bb.2:62 ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[LDR_PRE_REG]], %bb.3, [[MOVi]], %bb.163 ; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr64 ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 killed [[LDR_PRE_REG1]], 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.d)65 ; CHECK: MOVPCLR 14 /* CC::al */, $noreg66 bb.0:67 liveins: $r0, $r168 successors: %bb.1(0x40000000), %bb.2(0x40000000)69 70 %8:gpr = COPY $r171 %9:gprnopc = COPY $r072 %0:gpr, %6:gpr = LDR_PRE_REG %8, killed %9, 16387, 14, $noreg :: (load (s32) from %ir.c)73 %7:gpr = MOVi 0, 14, $noreg, $noreg74 CMPri %7, 0, 14, $noreg, implicit-def $cpsr75 Bcc %bb.2, 1, $cpsr76 B %bb.177 78 bb.1:79 successors: %bb.2(0x80000000)80 81 bb.2:82 83 %2:gpr = PHI %0, %bb.0, %7, %bb.184 CMPri %7, 0, 14, $noreg, implicit-def $cpsr85 %1:gpr = LDRi12 killed %6, 4, 14, $noreg :: (load (s32) from %ir.d)86 MOVPCLR 14, $noreg87 88...89