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1; RUN: llc < %s -mtriple=armv8-linux-gnu -mattr=+neon | FileCheck %s2 3; CHECK-LABEL: t14; CHECK: vmax.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}5define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) {6 %t1 = icmp sgt <4 x i32> %a, %b7 %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b8 ret <4 x i32> %t29}10 11; CHECK-LABEL: t212; CHECK: vmin.s32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}13define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) {14 %t1 = icmp slt <4 x i32> %a, %b15 %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b16 ret <4 x i32> %t217}18 19; CHECK-LABEL: t320; CHECK: vmax.u32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}21define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) {22 %t1 = icmp ugt <4 x i32> %a, %b23 %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b24 ret <4 x i32> %t225}26 27; CHECK-LABEL: t428; CHECK: vmin.u32 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}29define <4 x i32> @t4(<4 x i32> %a, <4 x i32> %b) {30 %t1 = icmp ult <4 x i32> %a, %b31 %t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b32 ret <4 x i32> %t233}34 35; CHECK-LABEL: t536; CHECK: vmax.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}37define <2 x i32> @t5(<2 x i32> %a, <2 x i32> %b) {38 %t1 = icmp sgt <2 x i32> %a, %b39 %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b40 ret <2 x i32> %t241}42 43; CHECK-LABEL: t644; CHECK: vmin.s32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}45define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) {46 %t1 = icmp slt <2 x i32> %a, %b47 %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b48 ret <2 x i32> %t249}50 51; CHECK-LABEL: t752; CHECK: vmax.u32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}53define <2 x i32> @t7(<2 x i32> %a, <2 x i32> %b) {54 %t1 = icmp ugt <2 x i32> %a, %b55 %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b56 ret <2 x i32> %t257}58 59; CHECK-LABEL: t860; CHECK: vmin.u32 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}61define <2 x i32> @t8(<2 x i32> %a, <2 x i32> %b) {62 %t1 = icmp ult <2 x i32> %a, %b63 %t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b64 ret <2 x i32> %t265}66 67; CHECK-LABEL: t968; CHECK: vmax.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}69define <8 x i16> @t9(<8 x i16> %a, <8 x i16> %b) {70 %t1 = icmp sgt <8 x i16> %a, %b71 %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b72 ret <8 x i16> %t273}74 75; CHECK-LABEL: t1076; CHECK: vmin.s16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}77define <8 x i16> @t10(<8 x i16> %a, <8 x i16> %b) {78 %t1 = icmp slt <8 x i16> %a, %b79 %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b80 ret <8 x i16> %t281}82 83; CHECK-LABEL: t1184; CHECK: vmax.u16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}85define <8 x i16> @t11(<8 x i16> %a, <8 x i16> %b) {86 %t1 = icmp ugt <8 x i16> %a, %b87 %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b88 ret <8 x i16> %t289}90 91; CHECK-LABEL: t1292; CHECK: vmin.u16 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}93define <8 x i16> @t12(<8 x i16> %a, <8 x i16> %b) {94 %t1 = icmp ult <8 x i16> %a, %b95 %t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b96 ret <8 x i16> %t297}98 99; CHECK-LABEL: t13100; CHECK: vmax.s16101define <4 x i16> @t13(<4 x i16> %a, <4 x i16> %b) {102 %t1 = icmp sgt <4 x i16> %a, %b103 %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b104 ret <4 x i16> %t2105}106 107; CHECK-LABEL: t14108; CHECK: vmin.s16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}109define <4 x i16> @t14(<4 x i16> %a, <4 x i16> %b) {110 %t1 = icmp slt <4 x i16> %a, %b111 %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b112 ret <4 x i16> %t2113}114 115; CHECK-LABEL: t15116; CHECK: vmax.u16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}117define <4 x i16> @t15(<4 x i16> %a, <4 x i16> %b) {118 %t1 = icmp ugt <4 x i16> %a, %b119 %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b120 ret <4 x i16> %t2121}122 123; CHECK-LABEL: t16124; CHECK: vmin.u16 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}125define <4 x i16> @t16(<4 x i16> %a, <4 x i16> %b) {126 %t1 = icmp ult <4 x i16> %a, %b127 %t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b128 ret <4 x i16> %t2129}130 131; CHECK-LABEL: t17132; CHECK: vmax.s8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}133define <16 x i8> @t17(<16 x i8> %a, <16 x i8> %b) {134 %t1 = icmp sgt <16 x i8> %a, %b135 %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b136 ret <16 x i8> %t2137}138 139; CHECK-LABEL: t18140; CHECK: vmin.s8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}141define <16 x i8> @t18(<16 x i8> %a, <16 x i8> %b) {142 %t1 = icmp slt <16 x i8> %a, %b143 %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b144 ret <16 x i8> %t2145}146 147; CHECK-LABEL: t19148; CHECK: vmax.u8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}149define <16 x i8> @t19(<16 x i8> %a, <16 x i8> %b) {150 %t1 = icmp ugt <16 x i8> %a, %b151 %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b152 ret <16 x i8> %t2153}154 155; CHECK-LABEL: t20156; CHECK: vmin.u8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}157define <16 x i8> @t20(<16 x i8> %a, <16 x i8> %b) {158 %t1 = icmp ult <16 x i8> %a, %b159 %t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b160 ret <16 x i8> %t2161}162 163; CHECK-LABEL: t21164; CHECK: vmax.s8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}165define <8 x i8> @t21(<8 x i8> %a, <8 x i8> %b) {166 %t1 = icmp sgt <8 x i8> %a, %b167 %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b168 ret <8 x i8> %t2169}170 171; CHECK-LABEL: t22172; CHECK: vmin.s8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}173define <8 x i8> @t22(<8 x i8> %a, <8 x i8> %b) {174 %t1 = icmp slt <8 x i8> %a, %b175 %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b176 ret <8 x i8> %t2177}178 179; CHECK-LABEL: t23180; CHECK: vmax.u8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}181define <8 x i8> @t23(<8 x i8> %a, <8 x i8> %b) {182 %t1 = icmp ugt <8 x i8> %a, %b183 %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b184 ret <8 x i8> %t2185}186 187; CHECK-LABEL: t24188; CHECK: vmin.u8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}189define <8 x i8> @t24(<8 x i8> %a, <8 x i8> %b) {190 %t1 = icmp ult <8 x i8> %a, %b191 %t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b192 ret <8 x i8> %t2193}194