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1; REQUIRES: asserts2; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a9 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \3; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A94; RUN: llc < %s -mtriple=arm-eabi -mcpu=swift -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \5; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT6; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \7; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R528; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-r52plus -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > \9; RUN: /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R5210;11; Check the latency of instructions for processors with sched-models12;13; Function Attrs: norecurse nounwind readnone14define i32 @foo(float %a, float %b, float %c, i32 %d) local_unnamed_addr #0 {15entry:16;17; CHECK: ********** MI Scheduling **********18; CHECK_A9: VADDS19; CHECK_SWIFT: VADDfd20; CHECK_R52: VADDS21; CHECK_A9: Latency : 522; CHECK_SWIFT: Latency : 423; CHECK_R52: Latency : 624;25; CHECK_A9: VMULS26; CHECK_SWIFT: VMULfd27; CHECK_R52: VMULS28; CHECK_SWIFT: Latency : 429; CHECK_A9: Latency : 630; CHECK_R52: Latency : 631;32; CHECK: VDIVS33; CHECK_SWIFT: Latency : 1734; CHECK_A9: Latency : 1635; CHECK_R52: Latency : 736;37; CHECK: VCVTDS38; CHECK_SWIFT: Latency : 439; CHECK_A9: Latency : 540; CHECK_R52: Latency : 641;42; CHECK: VADDD43; CHECK_SWIFT: Latency : 644; CHECK_A9: Latency : 545; CHECK_R52: Latency : 646;47; CHECK: VMULD48; CHECK_SWIFT: Latency : 649; CHECK_A9: Latency : 750; CHECK_R52: Latency : 651;52; CHECK: VDIVD53; CHECK_SWIFT: Latency : 3254; CHECK_A9: Latency : 2655; CHECK_R52: Latency : 1756;57; CHECK: VTOSIZD58; CHECK_SWIFT: Latency : 459; CHECK_A9: Latency : 560; CHECK_R52: Latency : 661;62 %add = fadd float %a, %b63 %mul = fmul float %add, %add64 %div = fdiv float %mul, %b65 %conv1 = fpext float %div to double66 %add3 = fadd double %conv1, %conv167 %mul4 = fmul double %add3, %add368 %div5 = fdiv double %mul4, %conv169 %conv6 = fptosi double %div5 to i3270 ret i32 %conv671}72