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1# Basic machine sched model test for Thumb2 int instructions2# RUN: llc -o /dev/null %s -mtriple=thumbv7-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \3# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT4# RUN: llc -o /dev/null %s -mtriple=thumbv7--eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \5# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A96# RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \7# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R528# RUN: llc -o /dev/null %s -mtriple=thumbv8r-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -verify-misched \9# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R5210# REQUIRES: asserts11--- |12 ; ModuleID = 'foo.ll'13 source_filename = "foo.ll"14 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"15 target triple = "thumbv7---eabi"16 17 @g1 = common global i32 0, align 418 @g2 = common global i32 0, align 419 20 define i64 @foo(i16 signext %a, i16 signext %b) {21 entry:22 %0 = load i32, ptr @g1, align 423 %1 = load i32, ptr @g2, align 424 %2 = add nuw nsw i32 %0, %025 %3 = sdiv i32 %2, %126 store i32 %3, ptr @g1, align 427 %d = mul nsw i16 %a, %a28 %e = mul nsw i16 %b, %b29 %f = add nuw nsw i16 %e, %d30 %c = zext i16 %f to i3231 %mul8 = mul nsw i32 %c, %332 %mul9 = mul nsw i32 %mul8, %mul833 %add10 = add nuw nsw i32 %mul9, %mul834 %conv1130 = zext i32 %add10 to i6435 %mul12 = mul nuw nsw i64 %conv1130, %conv113036 %mul13 = mul nsw i64 %mul12, %mul1237 %add14 = add nuw nsw i64 %mul13, %mul1238 ret i64 %add1439 }40#41# CHECK: ********** MI Scheduling **********42# CHECK: SU(2): %2:rgpr = t2MOVi32imm @g143# CHECK_A9: Latency : 244# CHECK_SWIFT: Latency : 245# CHECK_R52: Latency : 246#47# CHECK: SU(3): %3:rgpr = t2LDRi12 %2:rgpr, 0, 14, $noreg :: (dereferenceable load (s32) from @g1)48# CHECK_A9: Latency : 149# CHECK_SWIFT: Latency : 350# CHECK_R52: Latency : 451#52# CHECK: SU(6): %6:rgpr = t2ADDrr %3:rgpr, %3:rgpr, 14, $noreg, $noreg53# CHECK_A9: Latency : 154# CHECK_SWIFT: Latency : 155# CHECK_R52: Latency : 356 57# CHECK: SU(7): %7:rgpr = t2SDIV %6:rgpr, %5:rgpr, 14, $noreg58# CHECK_A9: Latency : 059# CHECK_SWIFT: Latency : 1460# CHECK_R52: Latency : 861 62# CHECK: SU(8): t2STRi12 %7:rgpr, %2:rgpr, 0, 14, $noreg :: (store (s32) into @g1)63# CHECK_A9: Latency : 164# CHECK_SWIFT: Latency : 065# CHECK_R52: Latency : 466#67# CHECK: SU(9): %8:rgpr = t2SMULBB %1:rgpr, %1:rgpr, 14, $noreg68# CHECK_A9: Latency : 269# CHECK_SWIFT: Latency : 470# CHECK_R52: Latency : 471#72# CHECK: SU(10): %9:rgpr = t2SMLABB %0:rgpr, %0:rgpr, %8:rgpr, 14, $noreg73# CHECK_A9: Latency : 274# CHECK_SWIFT: Latency : 475# CHECK_R52: Latency : 476#77# CHECK: SU(11): %10:rgpr = t2UXTH %9:rgpr, 0, 14, $noreg78# CHECK_A9: Latency : 179# CHECK_SWIFT: Latency : 180# CHECK_R52: Latency : 381#82# CHECK: SU(12): %11:rgpr = t2MUL %10:rgpr, %7:rgpr, 14, $noreg83# CHECK_A9: Latency : 284# CHECK_SWIFT: Latency : 485# CHECK_R52: Latency : 486#87# CHECK: SU(13): %12:rgpr = t2MLA %11:rgpr, %11:rgpr, %11:rgpr, 14, $noreg88# CHECK_A9: Latency : 289# CHECK_SWIFT: Latency : 490# CHECK_R52: Latency : 491#92# CHECK: SU(14): %13:rgpr, %14:rgpr = t2UMULL %12:rgpr, %12:rgpr, 14, $noreg93# CHECK_A9: Latency : 394# CHECK_SWIFT: Latency : 595# CHECK_R52: Latency : 496#97# CHECK: SU(18): %19:rgpr, %20:rgpr = t2UMLAL %12:rgpr, %12:rgpr, %19:rgpr(tied-def 0), %20:rgpr(tied-def 1), 14, $noreg98# CHECK_A9: Latency : 399# CHECK_SWIFT: Latency : 7100# CHECK_R52: Latency : 4101# CHECK: ** ScheduleDAGMILive::schedule picking next node102...103---104name: foo105alignment: 2106exposesReturnsTwice: false107legalized: false108regBankSelected: false109selected: false110tracksRegLiveness: true111registers:112 - { id: 0, class: rgpr }113 - { id: 1, class: rgpr }114 - { id: 2, class: rgpr }115 - { id: 3, class: rgpr }116 - { id: 4, class: rgpr }117 - { id: 5, class: rgpr }118 - { id: 6, class: rgpr }119 - { id: 7, class: rgpr }120 - { id: 8, class: rgpr }121 - { id: 9, class: rgpr }122 - { id: 10, class: rgpr }123 - { id: 11, class: rgpr }124 - { id: 12, class: rgpr }125 - { id: 13, class: rgpr }126 - { id: 14, class: rgpr }127 - { id: 15, class: rgpr }128 - { id: 16, class: rgpr }129 - { id: 17, class: rgpr }130 - { id: 18, class: rgpr }131 - { id: 19, class: rgpr }132 - { id: 20, class: rgpr }133liveins:134 - { reg: '$r0', virtual-reg: '%0' }135 - { reg: '$r1', virtual-reg: '%1' }136frameInfo:137 isFrameAddressTaken: false138 isReturnAddressTaken: false139 hasStackMap: false140 hasPatchPoint: false141 stackSize: 0142 offsetAdjustment: 0143 maxAlignment: 0144 adjustsStack: false145 hasCalls: false146 maxCallFrameSize: 0147 hasOpaqueSPAdjustment: false148 hasVAStart: false149 hasMustTailInVarArgFunc: false150body: |151 bb.0.entry:152 liveins: $r0, $r1153 154 %1 = COPY $r1155 %0 = COPY $r0156 %2 = t2MOVi32imm @g1157 %3 = t2LDRi12 %2, 0, 14, $noreg :: (dereferenceable load (s32) from @g1)158 %4 = t2MOVi32imm @g2159 %5 = t2LDRi12 %4, 0, 14, $noreg :: (dereferenceable load (s32) from @g2)160 %6 = t2ADDrr %3, %3, 14, $noreg, $noreg161 %7 = t2SDIV %6, %5, 14, $noreg162 t2STRi12 %7, %2, 0, 14, $noreg :: (store (s32) into @g1)163 %8 = t2SMULBB %1, %1, 14, $noreg164 %9 = t2SMLABB %0, %0, %8, 14, $noreg165 %10 = t2UXTH %9, 0, 14, $noreg166 %11 = t2MUL %10, %7, 14, $noreg167 %12 = t2MLA %11, %11, %11, 14, $noreg168 %13, %14 = t2UMULL %12, %12, 14, $noreg169 %19, %16 = t2UMULL %13, %13, 14, $noreg170 %17 = t2MLA %13, %14, %16, 14, $noreg171 %20 = t2MLA %13, %14, %17, 14, $noreg172 %19, %20 = t2UMLAL %12, %12, %19, %20, 14, $noreg173 $r0 = COPY %19174 $r1 = COPY %20175 tBX_RET 14, $noreg, implicit $r0, implicit $r1176 177...178