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1# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=swift -run-pass machine-scheduler -enable-misched -verify-misched \2# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_SWIFT3# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-a9 -run-pass machine-scheduler -enable-misched -verify-misched \4# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_A95# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52 -run-pass machine-scheduler -enable-misched -verify-misched \6# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R527# RUN: llc -o /dev/null %s -mtriple=arm-eabi -mcpu=cortex-r52plus -run-pass machine-scheduler -enable-misched -verify-misched \8# RUN: -debug-only=machine-scheduler 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK_R529# REQUIRES: asserts10--- |11 ; ModuleID = 'foo.ll'12 source_filename = "foo.ll"13 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"14 target triple = "arm---eabi"15 16 define i64 @foo(i16 signext %a, i16 signext %b) {17 entry:18 %d = mul nsw i16 %a, %a19 %e = mul nsw i16 %b, %b20 %f = add nuw nsw i16 %e, %d21 %c = zext i16 %f to i3222 %mul8 = mul nsw i32 %c, %c23 %mul9 = mul nsw i32 %mul8, %mul824 %add10 = add nuw nsw i32 %mul9, %mul825 %conv1130 = zext i32 %add10 to i6426 %mul12 = mul nuw nsw i64 %conv1130, %conv113027 %mul13 = mul nsw i64 %mul12, %mul1228 %add14 = add nuw nsw i64 %mul13, %mul1229 ret i64 %add1430 }31 32# CHECK: ********** MI Scheduling **********33# CHECK: SU(2): %2:gpr = SMULBB %1:gpr, %1:gpr, 14, $noreg34# CHECK_A9: Latency : 235# CHECK_SWIFT: Latency : 436# CHECK_R52: Latency : 437#38# CHECK: SU(3): %3:gprnopc = SMLABB %0:gprnopc, %0:gprnopc, %2:gpr, 14, $noreg39# CHECK_A9: Latency : 240# CHECK_SWIFT: Latency : 441# CHECK_R52: Latency : 442#43# CHECK: SU(4): %4:gprnopc = UXTH %3:gprnopc, 0, 14, $noreg44# CHECK_A9: Latency : 145# CHECK_SWIFT: Latency : 146# CHECK_R52: Latency : 347#48# CHECK: SU(5): %5:gprnopc = MUL %4:gprnopc, %4:gprnopc, 14, $noreg, $noreg49# CHECK_A9: Latency : 250# CHECK_SWIFT: Latency : 451# CHECK_R52: Latency : 452#53# CHECK: SU(6): %6:gprnopc = MLA %5:gprnopc, %5:gprnopc, %5:gprnopc, 14, $noreg, $noreg54# CHECK_A9: Latency : 255# CHECK_SWIFT: Latency : 456# CHECK_R52: Latency : 457#58# CHECK: SU(7): %7:gprnopc, %8:gprnopc = UMULL %6:gprnopc, %6:gprnopc, 14, $noreg, $noreg59# CHECK_A9: Latency : 360# CHECK_SWIFT: Latency : 561# CHECK_R52: Latency : 462#63# CHECK: SU(11): %13:gpr, %14:gprnopc = UMLAL %6:gprnopc, %6:gprnopc, %13:gpr(tied-def 0), %14:gprnopc(tied-def 1), 14, $noreg, $noreg64# CHECK_SWIFT: Latency : 765# CHECK_A9: Latency : 366# CHECK_R52: Latency : 467# CHECK: ** ScheduleDAGMILive::schedule picking next node68...69---70name: foo71alignment: 472exposesReturnsTwice: false73legalized: false74regBankSelected: false75selected: false76tracksRegLiveness: true77registers:78 - { id: 0, class: gprnopc }79 - { id: 1, class: gpr }80 - { id: 2, class: gpr }81 - { id: 3, class: gprnopc }82 - { id: 4, class: gprnopc }83 - { id: 5, class: gprnopc }84 - { id: 6, class: gprnopc }85 - { id: 7, class: gprnopc }86 - { id: 8, class: gprnopc }87 - { id: 9, class: gpr }88 - { id: 10, class: gprnopc }89 - { id: 11, class: gprnopc }90 - { id: 12, class: gprnopc }91 - { id: 13, class: gpr }92 - { id: 14, class: gprnopc }93liveins:94 - { reg: '$r0', virtual-reg: '%0' }95 - { reg: '$r1', virtual-reg: '%1' }96frameInfo:97 isFrameAddressTaken: false98 isReturnAddressTaken: false99 hasStackMap: false100 hasPatchPoint: false101 stackSize: 0102 offsetAdjustment: 0103 maxAlignment: 0104 adjustsStack: false105 hasCalls: false106 maxCallFrameSize: 0107 hasOpaqueSPAdjustment: false108 hasVAStart: false109 hasMustTailInVarArgFunc: false110body: |111 bb.0.entry:112 liveins: $r0, $r1113 114 %1 = COPY $r1115 %0 = COPY $r0116 %2 = SMULBB %1, %1, 14, $noreg117 %3 = SMLABB %0, %0, %2, 14, $noreg118 %4 = UXTH %3, 0, 14, $noreg119 %5 = MUL %4, %4, 14, $noreg, $noreg120 %6 = MLA %5, %5, %5, 14, $noreg, $noreg121 %7, %8 = UMULL %6, %6, 14, $noreg, $noreg122 %13, %10 = UMULL %7, %7, 14, $noreg, $noreg123 %11 = MLA %7, %8, %10, 14, $noreg, $noreg124 %14 = MLA %7, %8, %11, 14, $noreg, $noreg125 %13, %14 = UMLAL %6, %6, %13, %14, 14, $noreg, $noreg126 $r0 = COPY %13127 $r1 = COPY %14128 BX_RET 14, $noreg, implicit $r0, implicit $r1129 130...131