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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s3 4# Make sure the MOVCC to conditional instruction peephole doesn't change the5# register class to one that's invalid.6 7--- |8 target triple = "armv7-unknown-unknown"9 define i32 @test(i32 %x, i32 %y) {10 ret i32 undef11 }12...13---14name: test15tracksRegLiveness: true16body: |17 bb.0 (%ir-block.0):18 liveins: $r0, $r119 ; CHECK-LABEL: name: test20 ; CHECK: liveins: $r0, $r121 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r022 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $r123 ; CHECK-NEXT: [[MOVsi:%[0-9]+]]:gpr = MOVsi [[COPY1]], 27, 14 /* CC::al */, $noreg, $noreg24 ; CHECK-NEXT: [[ORRrsi:%[0-9]+]]:gpr = ORRrsi [[MOVsi]], [[COPY1]], 234, 14 /* CC::al */, $noreg, $noreg25 ; CHECK-NEXT: [[MOVsi1:%[0-9]+]]:gpr = MOVsi [[COPY1]], 155, 14 /* CC::al */, $noreg, $noreg26 ; CHECK-NEXT: [[ORRrsi1:%[0-9]+]]:gprnopc = ORRrsi killed [[MOVsi1]], killed [[MOVsi]], 106, 14 /* CC::al */, $noreg, $noreg27 ; CHECK-NEXT: TSTri [[COPY1]], 1, 14 /* CC::al */, $noreg, implicit-def $cpsr28 ; CHECK-NEXT: [[UXTH:%[0-9]+]]:gprnopc = UXTH killed [[ORRrsi1]], 0, 0 /* CC::eq */, $cpsr, implicit [[ORRrsi]](tied-def 0)29 ; CHECK-NEXT: $r0 = COPY killed [[UXTH]]30 ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r031 %0:gpr = COPY $r032 %1:gpr = COPY $r133 %2:gpr = MOVsi %1:gpr, 27, 14, $noreg, $noreg34 %3:gpr = ORRrsi %2:gpr, %1:gpr, 234, 14, $noreg, $noreg35 %4:gpr = MOVsi %1:gpr, 155, 14, $noreg, $noreg36 %5:gprnopc = ORRrsi killed %4:gpr, killed %2:gpr, 106, 14, $noreg, $noreg37 %6:gprnopc = UXTH killed %5:gprnopc, 0, 14, $noreg38 TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr39 %7:gpr = MOVCCr %3:gpr, killed %6:gprnopc, 0, $cpsr40 $r0 = COPY killed %741 BX_RET 14, $noreg, implicit $r042