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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=armv7a-none-eabihf -mattr=+neon -verify-machineinstrs | FileCheck %s3 4define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {5; CHECK-LABEL: ins16bw:6; CHECK: @ %bb.0:7; CHECK-NEXT: vmov.8 d1[7], r08; CHECK-NEXT: bx lr9 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 1510 ret <16 x i8> %tmp311}12 13define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {14; CHECK-LABEL: ins8hw:15; CHECK: @ %bb.0:16; CHECK-NEXT: vmov.16 d1[2], r017; CHECK-NEXT: bx lr18 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 619 ret <8 x i16> %tmp320}21 22define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {23; CHECK-LABEL: ins4sw:24; CHECK: @ %bb.0:25; CHECK-NEXT: vmov.32 d1[0], r026; CHECK-NEXT: bx lr27 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 228 ret <4 x i32> %tmp329}30 31define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {32; CHECK-LABEL: ins2dw:33; CHECK: @ %bb.0:34; CHECK-NEXT: vmov.32 d1[0], r035; CHECK-NEXT: vmov.32 d1[1], r136; CHECK-NEXT: bx lr37 %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 138 ret <2 x i64> %tmp339}40 41define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {42; CHECK-LABEL: ins8bw:43; CHECK: @ %bb.0:44; CHECK-NEXT: vmov.8 d0[5], r045; CHECK-NEXT: bx lr46 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 547 ret <8 x i8> %tmp348}49 50define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {51; CHECK-LABEL: ins4hw:52; CHECK: @ %bb.0:53; CHECK-NEXT: vmov.16 d0[3], r054; CHECK-NEXT: bx lr55 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 356 ret <4 x i16> %tmp357}58 59define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {60; CHECK-LABEL: ins2sw:61; CHECK: @ %bb.0:62; CHECK-NEXT: vmov.32 d0[1], r063; CHECK-NEXT: bx lr64 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 165 ret <2 x i32> %tmp366}67 68define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {69; CHECK-LABEL: ins16b16:70; CHECK: @ %bb.0:71; CHECK-NEXT: vmov.u8 r0, d0[2]72; CHECK-NEXT: vmov.8 d3[7], r073; CHECK-NEXT: vorr q0, q1, q174; CHECK-NEXT: bx lr75 %tmp3 = extractelement <16 x i8> %tmp1, i32 276 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 1577 ret <16 x i8> %tmp478}79 80define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {81; CHECK-LABEL: ins8h8:82; CHECK: @ %bb.0:83; CHECK-NEXT: vmov.u16 r0, d0[2]84; CHECK-NEXT: vmov.16 d3[3], r085; CHECK-NEXT: vorr q0, q1, q186; CHECK-NEXT: bx lr87 %tmp3 = extractelement <8 x i16> %tmp1, i32 288 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 789 ret <8 x i16> %tmp490}91 92define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {93; CHECK-LABEL: ins4s4:94; CHECK: @ %bb.0:95; CHECK-NEXT: vmov.32 r0, d1[0]96; CHECK-NEXT: vmov.32 d2[1], r097; CHECK-NEXT: vorr q0, q1, q198; CHECK-NEXT: bx lr99 %tmp3 = extractelement <4 x i32> %tmp1, i32 2100 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1101 ret <4 x i32> %tmp4102}103 104define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {105; CHECK-LABEL: ins2d2:106; CHECK: @ %bb.0:107; CHECK-NEXT: vmov r0, r1, d0108; CHECK-NEXT: vmov.32 d3[0], r0109; CHECK-NEXT: vmov.32 d3[1], r1110; CHECK-NEXT: vorr q0, q1, q1111; CHECK-NEXT: bx lr112 %tmp3 = extractelement <2 x i64> %tmp1, i32 0113 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1114 ret <2 x i64> %tmp4115}116 117define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {118; CHECK-LABEL: ins4f4:119; CHECK: @ %bb.0:120; CHECK-NEXT: vmov.f32 s5, s2121; CHECK-NEXT: vorr q0, q1, q1122; CHECK-NEXT: bx lr123 %tmp3 = extractelement <4 x float> %tmp1, i32 2124 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1125 ret <4 x float> %tmp4126}127 128define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {129; CHECK-LABEL: ins2df2:130; CHECK: @ %bb.0:131; CHECK-NEXT: vorr d3, d0, d0132; CHECK-NEXT: vorr q0, q1, q1133; CHECK-NEXT: bx lr134 %tmp3 = extractelement <2 x double> %tmp1, i32 0135 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1136 ret <2 x double> %tmp4137}138 139define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {140; CHECK-LABEL: ins8b16:141; CHECK: @ %bb.0:142; CHECK-NEXT: vmov.u8 r0, d0[2]143; CHECK-NEXT: vmov.8 d3[7], r0144; CHECK-NEXT: vorr q0, q1, q1145; CHECK-NEXT: bx lr146 %tmp3 = extractelement <8 x i8> %tmp1, i32 2147 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15148 ret <16 x i8> %tmp4149}150 151define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {152; CHECK-LABEL: ins4h8:153; CHECK: @ %bb.0:154; CHECK-NEXT: vmov.u16 r0, d0[2]155; CHECK-NEXT: vmov.16 d3[3], r0156; CHECK-NEXT: vorr q0, q1, q1157; CHECK-NEXT: bx lr158 %tmp3 = extractelement <4 x i16> %tmp1, i32 2159 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7160 ret <8 x i16> %tmp4161}162 163define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {164; CHECK-LABEL: ins2s4:165; CHECK: @ %bb.0:166; CHECK-NEXT: vmov.32 r0, d0[1]167; CHECK-NEXT: vmov.32 d2[1], r0168; CHECK-NEXT: vorr q0, q1, q1169; CHECK-NEXT: bx lr170 %tmp3 = extractelement <2 x i32> %tmp1, i32 1171 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1172 ret <4 x i32> %tmp4173}174 175define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {176; CHECK-LABEL: ins1d2:177; CHECK: @ %bb.0:178; CHECK-NEXT: vmov.32 r0, d0[0]179; CHECK-NEXT: vmov.32 r1, d0[1]180; CHECK-NEXT: vmov.32 d3[0], r0181; CHECK-NEXT: vmov.32 d3[1], r1182; CHECK-NEXT: vorr q0, q1, q1183; CHECK-NEXT: bx lr184 %tmp3 = extractelement <1 x i64> %tmp1, i32 0185 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1186 ret <2 x i64> %tmp4187}188 189define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {190; CHECK-LABEL: ins2f4:191; CHECK: @ %bb.0:192; CHECK-NEXT: vmov.f32 s5, s1193; CHECK-NEXT: vorr q0, q1, q1194; CHECK-NEXT: bx lr195 %tmp3 = extractelement <2 x float> %tmp1, i32 1196 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1197 ret <4 x float> %tmp4198}199 200define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {201; CHECK-LABEL: ins1f2:202; CHECK: @ %bb.0:203; CHECK-NEXT: vorr d3, d0, d0204; CHECK-NEXT: vorr q0, q1, q1205; CHECK-NEXT: bx lr206 %tmp3 = extractelement <1 x double> %tmp1, i32 0207 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1208 ret <2 x double> %tmp4209}210 211define <2 x double> @ins1f2_args_flipped(<2 x double> %tmp2, <1 x double> %tmp1) {212; CHECK-LABEL: ins1f2_args_flipped:213; CHECK: @ %bb.0:214; CHECK-NEXT: vmov.f64 d1, d2215; CHECK-NEXT: bx lr216 %tmp3 = extractelement <1 x double> %tmp1, i32 0217 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1218 ret <2 x double> %tmp4219}220 221define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {222; CHECK-LABEL: ins16b8:223; CHECK: @ %bb.0:224; CHECK-NEXT: vmov.u8 r0, d0[2]225; CHECK-NEXT: vmov.8 d2[7], r0226; CHECK-NEXT: vorr d0, d2, d2227; CHECK-NEXT: bx lr228 %tmp3 = extractelement <16 x i8> %tmp1, i32 2229 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7230 ret <8 x i8> %tmp4231}232 233define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {234; CHECK-LABEL: ins8h4:235; CHECK: @ %bb.0:236; CHECK-NEXT: vmov.u16 r0, d0[2]237; CHECK-NEXT: vmov.16 d2[3], r0238; CHECK-NEXT: vorr d0, d2, d2239; CHECK-NEXT: bx lr240 %tmp3 = extractelement <8 x i16> %tmp1, i32 2241 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3242 ret <4 x i16> %tmp4243}244 245define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {246; CHECK-LABEL: ins4s2:247; CHECK: @ %bb.0:248; CHECK-NEXT: vmov.32 r0, d1[0]249; CHECK-NEXT: vmov.32 d2[1], r0250; CHECK-NEXT: vorr d0, d2, d2251; CHECK-NEXT: bx lr252 %tmp3 = extractelement <4 x i32> %tmp1, i32 2253 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1254 ret <2 x i32> %tmp4255}256 257define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {258; CHECK-LABEL: ins2d1:259; CHECK: @ %bb.0:260; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0261; CHECK-NEXT: bx lr262 %tmp3 = extractelement <2 x i64> %tmp1, i32 0263 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0264 ret <1 x i64> %tmp4265}266 267define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {268; CHECK-LABEL: ins4f2:269; CHECK: @ %bb.0:270; CHECK-NEXT: vmov.f32 s5, s2271; CHECK-NEXT: vmov.f64 d0, d2272; CHECK-NEXT: bx lr273 %tmp3 = extractelement <4 x float> %tmp1, i32 2274 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1275 ret <2 x float> %tmp4276}277 278define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {279; CHECK-LABEL: ins2f1:280; CHECK: @ %bb.0:281; CHECK-NEXT: vmov.f64 d0, d1282; CHECK-NEXT: bx lr283 %tmp3 = extractelement <2 x double> %tmp1, i32 1284 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0285 ret <1 x double> %tmp4286}287 288define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {289; CHECK-LABEL: ins8b8:290; CHECK: @ %bb.0:291; CHECK-NEXT: vmov.u8 r0, d0[2]292; CHECK-NEXT: vmov.8 d1[4], r0293; CHECK-NEXT: vorr d0, d1, d1294; CHECK-NEXT: bx lr295 %tmp3 = extractelement <8 x i8> %tmp1, i32 2296 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4297 ret <8 x i8> %tmp4298}299 300define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {301; CHECK-LABEL: ins4h4:302; CHECK: @ %bb.0:303; CHECK-NEXT: vmov.u16 r0, d0[2]304; CHECK-NEXT: vmov.16 d1[3], r0305; CHECK-NEXT: vorr d0, d1, d1306; CHECK-NEXT: bx lr307 %tmp3 = extractelement <4 x i16> %tmp1, i32 2308 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3309 ret <4 x i16> %tmp4310}311 312define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {313; CHECK-LABEL: ins2s2:314; CHECK: @ %bb.0:315; CHECK-NEXT: vmov.32 r0, d0[0]316; CHECK-NEXT: vmov.32 d1[1], r0317; CHECK-NEXT: vorr d0, d1, d1318; CHECK-NEXT: bx lr319 %tmp3 = extractelement <2 x i32> %tmp1, i32 0320 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1321 ret <2 x i32> %tmp4322}323 324define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {325; CHECK-LABEL: ins1d1:326; CHECK: @ %bb.0:327; CHECK-NEXT: bx lr328 %tmp3 = extractelement <1 x i64> %tmp1, i32 0329 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0330 ret <1 x i64> %tmp4331}332 333define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {334; CHECK-LABEL: ins2f2:335; CHECK: @ %bb.0:336; CHECK-NEXT: vmov.f32 s3, s0337; CHECK-NEXT: vmov.f64 d0, d1338; CHECK-NEXT: bx lr339 %tmp3 = extractelement <2 x float> %tmp1, i32 0340 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1341 ret <2 x float> %tmp4342}343 344define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {345; CHECK-LABEL: ins1df1:346; CHECK: @ %bb.0:347; CHECK-NEXT: bx lr348 %tmp3 = extractelement <1 x double> %tmp1, i32 0349 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0350 ret <1 x double> %tmp4351}352 353define i32 @umovw16b(<16 x i8> %tmp1) {354; CHECK-LABEL: umovw16b:355; CHECK: @ %bb.0:356; CHECK-NEXT: vmov.u8 r0, d1[0]357; CHECK-NEXT: bx lr358 %tmp3 = extractelement <16 x i8> %tmp1, i32 8359 %tmp4 = zext i8 %tmp3 to i32360 ret i32 %tmp4361}362 363define i32 @umovw8h(<8 x i16> %tmp1) {364; CHECK-LABEL: umovw8h:365; CHECK: @ %bb.0:366; CHECK-NEXT: vmov.u16 r0, d0[2]367; CHECK-NEXT: bx lr368 %tmp3 = extractelement <8 x i16> %tmp1, i32 2369 %tmp4 = zext i16 %tmp3 to i32370 ret i32 %tmp4371}372 373define i32 @umovw4s(<4 x i32> %tmp1) {374; CHECK-LABEL: umovw4s:375; CHECK: @ %bb.0:376; CHECK-NEXT: vmov.32 r0, d1[0]377; CHECK-NEXT: bx lr378 %tmp3 = extractelement <4 x i32> %tmp1, i32 2379 ret i32 %tmp3380}381 382define i64 @umovx2d(<2 x i64> %tmp1) {383; CHECK-LABEL: umovx2d:384; CHECK: @ %bb.0:385; CHECK-NEXT: vmov r0, r1, d1386; CHECK-NEXT: bx lr387 %tmp3 = extractelement <2 x i64> %tmp1, i32 1388 ret i64 %tmp3389}390 391define i32 @umovw8b(<8 x i8> %tmp1) {392; CHECK-LABEL: umovw8b:393; CHECK: @ %bb.0:394; CHECK-NEXT: vmov.u8 r0, d0[7]395; CHECK-NEXT: bx lr396 %tmp3 = extractelement <8 x i8> %tmp1, i32 7397 %tmp4 = zext i8 %tmp3 to i32398 ret i32 %tmp4399}400 401define i32 @umovw4h(<4 x i16> %tmp1) {402; CHECK-LABEL: umovw4h:403; CHECK: @ %bb.0:404; CHECK-NEXT: vmov.u16 r0, d0[2]405; CHECK-NEXT: bx lr406 %tmp3 = extractelement <4 x i16> %tmp1, i32 2407 %tmp4 = zext i16 %tmp3 to i32408 ret i32 %tmp4409}410 411define i32 @umovw2s(<2 x i32> %tmp1) {412; CHECK-LABEL: umovw2s:413; CHECK: @ %bb.0:414; CHECK-NEXT: vmov.32 r0, d0[1]415; CHECK-NEXT: bx lr416 %tmp3 = extractelement <2 x i32> %tmp1, i32 1417 ret i32 %tmp3418}419 420define i64 @umovx1d(<1 x i64> %tmp1) {421; CHECK-LABEL: umovx1d:422; CHECK: @ %bb.0:423; CHECK-NEXT: vmov.32 r0, d0[0]424; CHECK-NEXT: vmov.32 r1, d0[1]425; CHECK-NEXT: bx lr426 %tmp3 = extractelement <1 x i64> %tmp1, i32 0427 ret i64 %tmp3428}429 430define i32 @smovw16b(<16 x i8> %tmp1) {431; CHECK-LABEL: smovw16b:432; CHECK: @ %bb.0:433; CHECK-NEXT: vmov.s8 r0, d1[0]434; CHECK-NEXT: add r0, r0, r0435; CHECK-NEXT: bx lr436 %tmp3 = extractelement <16 x i8> %tmp1, i32 8437 %tmp4 = sext i8 %tmp3 to i32438 %tmp5 = add i32 %tmp4, %tmp4439 ret i32 %tmp5440}441 442define i32 @smovw8h(<8 x i16> %tmp1) {443; CHECK-LABEL: smovw8h:444; CHECK: @ %bb.0:445; CHECK-NEXT: vmov.s16 r0, d0[2]446; CHECK-NEXT: add r0, r0, r0447; CHECK-NEXT: bx lr448 %tmp3 = extractelement <8 x i16> %tmp1, i32 2449 %tmp4 = sext i16 %tmp3 to i32450 %tmp5 = add i32 %tmp4, %tmp4451 ret i32 %tmp5452}453 454define i64 @smovx16b(<16 x i8> %tmp1) {455; CHECK-LABEL: smovx16b:456; CHECK: @ %bb.0:457; CHECK-NEXT: vmov.s8 r0, d1[0]458; CHECK-NEXT: asr r1, r0, #31459; CHECK-NEXT: bx lr460 %tmp3 = extractelement <16 x i8> %tmp1, i32 8461 %tmp4 = sext i8 %tmp3 to i64462 ret i64 %tmp4463}464 465define i64 @smovx8h(<8 x i16> %tmp1) {466; CHECK-LABEL: smovx8h:467; CHECK: @ %bb.0:468; CHECK-NEXT: vmov.s16 r0, d0[2]469; CHECK-NEXT: asr r1, r0, #31470; CHECK-NEXT: bx lr471 %tmp3 = extractelement <8 x i16> %tmp1, i32 2472 %tmp4 = sext i16 %tmp3 to i64473 ret i64 %tmp4474}475 476define i64 @smovx4s(<4 x i32> %tmp1) {477; CHECK-LABEL: smovx4s:478; CHECK: @ %bb.0:479; CHECK-NEXT: vmov.32 r0, d1[0]480; CHECK-NEXT: asr r1, r0, #31481; CHECK-NEXT: bx lr482 %tmp3 = extractelement <4 x i32> %tmp1, i32 2483 %tmp4 = sext i32 %tmp3 to i64484 ret i64 %tmp4485}486 487define i32 @smovw8b(<8 x i8> %tmp1) {488; CHECK-LABEL: smovw8b:489; CHECK: @ %bb.0:490; CHECK-NEXT: vmov.s8 r0, d0[4]491; CHECK-NEXT: add r0, r0, r0492; CHECK-NEXT: bx lr493 %tmp3 = extractelement <8 x i8> %tmp1, i32 4494 %tmp4 = sext i8 %tmp3 to i32495 %tmp5 = add i32 %tmp4, %tmp4496 ret i32 %tmp5497}498 499define i32 @smovw4h(<4 x i16> %tmp1) {500; CHECK-LABEL: smovw4h:501; CHECK: @ %bb.0:502; CHECK-NEXT: vmov.s16 r0, d0[2]503; CHECK-NEXT: add r0, r0, r0504; CHECK-NEXT: bx lr505 %tmp3 = extractelement <4 x i16> %tmp1, i32 2506 %tmp4 = sext i16 %tmp3 to i32507 %tmp5 = add i32 %tmp4, %tmp4508 ret i32 %tmp5509}510 511define i32 @smovx8b(<8 x i8> %tmp1) {512; CHECK-LABEL: smovx8b:513; CHECK: @ %bb.0:514; CHECK-NEXT: vmov.s8 r0, d0[6]515; CHECK-NEXT: bx lr516 %tmp3 = extractelement <8 x i8> %tmp1, i32 6517 %tmp4 = sext i8 %tmp3 to i32518 ret i32 %tmp4519}520 521define i32 @smovx4h(<4 x i16> %tmp1) {522; CHECK-LABEL: smovx4h:523; CHECK: @ %bb.0:524; CHECK-NEXT: vmov.s16 r0, d0[2]525; CHECK-NEXT: bx lr526 %tmp3 = extractelement <4 x i16> %tmp1, i32 2527 %tmp4 = sext i16 %tmp3 to i32528 ret i32 %tmp4529}530 531define i64 @smovx2s(<2 x i32> %tmp1) {532; CHECK-LABEL: smovx2s:533; CHECK: @ %bb.0:534; CHECK-NEXT: vmov.32 r0, d0[1]535; CHECK-NEXT: asr r1, r0, #31536; CHECK-NEXT: bx lr537 %tmp3 = extractelement <2 x i32> %tmp1, i32 1538 %tmp4 = sext i32 %tmp3 to i64539 ret i64 %tmp4540}541 542define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {543; CHECK-LABEL: test_vcopy_lane_s8:544; CHECK: @ %bb.0:545; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0546; CHECK-NEXT: vldr d16, .LCPI50_0547; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0548; CHECK-NEXT: vtbl.8 d0, {d0, d1}, d16549; CHECK-NEXT: bx lr550; CHECK-NEXT: .p2align 3551; CHECK-NEXT: @ %bb.1:552; CHECK-NEXT: .LCPI50_0:553; CHECK-NEXT: .byte 0 @ 0x0554; CHECK-NEXT: .byte 1 @ 0x1555; CHECK-NEXT: .byte 2 @ 0x2556; CHECK-NEXT: .byte 3 @ 0x3557; CHECK-NEXT: .byte 4 @ 0x4558; CHECK-NEXT: .byte 11 @ 0xb559; CHECK-NEXT: .byte 6 @ 0x6560; CHECK-NEXT: .byte 7 @ 0x7561 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>562 ret <8 x i8> %vset_lane563}564 565define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {566; CHECK-LABEL: test_vcopyq_laneq_s8:567; CHECK: @ %bb.0:568; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1569; CHECK-NEXT: vldr d16, .LCPI51_0570; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1571; CHECK-NEXT: vtbl.8 d1, {d1, d2}, d16572; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1573; CHECK-NEXT: bx lr574; CHECK-NEXT: .p2align 3575; CHECK-NEXT: @ %bb.1:576; CHECK-NEXT: .LCPI51_0:577; CHECK-NEXT: .byte 0 @ 0x0578; CHECK-NEXT: .byte 1 @ 0x1579; CHECK-NEXT: .byte 2 @ 0x2580; CHECK-NEXT: .byte 3 @ 0x3581; CHECK-NEXT: .byte 4 @ 0x4582; CHECK-NEXT: .byte 5 @ 0x5583; CHECK-NEXT: .byte 14 @ 0xe584; CHECK-NEXT: .byte 7 @ 0x7585 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15>586 ret <16 x i8> %vset_lane587}588 589define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {590; CHECK-LABEL: test_vcopy_lane_swap_s8:591; CHECK: @ %bb.0:592; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q0593; CHECK-NEXT: vldr d16, .LCPI52_0594; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q0595; CHECK-NEXT: vtbl.8 d0, {d0, d1}, d16596; CHECK-NEXT: bx lr597; CHECK-NEXT: .p2align 3598; CHECK-NEXT: @ %bb.1:599; CHECK-NEXT: .LCPI52_0:600; CHECK-NEXT: .byte 8 @ 0x8601; CHECK-NEXT: .byte 9 @ 0x9602; CHECK-NEXT: .byte 10 @ 0xa603; CHECK-NEXT: .byte 11 @ 0xb604; CHECK-NEXT: .byte 12 @ 0xc605; CHECK-NEXT: .byte 13 @ 0xd606; CHECK-NEXT: .byte 14 @ 0xe607; CHECK-NEXT: .byte 0 @ 0x0608 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>609 ret <8 x i8> %vset_lane610}611 612define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {613; CHECK-LABEL: test_vcopyq_laneq_swap_s8:614; CHECK: @ %bb.0:615; CHECK-NEXT: @ kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1616; CHECK-NEXT: vldr d16, .LCPI53_0617; CHECK-NEXT: @ kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1618; CHECK-NEXT: vtbl.8 d2, {d1, d2}, d16619; CHECK-NEXT: vorr q0, q1, q1620; CHECK-NEXT: bx lr621; CHECK-NEXT: .p2align 3622; CHECK-NEXT: @ %bb.1:623; CHECK-NEXT: .LCPI53_0:624; CHECK-NEXT: .byte 7 @ 0x7625; CHECK-NEXT: .byte 9 @ 0x9626; CHECK-NEXT: .byte 10 @ 0xa627; CHECK-NEXT: .byte 11 @ 0xb628; CHECK-NEXT: .byte 12 @ 0xc629; CHECK-NEXT: .byte 13 @ 0xd630; CHECK-NEXT: .byte 14 @ 0xe631; CHECK-NEXT: .byte 15 @ 0xf632 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>633 ret <16 x i8> %vset_lane634}635 636define <8 x i8> @test_vdup_n_u8(i8 %v1) #0 {637; CHECK-LABEL: test_vdup_n_u8:638; CHECK: @ %bb.0:639; CHECK-NEXT: vdup.8 d0, r0640; CHECK-NEXT: bx lr641 %vecinit.i = insertelement <8 x i8> undef, i8 %v1, i32 0642 %vecinit1.i = insertelement <8 x i8> %vecinit.i, i8 %v1, i32 1643 %vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 %v1, i32 2644 %vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 %v1, i32 3645 %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 %v1, i32 4646 %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 %v1, i32 5647 %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 %v1, i32 6648 %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 %v1, i32 7649 ret <8 x i8> %vecinit7.i650}651 652define <4 x i16> @test_vdup_n_u16(i16 %v1) #0 {653; CHECK-LABEL: test_vdup_n_u16:654; CHECK: @ %bb.0:655; CHECK-NEXT: vdup.16 d0, r0656; CHECK-NEXT: bx lr657 %vecinit.i = insertelement <4 x i16> undef, i16 %v1, i32 0658 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %v1, i32 1659 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %v1, i32 2660 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %v1, i32 3661 ret <4 x i16> %vecinit3.i662}663 664define <2 x i32> @test_vdup_n_u32(i32 %v1) #0 {665; CHECK-LABEL: test_vdup_n_u32:666; CHECK: @ %bb.0:667; CHECK-NEXT: vdup.32 d0, r0668; CHECK-NEXT: bx lr669 %vecinit.i = insertelement <2 x i32> undef, i32 %v1, i32 0670 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %v1, i32 1671 ret <2 x i32> %vecinit1.i672}673 674define <1 x i64> @test_vdup_n_u64(i64 %v1) #0 {675; CHECK-LABEL: test_vdup_n_u64:676; CHECK: @ %bb.0:677; CHECK-NEXT: vmov.32 d0[0], r0678; CHECK-NEXT: vmov.32 d0[1], r1679; CHECK-NEXT: bx lr680 %vecinit.i = insertelement <1 x i64> undef, i64 %v1, i32 0681 ret <1 x i64> %vecinit.i682}683 684define <16 x i8> @test_vdupq_n_u8(i8 %v1) #0 {685; CHECK-LABEL: test_vdupq_n_u8:686; CHECK: @ %bb.0:687; CHECK-NEXT: vdup.8 q0, r0688; CHECK-NEXT: bx lr689 %vecinit.i = insertelement <16 x i8> undef, i8 %v1, i32 0690 %vecinit1.i = insertelement <16 x i8> %vecinit.i, i8 %v1, i32 1691 %vecinit2.i = insertelement <16 x i8> %vecinit1.i, i8 %v1, i32 2692 %vecinit3.i = insertelement <16 x i8> %vecinit2.i, i8 %v1, i32 3693 %vecinit4.i = insertelement <16 x i8> %vecinit3.i, i8 %v1, i32 4694 %vecinit5.i = insertelement <16 x i8> %vecinit4.i, i8 %v1, i32 5695 %vecinit6.i = insertelement <16 x i8> %vecinit5.i, i8 %v1, i32 6696 %vecinit7.i = insertelement <16 x i8> %vecinit6.i, i8 %v1, i32 7697 %vecinit8.i = insertelement <16 x i8> %vecinit7.i, i8 %v1, i32 8698 %vecinit9.i = insertelement <16 x i8> %vecinit8.i, i8 %v1, i32 9699 %vecinit10.i = insertelement <16 x i8> %vecinit9.i, i8 %v1, i32 10700 %vecinit11.i = insertelement <16 x i8> %vecinit10.i, i8 %v1, i32 11701 %vecinit12.i = insertelement <16 x i8> %vecinit11.i, i8 %v1, i32 12702 %vecinit13.i = insertelement <16 x i8> %vecinit12.i, i8 %v1, i32 13703 %vecinit14.i = insertelement <16 x i8> %vecinit13.i, i8 %v1, i32 14704 %vecinit15.i = insertelement <16 x i8> %vecinit14.i, i8 %v1, i32 15705 ret <16 x i8> %vecinit15.i706}707 708define <8 x i16> @test_vdupq_n_u16(i16 %v1) #0 {709; CHECK-LABEL: test_vdupq_n_u16:710; CHECK: @ %bb.0:711; CHECK-NEXT: vdup.16 q0, r0712; CHECK-NEXT: bx lr713 %vecinit.i = insertelement <8 x i16> undef, i16 %v1, i32 0714 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %v1, i32 1715 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %v1, i32 2716 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %v1, i32 3717 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %v1, i32 4718 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %v1, i32 5719 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %v1, i32 6720 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %v1, i32 7721 ret <8 x i16> %vecinit7.i722}723 724define <4 x i32> @test_vdupq_n_u32(i32 %v1) #0 {725; CHECK-LABEL: test_vdupq_n_u32:726; CHECK: @ %bb.0:727; CHECK-NEXT: vdup.32 q0, r0728; CHECK-NEXT: bx lr729 %vecinit.i = insertelement <4 x i32> undef, i32 %v1, i32 0730 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %v1, i32 1731 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %v1, i32 2732 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %v1, i32 3733 ret <4 x i32> %vecinit3.i734}735 736define <2 x i64> @test_vdupq_n_u64(i64 %v1) #0 {737; CHECK-LABEL: test_vdupq_n_u64:738; CHECK: @ %bb.0:739; CHECK-NEXT: vmov.32 d0[0], r0740; CHECK-NEXT: vmov.32 d0[1], r1741; CHECK-NEXT: vorr d1, d0, d0742; CHECK-NEXT: bx lr743 %vecinit.i = insertelement <2 x i64> undef, i64 %v1, i32 0744 %vecinit1.i = insertelement <2 x i64> %vecinit.i, i64 %v1, i32 1745 ret <2 x i64> %vecinit1.i746}747 748define <8 x i8> @test_vdup_lane_s8(<8 x i8> %v1) #0 {749; CHECK-LABEL: test_vdup_lane_s8:750; CHECK: @ %bb.0:751; CHECK-NEXT: vdup.8 d0, d0[5]752; CHECK-NEXT: bx lr753 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>754 ret <8 x i8> %shuffle755}756 757define <4 x i16> @test_vdup_lane_s16(<4 x i16> %v1) #0 {758; CHECK-LABEL: test_vdup_lane_s16:759; CHECK: @ %bb.0:760; CHECK-NEXT: vdup.16 d0, d0[2]761; CHECK-NEXT: bx lr762 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>763 ret <4 x i16> %shuffle764}765 766define <2 x i32> @test_vdup_lane_s32(<2 x i32> %v1) #0 {767; CHECK-LABEL: test_vdup_lane_s32:768; CHECK: @ %bb.0:769; CHECK-NEXT: vdup.32 d0, d0[1]770; CHECK-NEXT: bx lr771 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <2 x i32> <i32 1, i32 1>772 ret <2 x i32> %shuffle773}774 775define <16 x i8> @test_vdupq_lane_s8(<8 x i8> %v1) #0 {776; CHECK-LABEL: test_vdupq_lane_s8:777; CHECK: @ %bb.0:778; CHECK-NEXT: vdup.8 q0, d0[5]779; CHECK-NEXT: bx lr780 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>781 ret <16 x i8> %shuffle782}783 784define <8 x i16> @test_vdupq_lane_s16(<4 x i16> %v1) #0 {785; CHECK-LABEL: test_vdupq_lane_s16:786; CHECK: @ %bb.0:787; CHECK-NEXT: vdup.16 q0, d0[2]788; CHECK-NEXT: bx lr789 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>790 ret <8 x i16> %shuffle791}792 793define <4 x i32> @test_vdupq_lane_s32(<2 x i32> %v1) #0 {794; CHECK-LABEL: test_vdupq_lane_s32:795; CHECK: @ %bb.0:796; CHECK-NEXT: vdup.32 q0, d0[1]797; CHECK-NEXT: bx lr798 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>799 ret <4 x i32> %shuffle800}801 802define <2 x i64> @test_vdupq_lane_s64(<1 x i64> %v1) #0 {803; CHECK-LABEL: test_vdupq_lane_s64:804; CHECK: @ %bb.0:805; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q0806; CHECK-NEXT: vmov.f64 d1, d0807; CHECK-NEXT: bx lr808 %shuffle = shufflevector <1 x i64> %v1, <1 x i64> undef, <2 x i32> zeroinitializer809 ret <2 x i64> %shuffle810}811 812define <8 x i8> @test_vdup_laneq_s8(<16 x i8> %v1) #0 {813; CHECK-LABEL: test_vdup_laneq_s8:814; CHECK: @ %bb.0:815; CHECK-NEXT: vdup.8 d0, d0[5]816; CHECK-NEXT: bx lr817 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>818 ret <8 x i8> %shuffle819}820 821define <4 x i16> @test_vdup_laneq_s16(<8 x i16> %v1) #0 {822; CHECK-LABEL: test_vdup_laneq_s16:823; CHECK: @ %bb.0:824; CHECK-NEXT: vdup.16 d0, d0[2]825; CHECK-NEXT: bx lr826 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>827 ret <4 x i16> %shuffle828}829 830define <2 x i32> @test_vdup_laneq_s32(<4 x i32> %v1) #0 {831; CHECK-LABEL: test_vdup_laneq_s32:832; CHECK: @ %bb.0:833; CHECK-NEXT: vdup.32 d0, d0[1]834; CHECK-NEXT: bx lr835 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 1, i32 1>836 ret <2 x i32> %shuffle837}838 839define <16 x i8> @test_vdupq_laneq_s8(<16 x i8> %v1) #0 {840; CHECK-LABEL: test_vdupq_laneq_s8:841; CHECK: @ %bb.0:842; CHECK-NEXT: vdup.8 q0, d0[5]843; CHECK-NEXT: bx lr844 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>845 ret <16 x i8> %shuffle846}847 848define <8 x i16> @test_vdupq_laneq_s16(<8 x i16> %v1) #0 {849; CHECK-LABEL: test_vdupq_laneq_s16:850; CHECK: @ %bb.0:851; CHECK-NEXT: vdup.16 q0, d0[2]852; CHECK-NEXT: bx lr853 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>854 ret <8 x i16> %shuffle855}856 857define <4 x i32> @test_vdupq_laneq_s32(<4 x i32> %v1) #0 {858; CHECK-LABEL: test_vdupq_laneq_s32:859; CHECK: @ %bb.0:860; CHECK-NEXT: vdup.32 q0, d0[1]861; CHECK-NEXT: bx lr862 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>863 ret <4 x i32> %shuffle864}865 866define <2 x i64> @test_vdupq_laneq_s64(<2 x i64> %v1) #0 {867; CHECK-LABEL: test_vdupq_laneq_s64:868; CHECK: @ %bb.0:869; CHECK-NEXT: vmov.f64 d1, d0870; CHECK-NEXT: bx lr871 %shuffle = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer872 ret <2 x i64> %shuffle873}874 875define i64 @test_bitcastv8i8toi64(<8 x i8> %in) {876; CHECK-LABEL: test_bitcastv8i8toi64:877; CHECK: @ %bb.0:878; CHECK-NEXT: vmov r0, r1, d0879; CHECK-NEXT: bx lr880 %res = bitcast <8 x i8> %in to i64881 ret i64 %res882}883 884define i64 @test_bitcastv4i16toi64(<4 x i16> %in) {885; CHECK-LABEL: test_bitcastv4i16toi64:886; CHECK: @ %bb.0:887; CHECK-NEXT: vmov r0, r1, d0888; CHECK-NEXT: bx lr889 %res = bitcast <4 x i16> %in to i64890 ret i64 %res891}892 893define i64 @test_bitcastv2i32toi64(<2 x i32> %in) {894; CHECK-LABEL: test_bitcastv2i32toi64:895; CHECK: @ %bb.0:896; CHECK-NEXT: vmov r0, r1, d0897; CHECK-NEXT: bx lr898 %res = bitcast <2 x i32> %in to i64899 ret i64 %res900}901 902define i64 @test_bitcastv2f32toi64(<2 x float> %in) {903; CHECK-LABEL: test_bitcastv2f32toi64:904; CHECK: @ %bb.0:905; CHECK-NEXT: vmov r0, r1, d0906; CHECK-NEXT: bx lr907 %res = bitcast <2 x float> %in to i64908 ret i64 %res909}910 911define i64 @test_bitcastv1i64toi64(<1 x i64> %in) {912; CHECK-LABEL: test_bitcastv1i64toi64:913; CHECK: @ %bb.0:914; CHECK-NEXT: vmov r0, r1, d0915; CHECK-NEXT: bx lr916 %res = bitcast <1 x i64> %in to i64917 ret i64 %res918}919 920define i64 @test_bitcastv1f64toi64(<1 x double> %in) {921; CHECK-LABEL: test_bitcastv1f64toi64:922; CHECK: @ %bb.0:923; CHECK-NEXT: vmov r0, r1, d0924; CHECK-NEXT: bx lr925 %res = bitcast <1 x double> %in to i64926 ret i64 %res927}928 929define <8 x i8> @test_bitcasti64tov8i8(i64 %in) {930; CHECK-LABEL: test_bitcasti64tov8i8:931; CHECK: @ %bb.0:932; CHECK-NEXT: vmov d0, r0, r1933; CHECK-NEXT: bx lr934 %res = bitcast i64 %in to <8 x i8>935 ret <8 x i8> %res936}937 938define <4 x i16> @test_bitcasti64tov4i16(i64 %in) {939; CHECK-LABEL: test_bitcasti64tov4i16:940; CHECK: @ %bb.0:941; CHECK-NEXT: vmov d0, r0, r1942; CHECK-NEXT: bx lr943 %res = bitcast i64 %in to <4 x i16>944 ret <4 x i16> %res945}946 947define <2 x i32> @test_bitcasti64tov2i32(i64 %in) {948; CHECK-LABEL: test_bitcasti64tov2i32:949; CHECK: @ %bb.0:950; CHECK-NEXT: vmov d0, r0, r1951; CHECK-NEXT: bx lr952 %res = bitcast i64 %in to <2 x i32>953 ret <2 x i32> %res954}955 956define <2 x float> @test_bitcasti64tov2f32(i64 %in) {957; CHECK-LABEL: test_bitcasti64tov2f32:958; CHECK: @ %bb.0:959; CHECK-NEXT: vmov d0, r0, r1960; CHECK-NEXT: bx lr961 %res = bitcast i64 %in to <2 x float>962 ret <2 x float> %res963}964 965define <1 x i64> @test_bitcasti64tov1i64(i64 %in) {966; CHECK-LABEL: test_bitcasti64tov1i64:967; CHECK: @ %bb.0:968; CHECK-NEXT: vmov d0, r0, r1969; CHECK-NEXT: bx lr970 %res = bitcast i64 %in to <1 x i64>971 ret <1 x i64> %res972}973 974define <1 x double> @test_bitcasti64tov1f64(i64 %in) {975; CHECK-LABEL: test_bitcasti64tov1f64:976; CHECK: @ %bb.0:977; CHECK-NEXT: vmov d0, r0, r1978; CHECK-NEXT: bx lr979 %res = bitcast i64 %in to <1 x double>980 ret <1 x double> %res981}982 983define <1 x i64> @test_bitcastv8i8tov1f64(<8 x i8> %a) #0 {984; CHECK-LABEL: test_bitcastv8i8tov1f64:985; CHECK: @ %bb.0:986; CHECK-NEXT: .save {r11, lr}987; CHECK-NEXT: push {r11, lr}988; CHECK-NEXT: vneg.s8 d16, d0989; CHECK-NEXT: vmov r0, r1, d16990; CHECK-NEXT: bl __aeabi_d2lz991; CHECK-NEXT: vmov.32 d0[0], r0992; CHECK-NEXT: vmov.32 d0[1], r1993; CHECK-NEXT: pop {r11, pc}994 %sub.i = sub <8 x i8> zeroinitializer, %a995 %1 = bitcast <8 x i8> %sub.i to <1 x double>996 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>997 ret <1 x i64> %vcvt.i998}999 1000define <1 x i64> @test_bitcastv4i16tov1f64(<4 x i16> %a) #0 {1001; CHECK-LABEL: test_bitcastv4i16tov1f64:1002; CHECK: @ %bb.0:1003; CHECK-NEXT: .save {r11, lr}1004; CHECK-NEXT: push {r11, lr}1005; CHECK-NEXT: vneg.s16 d16, d01006; CHECK-NEXT: vmov r0, r1, d161007; CHECK-NEXT: bl __aeabi_d2lz1008; CHECK-NEXT: vmov.32 d0[0], r01009; CHECK-NEXT: vmov.32 d0[1], r11010; CHECK-NEXT: pop {r11, pc}1011 %sub.i = sub <4 x i16> zeroinitializer, %a1012 %1 = bitcast <4 x i16> %sub.i to <1 x double>1013 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1014 ret <1 x i64> %vcvt.i1015}1016 1017define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 {1018; CHECK-LABEL: test_bitcastv2i32tov1f64:1019; CHECK: @ %bb.0:1020; CHECK-NEXT: .save {r11, lr}1021; CHECK-NEXT: push {r11, lr}1022; CHECK-NEXT: vneg.s32 d16, d01023; CHECK-NEXT: vmov r0, r1, d161024; CHECK-NEXT: bl __aeabi_d2lz1025; CHECK-NEXT: vmov.32 d0[0], r01026; CHECK-NEXT: vmov.32 d0[1], r11027; CHECK-NEXT: pop {r11, pc}1028 %sub.i = sub <2 x i32> zeroinitializer, %a1029 %1 = bitcast <2 x i32> %sub.i to <1 x double>1030 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1031 ret <1 x i64> %vcvt.i1032}1033 1034define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 {1035; CHECK-LABEL: test_bitcastv1i64tov1f64:1036; CHECK: @ %bb.0:1037; CHECK-NEXT: .save {r11, lr}1038; CHECK-NEXT: push {r11, lr}1039; CHECK-NEXT: vmov.i32 d16, #0x01040; CHECK-NEXT: vsub.i64 d16, d16, d01041; CHECK-NEXT: vmov r0, r1, d161042; CHECK-NEXT: bl __aeabi_d2lz1043; CHECK-NEXT: vmov.32 d0[0], r01044; CHECK-NEXT: vmov.32 d0[1], r11045; CHECK-NEXT: pop {r11, pc}1046 %sub.i = sub <1 x i64> zeroinitializer, %a1047 %1 = bitcast <1 x i64> %sub.i to <1 x double>1048 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1049 ret <1 x i64> %vcvt.i1050}1051 1052define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 {1053; CHECK-LABEL: test_bitcastv2f32tov1f64:1054; CHECK: @ %bb.0:1055; CHECK-NEXT: .save {r11, lr}1056; CHECK-NEXT: push {r11, lr}1057; CHECK-NEXT: vneg.f32 d16, d01058; CHECK-NEXT: vmov r0, r1, d161059; CHECK-NEXT: bl __aeabi_d2lz1060; CHECK-NEXT: vmov.32 d0[0], r01061; CHECK-NEXT: vmov.32 d0[1], r11062; CHECK-NEXT: pop {r11, pc}1063 %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %a1064 %1 = bitcast <2 x float> %sub.i to <1 x double>1065 %vcvt.i = fptosi <1 x double> %1 to <1 x i64>1066 ret <1 x i64> %vcvt.i1067}1068 1069define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 {1070; CHECK-LABEL: test_bitcastv1f64tov8i8:1071; CHECK: @ %bb.0:1072; CHECK-NEXT: .save {r11, lr}1073; CHECK-NEXT: push {r11, lr}1074; CHECK-NEXT: vmov.32 r0, d0[0]1075; CHECK-NEXT: vmov.32 r1, d0[1]1076; CHECK-NEXT: bl __aeabi_l2d1077; CHECK-NEXT: vmov d16, r0, r11078; CHECK-NEXT: vneg.s8 d0, d161079; CHECK-NEXT: pop {r11, pc}1080 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1081 %1 = bitcast <1 x double> %vcvt.i to <8 x i8>1082 %sub.i = sub <8 x i8> zeroinitializer, %11083 ret <8 x i8> %sub.i1084}1085 1086define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 {1087; CHECK-LABEL: test_bitcastv1f64tov4i16:1088; CHECK: @ %bb.0:1089; CHECK-NEXT: .save {r11, lr}1090; CHECK-NEXT: push {r11, lr}1091; CHECK-NEXT: vmov.32 r0, d0[0]1092; CHECK-NEXT: vmov.32 r1, d0[1]1093; CHECK-NEXT: bl __aeabi_l2d1094; CHECK-NEXT: vmov d16, r0, r11095; CHECK-NEXT: vneg.s16 d0, d161096; CHECK-NEXT: pop {r11, pc}1097 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1098 %1 = bitcast <1 x double> %vcvt.i to <4 x i16>1099 %sub.i = sub <4 x i16> zeroinitializer, %11100 ret <4 x i16> %sub.i1101}1102 1103define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 {1104; CHECK-LABEL: test_bitcastv1f64tov2i32:1105; CHECK: @ %bb.0:1106; CHECK-NEXT: .save {r11, lr}1107; CHECK-NEXT: push {r11, lr}1108; CHECK-NEXT: vmov.32 r0, d0[0]1109; CHECK-NEXT: vmov.32 r1, d0[1]1110; CHECK-NEXT: bl __aeabi_l2d1111; CHECK-NEXT: vmov d16, r0, r11112; CHECK-NEXT: vneg.s32 d0, d161113; CHECK-NEXT: pop {r11, pc}1114 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1115 %1 = bitcast <1 x double> %vcvt.i to <2 x i32>1116 %sub.i = sub <2 x i32> zeroinitializer, %11117 ret <2 x i32> %sub.i1118}1119 1120define <1 x i64> @test_bitcastv1f64tov1i64(<1 x i64> %a) #0 {1121; CHECK-LABEL: test_bitcastv1f64tov1i64:1122; CHECK: @ %bb.0:1123; CHECK-NEXT: .save {r11, lr}1124; CHECK-NEXT: push {r11, lr}1125; CHECK-NEXT: vmov.32 r0, d0[0]1126; CHECK-NEXT: vmov.32 r1, d0[1]1127; CHECK-NEXT: bl __aeabi_l2d1128; CHECK-NEXT: vmov.i32 d16, #0x01129; CHECK-NEXT: vmov d17, r0, r11130; CHECK-NEXT: vsub.i64 d0, d16, d171131; CHECK-NEXT: pop {r11, pc}1132 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1133 %1 = bitcast <1 x double> %vcvt.i to <1 x i64>1134 %sub.i = sub <1 x i64> zeroinitializer, %11135 ret <1 x i64> %sub.i1136}1137 1138define <2 x float> @test_bitcastv1f64tov2f32(<1 x i64> %a) #0 {1139; CHECK-LABEL: test_bitcastv1f64tov2f32:1140; CHECK: @ %bb.0:1141; CHECK-NEXT: .save {r11, lr}1142; CHECK-NEXT: push {r11, lr}1143; CHECK-NEXT: vmov.32 r0, d0[0]1144; CHECK-NEXT: vmov.32 r1, d0[1]1145; CHECK-NEXT: bl __aeabi_l2d1146; CHECK-NEXT: vmov d16, r0, r11147; CHECK-NEXT: vneg.f32 d0, d161148; CHECK-NEXT: pop {r11, pc}1149 %vcvt.i = sitofp <1 x i64> %a to <1 x double>1150 %1 = bitcast <1 x double> %vcvt.i to <2 x float>1151 %sub.i = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %11152 ret <2 x float> %sub.i1153}1154 1155; Test insert element into an undef vector1156define <8 x i8> @scalar_to_vector_v8i8(i8 %a) {1157; CHECK-LABEL: scalar_to_vector_v8i8:1158; CHECK: @ %bb.0:1159; CHECK-NEXT: vmov.8 d0[0], r01160; CHECK-NEXT: bx lr1161 %b = insertelement <8 x i8> undef, i8 %a, i32 01162 ret <8 x i8> %b1163}1164 1165define <16 x i8> @scalar_to_vector_v16i8(i8 %a) {1166; CHECK-LABEL: scalar_to_vector_v16i8:1167; CHECK: @ %bb.0:1168; CHECK-NEXT: vmov.8 d0[0], r01169; CHECK-NEXT: bx lr1170 %b = insertelement <16 x i8> undef, i8 %a, i32 01171 ret <16 x i8> %b1172}1173 1174define <4 x i16> @scalar_to_vector_v4i16(i16 %a) {1175; CHECK-LABEL: scalar_to_vector_v4i16:1176; CHECK: @ %bb.0:1177; CHECK-NEXT: vmov.16 d0[0], r01178; CHECK-NEXT: bx lr1179 %b = insertelement <4 x i16> undef, i16 %a, i32 01180 ret <4 x i16> %b1181}1182 1183define <8 x i16> @scalar_to_vector_v8i16(i16 %a) {1184; CHECK-LABEL: scalar_to_vector_v8i16:1185; CHECK: @ %bb.0:1186; CHECK-NEXT: vmov.16 d0[0], r01187; CHECK-NEXT: bx lr1188 %b = insertelement <8 x i16> undef, i16 %a, i32 01189 ret <8 x i16> %b1190}1191 1192define <2 x i32> @scalar_to_vector_v2i32(i32 %a) {1193; CHECK-LABEL: scalar_to_vector_v2i32:1194; CHECK: @ %bb.0:1195; CHECK-NEXT: vmov.32 d0[0], r01196; CHECK-NEXT: bx lr1197 %b = insertelement <2 x i32> undef, i32 %a, i32 01198 ret <2 x i32> %b1199}1200 1201define <4 x i32> @scalar_to_vector_v4i32(i32 %a) {1202; CHECK-LABEL: scalar_to_vector_v4i32:1203; CHECK: @ %bb.0:1204; CHECK-NEXT: vmov.32 d0[0], r01205; CHECK-NEXT: bx lr1206 %b = insertelement <4 x i32> undef, i32 %a, i32 01207 ret <4 x i32> %b1208}1209 1210define <2 x i64> @scalar_to_vector_v2i64(i64 %a) {1211; CHECK-LABEL: scalar_to_vector_v2i64:1212; CHECK: @ %bb.0:1213; CHECK-NEXT: vmov.32 d0[0], r01214; CHECK-NEXT: vmov.32 d0[1], r11215; CHECK-NEXT: bx lr1216 %b = insertelement <2 x i64> undef, i64 %a, i32 01217 ret <2 x i64> %b1218}1219 1220define <8 x i8> @testDUPv1i8(<1 x i8> %a) {1221; CHECK-LABEL: testDUPv1i8:1222; CHECK: @ %bb.0:1223; CHECK-NEXT: vdup.8 d0, r01224; CHECK-NEXT: bx lr1225 %b = extractelement <1 x i8> %a, i32 01226 %c = insertelement <8 x i8> undef, i8 %b, i32 01227 %d = insertelement <8 x i8> %c, i8 %b, i32 11228 %e = insertelement <8 x i8> %d, i8 %b, i32 21229 %f = insertelement <8 x i8> %e, i8 %b, i32 31230 %g = insertelement <8 x i8> %f, i8 %b, i32 41231 %h = insertelement <8 x i8> %g, i8 %b, i32 51232 %i = insertelement <8 x i8> %h, i8 %b, i32 61233 %j = insertelement <8 x i8> %i, i8 %b, i32 71234 ret <8 x i8> %j1235}1236 1237define <8 x i16> @testDUPv1i16(<1 x i16> %a) {1238; CHECK-LABEL: testDUPv1i16:1239; CHECK: @ %bb.0:1240; CHECK-NEXT: vdup.16 q0, r01241; CHECK-NEXT: bx lr1242 %b = extractelement <1 x i16> %a, i32 01243 %c = insertelement <8 x i16> undef, i16 %b, i32 01244 %d = insertelement <8 x i16> %c, i16 %b, i32 11245 %e = insertelement <8 x i16> %d, i16 %b, i32 21246 %f = insertelement <8 x i16> %e, i16 %b, i32 31247 %g = insertelement <8 x i16> %f, i16 %b, i32 41248 %h = insertelement <8 x i16> %g, i16 %b, i32 51249 %i = insertelement <8 x i16> %h, i16 %b, i32 61250 %j = insertelement <8 x i16> %i, i16 %b, i32 71251 ret <8 x i16> %j1252}1253 1254define <4 x i32> @testDUPv1i32(<1 x i32> %a) {1255; CHECK-LABEL: testDUPv1i32:1256; CHECK: @ %bb.0:1257; CHECK-NEXT: vdup.32 q0, r01258; CHECK-NEXT: bx lr1259 %b = extractelement <1 x i32> %a, i32 01260 %c = insertelement <4 x i32> undef, i32 %b, i32 01261 %d = insertelement <4 x i32> %c, i32 %b, i32 11262 %e = insertelement <4 x i32> %d, i32 %b, i32 21263 %f = insertelement <4 x i32> %e, i32 %b, i32 31264 ret <4 x i32> %f1265}1266 1267define <8 x i8> @getl(<16 x i8> %x) #0 {1268; CHECK-LABEL: getl:1269; CHECK: @ %bb.0:1270; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q01271; CHECK-NEXT: bx lr1272 %vecext = extractelement <16 x i8> %x, i32 01273 %vecinit = insertelement <8 x i8> undef, i8 %vecext, i32 01274 %vecext1 = extractelement <16 x i8> %x, i32 11275 %vecinit2 = insertelement <8 x i8> %vecinit, i8 %vecext1, i32 11276 %vecext3 = extractelement <16 x i8> %x, i32 21277 %vecinit4 = insertelement <8 x i8> %vecinit2, i8 %vecext3, i32 21278 %vecext5 = extractelement <16 x i8> %x, i32 31279 %vecinit6 = insertelement <8 x i8> %vecinit4, i8 %vecext5, i32 31280 %vecext7 = extractelement <16 x i8> %x, i32 41281 %vecinit8 = insertelement <8 x i8> %vecinit6, i8 %vecext7, i32 41282 %vecext9 = extractelement <16 x i8> %x, i32 51283 %vecinit10 = insertelement <8 x i8> %vecinit8, i8 %vecext9, i32 51284 %vecext11 = extractelement <16 x i8> %x, i32 61285 %vecinit12 = insertelement <8 x i8> %vecinit10, i8 %vecext11, i32 61286 %vecext13 = extractelement <16 x i8> %x, i32 71287 %vecinit14 = insertelement <8 x i8> %vecinit12, i8 %vecext13, i32 71288 ret <8 x i8> %vecinit141289}1290 1291define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) {1292; CHECK-LABEL: test_extracts_inserts_varidx_extract:1293; CHECK: @ %bb.0:1294; CHECK-NEXT: .save {r11}1295; CHECK-NEXT: push {r11}1296; CHECK-NEXT: .setfp r11, sp1297; CHECK-NEXT: mov r11, sp1298; CHECK-NEXT: .pad #281299; CHECK-NEXT: sub sp, sp, #281300; CHECK-NEXT: bfc sp, #0, #41301; CHECK-NEXT: vmov.u16 r1, d0[1]1302; CHECK-NEXT: and r0, r0, #71303; CHECK-NEXT: vmov.u16 r2, d0[2]1304; CHECK-NEXT: mov r3, sp1305; CHECK-NEXT: vmov.u16 r12, d0[3]1306; CHECK-NEXT: lsl r0, r0, #11307; CHECK-NEXT: vst1.64 {d0, d1}, [r3:128], r01308; CHECK-NEXT: vld1.16 {d0[0]}, [r3:16]1309; CHECK-NEXT: vmov.16 d0[1], r11310; CHECK-NEXT: vmov.16 d0[2], r21311; CHECK-NEXT: vmov.16 d0[3], r121312; CHECK-NEXT: mov sp, r111313; CHECK-NEXT: pop {r11}1314; CHECK-NEXT: bx lr1315 %tmp = extractelement <8 x i16> %x, i32 %idx1316 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 01317 %tmp3 = extractelement <8 x i16> %x, i32 11318 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 11319 %tmp5 = extractelement <8 x i16> %x, i32 21320 %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 21321 %tmp7 = extractelement <8 x i16> %x, i32 31322 %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 31323 ret <4 x i16> %tmp81324}1325 1326define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) {1327; CHECK-LABEL: test_extracts_inserts_varidx_insert:1328; CHECK: @ %bb.0:1329; CHECK-NEXT: .pad #81330; CHECK-NEXT: sub sp, sp, #81331; CHECK-NEXT: vmov.u16 r1, d0[1]1332; CHECK-NEXT: and r0, r0, #31333; CHECK-NEXT: vmov.u16 r2, d0[2]1334; CHECK-NEXT: mov r3, sp1335; CHECK-NEXT: vmov.u16 r12, d0[3]1336; CHECK-NEXT: orr r0, r3, r0, lsl #11337; CHECK-NEXT: vst1.16 {d0[0]}, [r0:16]1338; CHECK-NEXT: vldr d0, [sp]1339; CHECK-NEXT: vmov.16 d0[1], r11340; CHECK-NEXT: vmov.16 d0[2], r21341; CHECK-NEXT: vmov.16 d0[3], r121342; CHECK-NEXT: add sp, sp, #81343; CHECK-NEXT: bx lr1344 %tmp = extractelement <8 x i16> %x, i32 01345 %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx1346 %tmp3 = extractelement <8 x i16> %x, i32 11347 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 11348 %tmp5 = extractelement <8 x i16> %x, i32 21349 %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 21350 %tmp7 = extractelement <8 x i16> %x, i32 31351 %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 31352 ret <4 x i16> %tmp81353}1354 1355define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) {1356; CHECK-LABEL: test_dup_v2i32_v4i16:1357; CHECK: @ %bb.0: @ %entry1358; CHECK-NEXT: vmov.32 r0, d0[1]1359; CHECK-NEXT: vmov.16 d16[1], r01360; CHECK-NEXT: vdup.16 d0, d16[1]1361; CHECK-NEXT: bx lr1362entry:1363 %x = extractelement <2 x i32> %a, i32 11364 %vget_lane = trunc i32 %x to i161365 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01366 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11367 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21368 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31369 ret <4 x i16> %vecinit3.i1370}1371 1372define <8 x i16> @test_dup_v4i32_v8i16(<4 x i32> %a) {1373; CHECK-LABEL: test_dup_v4i32_v8i16:1374; CHECK: @ %bb.0: @ %entry1375; CHECK-NEXT: vmov.32 r0, d1[1]1376; CHECK-NEXT: vmov.16 d16[3], r01377; CHECK-NEXT: vdup.16 q0, d16[3]1378; CHECK-NEXT: bx lr1379entry:1380 %x = extractelement <4 x i32> %a, i32 31381 %vget_lane = trunc i32 %x to i161382 %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 01383 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 11384 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 21385 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 31386 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 41387 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 51388 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 61389 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 71390 ret <8 x i16> %vecinit7.i1391}1392 1393define <4 x i16> @test_dup_v1i64_v4i16(<1 x i64> %a) {1394; CHECK-LABEL: test_dup_v1i64_v4i16:1395; CHECK: @ %bb.0: @ %entry1396; CHECK-NEXT: vmov.32 r0, d0[0]1397; CHECK-NEXT: vmov.16 d16[0], r01398; CHECK-NEXT: vdup.16 d0, d16[0]1399; CHECK-NEXT: bx lr1400entry:1401 %x = extractelement <1 x i64> %a, i32 01402 %vget_lane = trunc i64 %x to i161403 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01404 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11405 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21406 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31407 ret <4 x i16> %vecinit3.i1408}1409 1410define <2 x i32> @test_dup_v1i64_v2i32(<1 x i64> %a) {1411; CHECK-LABEL: test_dup_v1i64_v2i32:1412; CHECK: @ %bb.0: @ %entry1413; CHECK-NEXT: vdup.32 d0, d0[0]1414; CHECK-NEXT: bx lr1415entry:1416 %x = extractelement <1 x i64> %a, i32 01417 %vget_lane = trunc i64 %x to i321418 %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 01419 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 11420 ret <2 x i32> %vecinit1.i1421}1422 1423define <8 x i16> @test_dup_v2i64_v8i16(<2 x i64> %a) {1424; CHECK-LABEL: test_dup_v2i64_v8i16:1425; CHECK: @ %bb.0: @ %entry1426; CHECK-NEXT: vmov.32 r0, d1[0]1427; CHECK-NEXT: vmov.16 d16[2], r01428; CHECK-NEXT: vdup.16 q0, d16[2]1429; CHECK-NEXT: bx lr1430entry:1431 %x = extractelement <2 x i64> %a, i32 11432 %vget_lane = trunc i64 %x to i161433 %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 01434 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 11435 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 21436 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 31437 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 41438 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 51439 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 61440 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 71441 ret <8 x i16> %vecinit7.i1442}1443 1444define <4 x i32> @test_dup_v2i64_v4i32(<2 x i64> %a) {1445; CHECK-LABEL: test_dup_v2i64_v4i32:1446; CHECK: @ %bb.0: @ %entry1447; CHECK-NEXT: vdup.32 q0, d1[0]1448; CHECK-NEXT: bx lr1449entry:1450 %x = extractelement <2 x i64> %a, i32 11451 %vget_lane = trunc i64 %x to i321452 %vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 01453 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 11454 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 21455 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 31456 ret <4 x i32> %vecinit3.i1457}1458 1459define <4 x i16> @test_dup_v4i32_v4i16(<4 x i32> %a) {1460; CHECK-LABEL: test_dup_v4i32_v4i16:1461; CHECK: @ %bb.0: @ %entry1462; CHECK-NEXT: vmov.32 r0, d0[1]1463; CHECK-NEXT: vmov.16 d16[1], r01464; CHECK-NEXT: vdup.16 d0, d16[1]1465; CHECK-NEXT: bx lr1466entry:1467 %x = extractelement <4 x i32> %a, i32 11468 %vget_lane = trunc i32 %x to i161469 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01470 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11471 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21472 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31473 ret <4 x i16> %vecinit3.i1474}1475 1476define <4 x i16> @test_dup_v2i64_v4i16(<2 x i64> %a) {1477; CHECK-LABEL: test_dup_v2i64_v4i16:1478; CHECK: @ %bb.0: @ %entry1479; CHECK-NEXT: vmov.32 r0, d0[0]1480; CHECK-NEXT: vmov.16 d16[0], r01481; CHECK-NEXT: vdup.16 d0, d16[0]1482; CHECK-NEXT: bx lr1483entry:1484 %x = extractelement <2 x i64> %a, i32 01485 %vget_lane = trunc i64 %x to i161486 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 01487 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 11488 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 21489 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 31490 ret <4 x i16> %vecinit3.i1491}1492 1493define <2 x i32> @test_dup_v2i64_v2i32(<2 x i64> %a) {1494; CHECK-LABEL: test_dup_v2i64_v2i32:1495; CHECK: @ %bb.0: @ %entry1496; CHECK-NEXT: vdup.32 d0, d0[0]1497; CHECK-NEXT: bx lr1498entry:1499 %x = extractelement <2 x i64> %a, i32 01500 %vget_lane = trunc i64 %x to i321501 %vecinit.i = insertelement <2 x i32> undef, i32 %vget_lane, i32 01502 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %vget_lane, i32 11503 ret <2 x i32> %vecinit1.i1504}1505 1506define <2 x i32> @test_concat_undef_v1i32(<2 x i32> %a) {1507; CHECK-LABEL: test_concat_undef_v1i32:1508; CHECK: @ %bb.0: @ %entry1509; CHECK-NEXT: vdup.32 d0, d0[0]1510; CHECK-NEXT: bx lr1511entry:1512 %0 = extractelement <2 x i32> %a, i32 01513 %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 11514 ret <2 x i32> %vecinit1.i1515}1516 1517define <2 x i32> @test_concat_same_v1i32_v1i32(<2 x i32> %a) {1518; CHECK-LABEL: test_concat_same_v1i32_v1i32:1519; CHECK: @ %bb.0: @ %entry1520; CHECK-NEXT: vdup.32 d0, d0[0]1521; CHECK-NEXT: bx lr1522entry:1523 %0 = extractelement <2 x i32> %a, i32 01524 %vecinit.i = insertelement <2 x i32> undef, i32 %0, i32 01525 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %0, i32 11526 ret <2 x i32> %vecinit1.i1527}1528 1529 1530define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {1531; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:1532; CHECK: @ %bb.0: @ %entry1533; CHECK-NEXT: vmov.f64 d1, d21534; CHECK-NEXT: bx lr1535entry:1536 %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>1537 ret <16 x i8> %vecinit301538}1539 1540define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {1541; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:1542; CHECK: @ %bb.0: @ %entry1543; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q01544; CHECK-NEXT: vmov.f64 d1, d21545; CHECK-NEXT: bx lr1546entry:1547 %vecext = extractelement <8 x i8> %x, i32 01548 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 01549 %vecext1 = extractelement <8 x i8> %x, i32 11550 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 11551 %vecext3 = extractelement <8 x i8> %x, i32 21552 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 21553 %vecext5 = extractelement <8 x i8> %x, i32 31554 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 31555 %vecext7 = extractelement <8 x i8> %x, i32 41556 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 41557 %vecext9 = extractelement <8 x i8> %x, i32 51558 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 51559 %vecext11 = extractelement <8 x i8> %x, i32 61560 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 61561 %vecext13 = extractelement <8 x i8> %x, i32 71562 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 71563 %vecinit30 = shufflevector <16 x i8> %vecinit14, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>1564 ret <16 x i8> %vecinit301565}1566 1567define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {1568; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:1569; CHECK: @ %bb.0: @ %entry1570; CHECK-NEXT: vmov.f64 d1, d21571; CHECK-NEXT: bx lr1572entry:1573 %vecext = extractelement <16 x i8> %x, i32 01574 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 01575 %vecext1 = extractelement <16 x i8> %x, i32 11576 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 11577 %vecext3 = extractelement <16 x i8> %x, i32 21578 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 21579 %vecext5 = extractelement <16 x i8> %x, i32 31580 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 31581 %vecext7 = extractelement <16 x i8> %x, i32 41582 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 41583 %vecext9 = extractelement <16 x i8> %x, i32 51584 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 51585 %vecext11 = extractelement <16 x i8> %x, i32 61586 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 61587 %vecext13 = extractelement <16 x i8> %x, i32 71588 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 71589 %vecext15 = extractelement <8 x i8> %y, i32 01590 %vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 81591 %vecext17 = extractelement <8 x i8> %y, i32 11592 %vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 91593 %vecext19 = extractelement <8 x i8> %y, i32 21594 %vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 101595 %vecext21 = extractelement <8 x i8> %y, i32 31596 %vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 111597 %vecext23 = extractelement <8 x i8> %y, i32 41598 %vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 121599 %vecext25 = extractelement <8 x i8> %y, i32 51600 %vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 131601 %vecext27 = extractelement <8 x i8> %y, i32 61602 %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 141603 %vecext29 = extractelement <8 x i8> %y, i32 71604 %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 151605 ret <16 x i8> %vecinit301606}1607 1608define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {1609; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:1610; CHECK: @ %bb.0: @ %entry1611; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q01612; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q01613; CHECK-NEXT: bx lr1614entry:1615 %vecext = extractelement <8 x i8> %x, i32 01616 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 01617 %vecext1 = extractelement <8 x i8> %x, i32 11618 %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 11619 %vecext3 = extractelement <8 x i8> %x, i32 21620 %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 21621 %vecext5 = extractelement <8 x i8> %x, i32 31622 %vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 31623 %vecext7 = extractelement <8 x i8> %x, i32 41624 %vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 41625 %vecext9 = extractelement <8 x i8> %x, i32 51626 %vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 51627 %vecext11 = extractelement <8 x i8> %x, i32 61628 %vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 61629 %vecext13 = extractelement <8 x i8> %x, i32 71630 %vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 71631 %vecext15 = extractelement <8 x i8> %y, i32 01632 %vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 81633 %vecext17 = extractelement <8 x i8> %y, i32 11634 %vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 91635 %vecext19 = extractelement <8 x i8> %y, i32 21636 %vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 101637 %vecext21 = extractelement <8 x i8> %y, i32 31638 %vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 111639 %vecext23 = extractelement <8 x i8> %y, i32 41640 %vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 121641 %vecext25 = extractelement <8 x i8> %y, i32 51642 %vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 131643 %vecext27 = extractelement <8 x i8> %y, i32 61644 %vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 141645 %vecext29 = extractelement <8 x i8> %y, i32 71646 %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 151647 ret <16 x i8> %vecinit301648}1649 1650define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {1651; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:1652; CHECK: @ %bb.0: @ %entry1653; CHECK-NEXT: vmov.f64 d1, d21654; CHECK-NEXT: bx lr1655entry:1656 %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>1657 ret <8 x i16> %vecinit141658}1659 1660define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {1661; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:1662; CHECK: @ %bb.0: @ %entry1663; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q01664; CHECK-NEXT: vmov.f64 d1, d21665; CHECK-NEXT: bx lr1666entry:1667 %vecext = extractelement <4 x i16> %x, i32 01668 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 01669 %vecext1 = extractelement <4 x i16> %x, i32 11670 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 11671 %vecext3 = extractelement <4 x i16> %x, i32 21672 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 21673 %vecext5 = extractelement <4 x i16> %x, i32 31674 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 31675 %vecinit14 = shufflevector <8 x i16> %vecinit6, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>1676 ret <8 x i16> %vecinit141677}1678 1679define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {1680; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:1681; CHECK: @ %bb.0: @ %entry1682; CHECK-NEXT: vmov.f64 d1, d21683; CHECK-NEXT: bx lr1684entry:1685 %vecext = extractelement <8 x i16> %x, i32 01686 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 01687 %vecext1 = extractelement <8 x i16> %x, i32 11688 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 11689 %vecext3 = extractelement <8 x i16> %x, i32 21690 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 21691 %vecext5 = extractelement <8 x i16> %x, i32 31692 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 31693 %vecext7 = extractelement <4 x i16> %y, i32 01694 %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 41695 %vecext9 = extractelement <4 x i16> %y, i32 11696 %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 51697 %vecext11 = extractelement <4 x i16> %y, i32 21698 %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 61699 %vecext13 = extractelement <4 x i16> %y, i32 31700 %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 71701 ret <8 x i16> %vecinit141702}1703 1704define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {1705; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:1706; CHECK: @ %bb.0: @ %entry1707; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q01708; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q01709; CHECK-NEXT: bx lr1710entry:1711 %vecext = extractelement <4 x i16> %x, i32 01712 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 01713 %vecext1 = extractelement <4 x i16> %x, i32 11714 %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 11715 %vecext3 = extractelement <4 x i16> %x, i32 21716 %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 21717 %vecext5 = extractelement <4 x i16> %x, i32 31718 %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 31719 %vecext7 = extractelement <4 x i16> %y, i32 01720 %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 41721 %vecext9 = extractelement <4 x i16> %y, i32 11722 %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 51723 %vecext11 = extractelement <4 x i16> %y, i32 21724 %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 61725 %vecext13 = extractelement <4 x i16> %y, i32 31726 %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 71727 ret <8 x i16> %vecinit141728}1729 1730define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {1731; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:1732; CHECK: @ %bb.0: @ %entry1733; CHECK-NEXT: vmov.f64 d1, d21734; CHECK-NEXT: bx lr1735entry:1736 %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>1737 ret <4 x i32> %vecinit61738}1739 1740define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {1741; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:1742; CHECK: @ %bb.0: @ %entry1743; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q01744; CHECK-NEXT: vmov.f64 d1, d21745; CHECK-NEXT: bx lr1746entry:1747 %vecext = extractelement <2 x i32> %x, i32 01748 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 01749 %vecext1 = extractelement <2 x i32> %x, i32 11750 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 11751 %vecinit6 = shufflevector <4 x i32> %vecinit2, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>1752 ret <4 x i32> %vecinit61753}1754 1755define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {1756; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:1757; CHECK: @ %bb.0: @ %entry1758; CHECK-NEXT: vmov.f64 d1, d21759; CHECK-NEXT: bx lr1760entry:1761 %vecext = extractelement <4 x i32> %x, i32 01762 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 01763 %vecext1 = extractelement <4 x i32> %x, i32 11764 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 11765 %vecext3 = extractelement <2 x i32> %y, i32 01766 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 21767 %vecext5 = extractelement <2 x i32> %y, i32 11768 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 31769 ret <4 x i32> %vecinit61770}1771 1772define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {1773; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:1774; CHECK: @ %bb.0: @ %entry1775; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q01776; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q01777; CHECK-NEXT: bx lr1778entry:1779 %vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1780 ret <4 x i32> %vecinit61781}1782 1783define <2 x i64> @test_concat_v2i64_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) #0 {1784; CHECK-LABEL: test_concat_v2i64_v2i64_v2i64:1785; CHECK: @ %bb.0: @ %entry1786; CHECK-NEXT: vmov.f64 d1, d21787; CHECK-NEXT: bx lr1788entry:1789 %vecinit2 = shufflevector <2 x i64> %x, <2 x i64> %y, <2 x i32> <i32 0, i32 2>1790 ret <2 x i64> %vecinit21791}1792 1793define <2 x i64> @test_concat_v2i64_v1i64_v2i64(<1 x i64> %x, <2 x i64> %y) #0 {1794; CHECK-LABEL: test_concat_v2i64_v1i64_v2i64:1795; CHECK: @ %bb.0: @ %entry1796; CHECK-NEXT: @ kill: def $d0 killed $d0 def $q01797; CHECK-NEXT: vmov.f64 d1, d21798; CHECK-NEXT: bx lr1799entry:1800 %vecext = extractelement <1 x i64> %x, i32 01801 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 01802 %vecinit2 = shufflevector <2 x i64> %vecinit, <2 x i64> %y, <2 x i32> <i32 0, i32 2>1803 ret <2 x i64> %vecinit21804}1805 1806define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {1807; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:1808; CHECK: @ %bb.0: @ %entry1809; CHECK-NEXT: vmov.f64 d1, d21810; CHECK-NEXT: bx lr1811entry:1812 %vecext = extractelement <2 x i64> %x, i32 01813 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 01814 %vecext1 = extractelement <1 x i64> %y, i32 01815 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 11816 ret <2 x i64> %vecinit21817}1818 1819define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {1820; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:1821; CHECK: @ %bb.0: @ %entry1822; CHECK-NEXT: @ kill: def $d1 killed $d1 killed $q0 def $q01823; CHECK-NEXT: @ kill: def $d0 killed $d0 killed $q0 def $q01824; CHECK-NEXT: bx lr1825entry:1826 %vecext = extractelement <1 x i64> %x, i32 01827 %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 01828 %vecext1 = extractelement <1 x i64> %y, i32 01829 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 11830 ret <2 x i64> %vecinit21831}1832 1833 1834define <4 x i16> @concat_vector_v4i16_const() {1835; CHECK-LABEL: concat_vector_v4i16_const:1836; CHECK: @ %bb.0:1837; CHECK-NEXT: vmov.i32 d0, #0x01838; CHECK-NEXT: bx lr1839 %r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <4 x i32> zeroinitializer1840 ret <4 x i16> %r1841}1842 1843define <4 x i16> @concat_vector_v4i16_const_one() {1844; CHECK-LABEL: concat_vector_v4i16_const_one:1845; CHECK: @ %bb.0:1846; CHECK-NEXT: vmov.i16 d0, #0x11847; CHECK-NEXT: bx lr1848 %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <4 x i32> zeroinitializer1849 ret <4 x i16> %r1850}1851 1852define <4 x i32> @concat_vector_v4i32_const() {1853; CHECK-LABEL: concat_vector_v4i32_const:1854; CHECK: @ %bb.0:1855; CHECK-NEXT: vmov.i32 q0, #0x01856; CHECK-NEXT: bx lr1857 %r = shufflevector <1 x i32> zeroinitializer, <1 x i32> undef, <4 x i32> zeroinitializer1858 ret <4 x i32> %r1859}1860 1861define <8 x i8> @concat_vector_v8i8_const() {1862; CHECK-LABEL: concat_vector_v8i8_const:1863; CHECK: @ %bb.0:1864; CHECK-NEXT: vmov.i32 d0, #0x01865; CHECK-NEXT: bx lr1866 %r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <8 x i32> zeroinitializer1867 ret <8 x i8> %r1868}1869 1870define <8 x i16> @concat_vector_v8i16_const() {1871; CHECK-LABEL: concat_vector_v8i16_const:1872; CHECK: @ %bb.0:1873; CHECK-NEXT: vmov.i32 q0, #0x01874; CHECK-NEXT: bx lr1875 %r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <8 x i32> zeroinitializer1876 ret <8 x i16> %r1877}1878 1879define <8 x i16> @concat_vector_v8i16_const_one() {1880; CHECK-LABEL: concat_vector_v8i16_const_one:1881; CHECK: @ %bb.0:1882; CHECK-NEXT: vmov.i16 q0, #0x11883; CHECK-NEXT: bx lr1884 %r = shufflevector <1 x i16> <i16 1>, <1 x i16> undef, <8 x i32> zeroinitializer1885 ret <8 x i16> %r1886}1887 1888define <16 x i8> @concat_vector_v16i8_const() {1889; CHECK-LABEL: concat_vector_v16i8_const:1890; CHECK: @ %bb.0:1891; CHECK-NEXT: vmov.i32 q0, #0x01892; CHECK-NEXT: bx lr1893 %r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <16 x i32> zeroinitializer1894 ret <16 x i8> %r1895}1896 1897define <4 x i16> @concat_vector_v4i16(<1 x i16> %a) {1898; CHECK-LABEL: concat_vector_v4i16:1899; CHECK: @ %bb.0:1900; CHECK-NEXT: vdup.16 d0, r01901; CHECK-NEXT: bx lr1902 %r = shufflevector <1 x i16> %a, <1 x i16> undef, <4 x i32> zeroinitializer1903 ret <4 x i16> %r1904}1905 1906define <4 x i32> @concat_vector_v4i32(<1 x i32> %a) {1907; CHECK-LABEL: concat_vector_v4i32:1908; CHECK: @ %bb.0:1909; CHECK-NEXT: vdup.32 q0, r01910; CHECK-NEXT: bx lr1911 %r = shufflevector <1 x i32> %a, <1 x i32> undef, <4 x i32> zeroinitializer1912 ret <4 x i32> %r1913}1914 1915define <8 x i8> @concat_vector_v8i8(<1 x i8> %a) {1916; CHECK-LABEL: concat_vector_v8i8:1917; CHECK: @ %bb.0:1918; CHECK-NEXT: vdup.8 d0, r01919; CHECK-NEXT: bx lr1920 %r = shufflevector <1 x i8> %a, <1 x i8> undef, <8 x i32> zeroinitializer1921 ret <8 x i8> %r1922}1923 1924define <8 x i16> @concat_vector_v8i16(<1 x i16> %a) {1925; CHECK-LABEL: concat_vector_v8i16:1926; CHECK: @ %bb.0:1927; CHECK-NEXT: vdup.16 q0, r01928; CHECK-NEXT: bx lr1929 %r = shufflevector <1 x i16> %a, <1 x i16> undef, <8 x i32> zeroinitializer1930 ret <8 x i16> %r1931}1932 1933define <16 x i8> @concat_vector_v16i8(<1 x i8> %a) {1934; CHECK-LABEL: concat_vector_v16i8:1935; CHECK: @ %bb.0:1936; CHECK-NEXT: vdup.8 q0, r01937; CHECK-NEXT: bx lr1938 %r = shufflevector <1 x i8> %a, <1 x i8> undef, <16 x i32> zeroinitializer1939 ret <16 x i8> %r1940}1941